JP2002366362A - Electronic equipment and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly start a program with a small ROM(read-only memory) capacity to start electronic equipment. SOLUTION: A compressed main body program A606 to be expanded by a CPU(central processing unit) 401 and a compressed main body program B607 to be expanded by a CODEC(coder-decoder) 418 are stored in a ROM 114. When the equipment is started, the compressed main body program A606 is expanded by the CPU 401 and the compressed main body program B607 is expanded by the CODEC 418, and they are arranged on a RAM(random access memory) 116, and the boot sequence where the expanded system program is executed by the CPU 401 is performed. The CODEC 418 can be operated as a bus master of DMA(direct memory access) transfer, and expansion by the CPU 401 and that by the CODEC 418 are executed in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a ROM in which a compressed system program is stored, decompresses the compressed system program and places it on a RAM when the apparatus is started, and executes the decompressed system program by a CPU. And a control method therefor.

[0002]

2. Description of the Related Art Conventionally, in computer systems and various electronic devices (printers and image forming apparatuses), a microprocessor is used as a CPU (central processing unit), a predetermined boot process is performed when power is turned on, and an initial program is stored in a RAM. Load and execute this to launch the system software.

The conventional structure of such an electronic device is as shown in FIG. 9, and as shown in FIG.
16. The CPU 401 includes a CPU 401 and a bus 801 connecting them. When the power is turned on, the CPU 401 uses a predetermined address as a start address and starts a program (boot program) on the ROM 114 connected to the address.

[0004] In an electronic device such as an embedded device having no auxiliary storage device, a boot program (initial program loader) 601 and a compressed main body program 605 are integrated as shown in FIG.
Both the main body of the system program and the main body of the system program are placed on the ROM 114, a boot program is started on the ROM 114, and the temporarily required memory space operates by using the RAM 116.

In recent years, changes in the environment surrounding the electronic equipment industry include increasing the capacity of RAM and reducing the price per capacity. SDRAM (synchronous DRA)
M) and RDRAM (Rambus DRAM) have also appeared.

On the other hand, a ROM is a non-rewritable ROM such as a mask ROM, and a UV-EPROM (Ultra ViVROM) which can be rewritten by irradiation of ultraviolet rays.
olet Erasable Programmable
eROM) and more electrically rewritable E
EPROM (Electrically Erasab)
le Programmable ROM) is also used. However, the EEPROM has disadvantages in that the price per capacity is higher than that of the RAM, there is no very large capacity, and the speed is slow.

Further, in recent years, programs have become larger in scale, and placing the programs as they are on the ROM requires a large amount of expensive ROM, which leads to an increase in equipment cost.

For this reason, as described in Japanese Patent Application Laid-Open No. Hei 5-217005, the main program is stored in a compressed state on a ROM, and the compressed main program is executed by a boot program on the ROM which operates at the time of startup. Is expanded on a RAM, and then a main body program is started. As a result, the device can be operated with a small number of ROMs and a high-speed R
Since the program operates on the AM, an improvement in the speed of the program can be expected.

[0009]

However, in the above-mentioned conventional method, it is necessary to expand the compressed main program on the ROM into the RAM at the time of startup. For this reason, there is a drawback in that there is an overhead of the decompression processing of the main program, and the start is slowed down, as compared with a method in which the main program is started on the ROM in the related art. In addition, since the boot program performs only minimal initialization, the information that can be output to a display device such as a display is often poor, and the state of the device during the expansion of the main program by the user is described. It is difficult to judge.

An object of the present invention is to enable a program to be started at a high speed with a small ROM capacity and to start an electronic device.

[0011]

In order to solve the above-mentioned problems, the present invention has a ROM in which a compressed system program is stored, and expands the compressed system program on the RAM when the apparatus is started up. An electronic apparatus and a control method therefor, wherein a boot sequence in which a placed and decompressed system program is executed by a CPU, and a control method therefor, wherein a first compressed system program decompressed by the CPU and a first decompressed data program decompressed by predetermined data decompression hardware And storing the compressed system program in the ROM and expanding the first compressed system program by the CPU when the apparatus is started, and expanding the second compressed system program by the data decompression hardware. And place the expanded system program in the RAM Employing the configuration to run by the CPU.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the image input / output system is exemplified as an example of an electronic device.

[Overall Configuration] FIG. 1 shows the overall configuration of a control system of an image input / output system according to this embodiment.

In FIG. 1, a reader unit (image input device) 200 optically reads a document image and converts it into image data. The reader unit 200 includes a scanner unit 210 having a function of reading a document, and a document feeding unit 250 having a function of conveying document sheets.

A printer section (image output device) 300 conveys a recording sheet, prints image data thereon as a visible image, and discharges the recording sheet outside the apparatus. The printer unit 300 includes a paper feeding unit 310 having a plurality of types of recording paper cassettes, a marking unit 320 having a function of transferring and fixing image data on recording paper, and a printing unit that sorts and staples printed recording paper, Output unit 33 with the function of outputting to
0.

The control unit 110 is electrically connected to the reader unit 200 and the printer unit 300, and further, via the network 4000, the host computers 4001, 4
002.

The control unit 110 controls the reader unit 200 to read the image data of the original, and
0 is provided to provide a copy function for outputting image data to recording paper by controlling the image data on a recording sheet. Further, the image data read from the reader unit 200 is converted into code data,
Scanner function for transmitting to the host computers 4001 and 4002 through the host computer 4001,
A printer function is provided that converts code data received from the network unit 4002 via the network 4000 into image data and outputs the image data to the printer unit 300. Network 400
Generally, Ethernet (registered trademark) or the like is used as 0.

The operation unit 150 is connected to the control device 110, is constituted by a liquid crystal touch panel, and provides a user interface for operating the image input / output system.

FIG. 2 shows a reader unit 200 and a printer unit 3.
00 shows a cross-sectional configuration. In FIG. 2, a document feeding unit 250 of the reader unit feeds a document one by one sequentially from the top onto the platen glass 211, and discharges the document on the platen glass 211 after the reading operation of the document is completed. When the original is conveyed onto the platen glass 211, the lamp 212 is turned on, and the optical unit 21 is turned on.
3 is started, and the original is exposed and scanned. The reflected light from the original at this time is reflected by mirrors 214, 215, 216,
The light is guided to a CCD image sensor (hereinafter, referred to as a CCD) 218 by a lens 217. Thus, the scanned image of the document is read by the CCD 218.
The image data output from the CCD 218 is transferred to the control device 110 after being subjected to predetermined processing.

The laser driver 321 of the printer unit 300
Drives the laser emitting unit 322, and causes the laser emitting unit 322 to emit laser light modulated by the image data output from the control device 110. The laser light is irradiated on the photosensitive drum 323, and a latent image corresponding to the laser light is formed on the photosensitive drum 323. This photosensitive drum 323
The developer is attached to the latent image portion by the developing device 324.

Then, at a timing synchronized with the start of the laser beam irradiation, a recording sheet is fed from one of the cassettes 311 and 312 and conveyed to the transfer section 325 to record the developer adhered to the photosensitive drum 323. Transfer to paper.
The recording paper carrying the developer is conveyed to the fixing unit 326, and the developer is fixed on the recording paper by the heat and pressure of the fixing unit 326. The recording paper that has passed through the fixing unit 326 is discharged by a discharge roller 327.
The paper discharge unit 330 bundles the discharged recording papers and sorts the recording papers, and staples the sorted recording papers.

When double-sided recording is set,
After the recording paper is conveyed to the discharge roller 327, the rotation direction of the discharge roller 327 is reversed, and the flapper 328 is rotated.
To the re-feeding conveyance path 329. Refeeding conveyance path 32
9 is transferred to the transfer unit 32 at the timing described above.
5 is fed.

[Description of Control Device] Here, the control device 110
Will be described with reference to the block diagram of FIG.

The main controller 111 is mainly composed of a CPU
112, a bus controller 113, and various interface controller circuits.

The CPU 112 and the bus controller 113 control the operation of the control device 110 as a whole.
U112 is from ROM114 to ROM interface1
It operates based on the program read through the CPU 15.

The P received from the host computer
The operation of interpreting DL (page description language) code data and expanding the raster image data is also performed by the CPU 112.
And is processed by software. The bus controller 113 controls data transfer input / output from each interface, and performs arbitration at the time of bus contention and controls DMA data transfer.

The DRAM 116 is connected to the main controller 111 by a DRAM interface 117, and is used as a work area for the operation of the CPU 112 and an area for storing image data.

The network controller 121 for connecting to the network 4000 includes an interface 12
3 is connected to the main controller 111 and the connector 122 is connected to an external network.

An extension connector 124 for connecting an extension board and an I / O control unit 126 are connected to the general-purpose high-speed bus 125.
Is connected. The general-purpose high-speed bus 125 includes a PC
An I bus or the like can be used.

The I / O control unit 126 includes the reader unit 20
0, an asynchronous serial communication controller 127 for transmitting and receiving control commands to and from each CPU of the printer unit 300
Are connected to external interface circuits 140 and 145 via an I / O bus 128.

The panel interface 132 is an LCD
It is connected to the controller 131 and includes an interface for displaying on a liquid crystal screen on the operation unit 150 and a key input interface 130 for inputting hard keys and touch panel keys.

The operation unit 150 has a liquid crystal display unit, a touch panel input device attached on the liquid crystal display unit, and a plurality of hard keys. The signal input by the touch panel or the hard key is the panel interface 1 described above.
The image data is transmitted to the CPU 112 via the LCD interface 32, and the liquid crystal display unit displays the image data sent from the panel interface 132. The liquid crystal display unit displays a function display, image data, and the like in the operation of the image forming apparatus.

The real-time clock module 133
Is used to update / save the date and time managed in the device, and is backed up by the backup battery 134.

The E-IDE interface 161 is for connecting an external storage device. A hard disk or a CD-ROM drive can be connected via this interface to write and read programs and image data.

The connectors 142 and 147 are connected to the reader unit 200 and the printer unit 300, respectively, and are comprised of synchronous serial interfaces 143 and 148 and video interfaces 144 and 149, respectively.

The scanner interface 140 is connected to the reader unit 200 via a connector 142, and is connected to the main controller 1 via a scanner bus 141.
11 and is connected to the image received from the reader unit 200 according to the contents of processing in the subsequent process.
It has a function of performing optimal binarization and performing scaling processing of main scanning and sub-scanning, and further generates a control signal generated based on a video control signal transmitted from the reader unit 200.
It also has a function of outputting to the scanner bus 141.

Data transfer from the scanner bus 141 to the DRAM 116 is controlled by the bus controller 113.

The printer interface 145 is connected to the printer unit 300 via a connector 147, and is connected to the main controller 1 via a printer bus 146.
11 is connected. Printer interface 14
Reference numeral 5 denotes a function of performing a smoothing process on the image data output from the main controller 111 and outputting the image data to the printer unit 300, and a control signal generated based on the video control signal sent from the printer unit 300. 146.

The transfer of the raster image data expanded on the DRAM 116 to the printer unit is controlled by the bus controller 113, and is transmitted via the printer bus 146 and the video interface 149 to the printer unit 30.
DMA transfer to 0 is performed.

[Description of Main Controller] FIG. 4 is a block diagram of the main controller 111.

The CPU core 401 is connected to a system bus bridge (SBB) 402 via a 64-bit processor bus (SC bus). SBB402 is 4
× 4 64-bit cross bus switch, and an SDR provided with a cache memory in addition to the processor core 401.
A memory controller 403 for controlling the AM and ROM is connected to a dedicated local bus (MC bus), and further connected to a G bus 404 as a graphic bus and a B bus 405 as an IO bus, for a total of four buses. Connected to. The SBB 402 is designed to ensure simultaneous parallel connection between these four modules as much as possible. The data compression / decompression unit (c
odec) 418 is also connected via a codec interface.

The G bus 404 is a G bus arbiter (GBA).
A scanner / printer controller (S
PC 408). Also, the B bus 405
It is cooperatively controlled by a bus arbiter (BBA) 407. In addition to the SPC 408, a power management unit (PMU)
409, interrupt controller (IC) 410, U
Serial interface controller (SIC) 411 using ART, USB controller 412, IEEE
It is also connected to a parallel interface controller (PIC) 413 based on E1284, a LAN controller (LANC) 414 using Ethernet, an LCD panel, keys, a general-purpose input / output controller (PC) 415, and a PCI bus interface (PCIC) 416.

An operation panel 417 provided with a display panel and a keyboard is connected to the controller 415.

[Explanation of Interrupt Controller] The interrupt controller 410 is connected to the B bus 405, integrates each functional block in the main controller chip and an interrupt from outside the chip, and has six levels of interrupts supported by the CPU core 401. Redistribute into external interrupts and non-maskable interrupts (NMI). Each functional block includes a power management unit 409, a serial interface controller 411, a USB controller 412, a parallel interface controller 413, an Ethernet controller 414, a general-purpose IO controller 415, a PCI interface controller 416, a scanner / printer controller 408, and the like.

[Explanation of Memory Controller] The memory controller 403 is connected to the MC bus which is a local bus dedicated to the memory controller, and is connected to the synchronous DRAM.
(SDRAM), flash ROM, and ROM.

[Description of System Bus Bridge] SBB4
02 is a B bus (input / output bus), G bus (graphic bus), SC bus (processor local bus), and MC
A multi-channel bidirectional bus bridge that provides interconnection between buses using a cross bus switch. The cross bus switch can simultaneously establish two systems of connections, and realize high-speed data transfer with high parallelism, and is configured as shown in FIG.

The SBB 402 includes a B bus interface 2009 for connecting to the B bus 405 and a G bus 404.
G bus interface 2006 for connecting to the CPU core, a CPU interface slave port 2002 for connecting to the processor core 401, and a memory controller 4
In addition to a memory interface master port 2001 for connecting to the address switch 200 and a CODEC bus interface 2014 for connecting to the compression / decompression unit 418,
3. Including a data switch 2004 for connecting the data bus. Further, a cache invalidation unit 2005 for invalidating the cache memory of the processor core is provided.

[Description of PCI Bus Interface] PC
The I bus interface 416 is a block that interfaces between the B bus, which is a general-purpose IO bus inside the main controller, and the PCI bus, which is an IO bus external to the chip.

[Explanation of G bus arbiter and B bus arbiter] G bus arbitration is a central arbitration system, and has a request signal and a grant signal dedicated to each bus master. This arbiter can program the control method. In addition, as a method of giving priority to the bus masters, all bus masters have the same priority, a fair arbitration mode in which the bus rights are imparted fairly, and the priority of one of the bus masters is raised to use the bus preferentially. Priority arbitration mode can be specified.

The B bus arbiter 407 receives a bus use request of the B bus 405, which is an IO general-purpose bus, and after arbitration, gives use permission to one selected master.
Prohibits two or more masters from accessing the bus at the same time. The arbitration system has three levels of priorities, and a plurality of masters can be assigned to each priority in a programmable manner.

[Configuration of Scanner Controller / Printer Controller] FIG. 11 shows the configuration around the scanner / printer controller 408.

Scanner / Printer Controller 408
Is a block that is connected to the scanner and the printer by the Video interface and interfaces with the internal buses G bus and B bus, and is composed of the following members.

A scanner controller 4302 is connected to the scanner by a video interface, and performs operation control and data transfer control. The following G bus / B bus interface unit (GBI) 4301A is connected by an IF bus, and performs data transfer and register read / write.

Printer controller 4303 The printer controller 4303 is connected to the printer by a video interface, and performs operation control and data transfer control. The GBI4301B is connected to the GBI4301B by an IF bus, and performs data transfer and read / write of a register.

G bus / B bus I / F (GBI) 430
1A, 4301B An interface unit for connecting the scanner controller 4302 and the printer controller 4303 to the G bus or the B bus. The scanner controller 4302 and the printer controller 4303 are independently connected to each other, and are connected to both the G bus and the B bus.

CP bus A bus for directly connecting image data of the scanner and the printer and a synchronization signal for horizontal / vertical synchronization.

[Description of Power Management Unit] The main controller 111 is a large-scale ASIC with a built-in CPU. For this reason, if all the internal logics operate simultaneously, a large amount of heat is generated, and the chip itself may be destroyed. To prevent this, the main controller performs power management for each block, that is, power management, and further monitors the power consumption of the entire chip.

The power management is performed individually by each block. Information on the power consumption of each block is collected in a power management unit (PMU) 409 as a power management level. The PMU 409 sums up the power consumption of each block, and collectively monitors the power consumption of each block of the main controller so that the value does not exceed the limit power consumption.

FIG. 6 is an explanatory diagram showing a memory map of the ROM 114 and the RAM 116.

FIG. 10 is a memory map in the case of the conventional activation method.

The ROM 114 stores a boot program 601 to be started when the system is started and a compressed main body program 605.

The boot program 601 includes a routine 602 for expanding the compressed main program 605 separately from the initialization of the device. There are various compression methods for the compressed main program, but it goes without saying that reversible compression is required for such applications.

The RAM 114 has an area 620 for accommodating the main program and a work area 630 necessary for the operation of the main program.

FIG. 6 is a memory map in the case of the activation method according to the present embodiment.

The ROM 114 stores a boot program 601 started when the system is started and a compressed main program 605.

In this embodiment, the compressed main body program 6
05 is divided into two: a compressed main body program A 606 expanded by the CPU 401 and a compressed main body program B 607 expanded by the CODEC 418.

The area of the compressed main program A 606 has a start address 610 to an end address 611, and the area of the compressed main program B 607 has a start address 612 to an end address 613.

The boot program 601 includes a routine 602 for expanding the compressed main program A separately from the initialization of the device.

The compressed main program A 606 is compressed in a compression format that can be expanded by the expansion routine 602 in the boot program 601.

The compressed main program B 607 is
The DEC 418 is compressed in a decompressible compression format.

There are various compression methods, but the condition is that lossless compression be performed as described above. Compressed main program A606, compressed main program B6
07 may be the same or different.

The RAM 114 has an area 620 for storing the main program. The area 620 can be divided into an area 621 to which the compressed main program A 606 is expanded and an area 622 to which the compressed main program B 607 is expanded. it can. The start address and end address of the area 621 are 625 and 626, and similarly, the start address of the area 622 is 627, and the end address is 628.

FIG. 7 shows a boot sequence by the boot program 601. FIG. 7 (A) shows a conventional boot sequence, and FIGS. 7 (B) and (C) show a boot sequence of this embodiment. Is shown.

First, in the conventional startup sequence, after power is turned on, the CPU 401 starts the boot program 601 on the ROM 114 in FIG. The boot program 601 that has been started is loaded into the ROM 114 by the decompression routine 602.
The compressed main program 605 above is stored in the RAM 116
Start stretching above zero (710). When all the main programs have been expanded (711), the boot program is R
The main program on the AM 116 is started (712).

On the other hand, in the startup sequence of this embodiment,
First, after turning on the power, the CPU 401 starts the boot program 601 on the ROM 114 in FIG. The activated boot program 601 first initializes the CODEC 418 (720).

Next, the ROM is stored in the initialized CODEC 418.
114 is stored in the RAM 11
Then, an instruction is issued to expand the data on 622 of 622 (721).

At the same time as the expansion operation of the CODEC 418, the boot program 601 uses the expansion routine 602 to execute the compressed main program A 606 on the ROM 114.
Is expanded onto 621 of the RAM 116 (722).

After the decompression on the CPU side is completed (723), the boot program 601 checks whether the decompression of the CODEC 418 is completed. The subsequent processing changes depending on which of the expansion on the CPU 401 side and the expansion on the CODEC 418 side is completed earlier.

FIG. 7B shows the case where the expansion on the CPU 401 side is completed first, and FIG. 7C shows the case where the expansion on the CODEC 418 side is completed first.

First, as shown in FIG.
The case where the extension on one side is completed first will be described. CPU40
Even if the decompression of 1 is completed, the main program 620 on the RAM 116 is not ready to be started because the decompression on the CODEC 418 side has not been completed yet (the memory area of the main program B is incomplete).

Therefore, the boot program 601 has the COD
Wait until EC 418 completes decompression. Then, after the expansion of the CODEC 418 is completed (724), that is, when the main program 620 is completely expanded and becomes operable, the boot program 601 activates the main program 620 (725).

On the other hand, as shown in FIG.
If the (418) side has already completed the decompression, the following operation is performed.

The extension on the CODEC 418 side is completed (72).
4 ') After that, the boot program 601 has the CODEC 418
Receives an interrupt notifying that expansion has been completed.
Thereby, the CODEC 418 is added to the boot program 601.
You can know that the program has been decompressed.

Thereafter, the boot program 601 completes the decompression of the main program A which has been decompressed by the decompression routine 602 (723 '). Thereafter, it has been detected that the decompression on the CODEC side has already been completed by the previous interrupt. Therefore, the main program 620 is immediately started (725).

It is desirable that the CODEC 418 can perform a DMA transfer, whereby the CPU issues a compression / decompression command to the CODEC, and then issues a CODEC 41 instruction.
8 can be performed without waiting for the end of the processing of Step 8
The 401 and the CODEC 418 can perform decompression processing of the compressed system program in parallel and independently, so that high-speed activation is possible.

By performing the above processing, according to the present embodiment, the conventional method expands the main program by the CPU alone, whereas the conventional method expands the CODEC (image compression / expansion) which is idle at the time of system startup. (Dedicated circuit) and at the same time, the decompression can be completed in a shorter time than the conventional method, and the main body program can be started (reference numeral 750 in FIG. The time difference between when the program is started and when it is started according to the present invention is shown).

The required capacity of the ROM 114 can be greatly reduced by appropriately selecting the compression / decompression method used for decompression of the CODEC 418 and the compression / decompression method used for decompression of the CPU.
There is room for storing more routines in the ROM 114 than before. Thus, for example, at the time of booting, various kinds of kind monitor displays can be displayed on the operation panel 417 to inform the user of the process being executed, as compared with the conventional system.

The minimum equipment required in the present invention is as shown in FIG. That is, the first compressed system program decompressed by the CPU, the second compressed system program decompressed by the data decompression hardware (CODEC), the ROM 114 storing the decompression program of the CPU, and the compressed system program RAM 11 for decompressing and expanding and executing on it
6, a CPU 401 that executes a boot program, a system program, and a decompression program, a CODEC 418 that decompresses a second compressed system program, and a bus 801 that connects them.

In the above embodiment, the image COD is used.
The system program is extended using EC,
A system program (O) stored in a predetermined storage
S or embedded system software), the hardware used for expanding the system program is not limited to the CODEC for images as in the present embodiment, and any hardware can be used. For example, a CODEC for audio or the like that can perform reversible conversion can be used, or a configuration using a dedicated CODEC for booting the system as in the present embodiment can be considered.

Therefore, in the above embodiment, the image input / output system has been described as an example. However, the system which can implement the present invention is not limited to such an image processing system.
Needless to say, the present invention can be applied to any electronic device as long as it is an electronic device having the hardware shown in FIG.

[0091]

As is apparent from the above, according to the present invention, a ROM having a compressed system program stored therein is provided, and when the apparatus is started, the compressed system program is expanded and arranged in the RAM. And a control method therefor, wherein a first compressed system program decompressed by the CPU and a second compressed system program decompressed by predetermined data decompression hardware are provided. A system program is stored in the ROM, the first compressed system program is decompressed by the CPU when the apparatus is started, and the second compressed system program is decompressed by the data decompression hardware so as to be stored in the RAM. And execute the expanded system program by the CPU. Because it uses a structure that, without requiring a large ROM capacity, the system can be booted program of the electronic apparatus at high speed, there is excellent effect that.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an overall configuration of an image input / output system of an electronic device employing the present invention.

FIG. 2 is a sectional view of a reader unit and a printer unit of the electronic apparatus according to the invention.

FIG. 3 is a block diagram of a control device of the electronic device of the present invention.

FIG. 4 is a block diagram of a main controller of the electronic device of the present invention.

FIG. 5 is a block diagram showing a configuration of a system bus bridge of the electronic device of the present invention.

FIG. 6 is a memory map showing a startup sequence of the electronic device of the present invention.

FIG. 7 is an explanatory diagram showing a control flow of a boot program of the present invention.

FIG. 8 is a block diagram showing a basic configuration of the present invention.

FIG. 9 is a block diagram illustrating a configuration of a conventional electronic device.

FIG. 10 is a memory map diagram showing a startup sequence of a conventional electronic device.

FIG. 11 is a block diagram illustrating a configuration of a scanner / printer controller of the electronic apparatus according to the invention.

[Explanation of symbols]

110 controller 111 main controller 112 CPU 113 bus controller 116 RAM 114 ROM 121 network controller 125 general-purpose high-speed bus 127 start-stop synchronous serial communication controller 131 LCD controller 134 backup battery 140, 145 external interface circuit 141 scanner bus 142, 147 connector 146 printer bus 147 Connector 150 Operation unit 161 E-IDE interface 200 Reader unit 210 Scanner unit 211 Platen glass 213 Optical unit 214, 215, 216 Mirror 217 Lens 218 CCD 250 Document feed unit 300 Printer unit 310 Feed unit 311 Cassette 312 Cassette 320 Marking Unit 321 レThe driver 322 Laser emitting unit 323 Photosensitive drum 324 Developing unit 325 Transfer unit 326 Fixing unit 327 Discharge roller 328 Flapper 329 Re-feeding conveyance path 330 Discharge unit 401 CPU (processor core) 402 SBB 418 CODEC 520 Panel interface 601 Boot program 602 Decompression routine 605 Compressed main program 606 Compressed main program A 607 Compressed main program B 620 Main program 403 Memory controller 404 G bus 405 B bus 406 G bus arbiter (GBA) 407 B bus arbiter (BBA) 408 Scanner / printer controller (SPC) ) 409 Power management unit (PMU) 410 Interrupt controller (IC) 411 Serial interface controller Controller 412 USB controller 413 Parallel interface controller (PI
C) 414 LAN controller (LANC) 415 General-purpose input / output controller (PC) 416 PCI interface controller 418 CODEC (compression / decompression unit) 4001, 4002 Host computer

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) G06F 12/04 530 G06F 12/06 520F 12/06 520 9/06 610J F-term (Reference) 2C061 AP01 AP04 AQ06 HH09 HJ10 HN15 2C087 AA09 AB05 AC08 BC15 BD40 5B060 DA08 MM02 5B076 BB12 5B105 CA00 CA01

Claims (5)

[Claims] 1. An R storing a compressed system program
An electronic device having a OM and performing a boot sequence in which the compressed system program is decompressed and arranged on the RAM when the apparatus is started up, and the decompressed system program is executed by a CPU; A first compressed system program decompressed by a CPU and a second compressed system program decompressed by the data decompression hardware are stored in the ROM, and when the apparatus is started, the first compressed system program is stored by the CPU. An electronic device, wherein a system program is expanded, the second compressed system program is expanded by the data expansion hardware and arranged on the RAM, and the expanded system program is executed by the CPU. 2. The method according to claim 1, wherein the expansion of the first compressed system program by the CPU and the expansion of the second compressed system program by the data expansion hardware are performed in parallel. Electronic equipment. 3. The electronic apparatus according to claim 1, wherein the electronic apparatus is configured as an image processing apparatus that performs predetermined image processing, and the data expansion hardware includes a data expansion circuit that expands image data. . 4. The electronic apparatus according to claim 1, wherein said data decompression hardware comprises a data decompression circuit operable as a bus master. 5. An R storing a compressed system program
A method of controlling an electronic device having an OM, expanding a compressed system program at the time of starting up an apparatus, arranging the compressed system program on a RAM, and executing a boot sequence in which the expanded system program is executed by a CPU, wherein the expanded system program is expanded by the CPU A first compressed system program and a second compressed system program decompressed by predetermined data decompression hardware are stored in the ROM, and when the apparatus is started, the first decompressed system program is decompressed by the CPU. A method of controlling the electronic device, wherein the second decompressed system program is decompressed by the data decompression hardware and arranged on the RAM, and the decompressed system program is executed by the CPU.