JP2002359529A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove the effect of the input gate capacity, which deteriorates the high frequency property of a power amplifier which has a complementary power MOS output stage. SOLUTION: This power amplifier operates, so that the gate capacity of a p-channel power MOSFET 12 can be ignored as the load of a transistor 2 for power amplification by the buffer made of a PNP emitter follower transistor 5. However, the buffer made of the PNP emitter follower transistor 5 brings about the occurrence of a through-current characteristic to a bipolar transistor. In general, this phenomenon is seen conspicuously, when the audio signal is 20 kHz or higher. A capacitor 7 for through-current prevention effectively performs the function of preventing this phenomenon. For the value of the capacitor 7 for through-current prevention, an optimum value exists from the relation among the gate capacity value of an n-channel power MOSFET 9, the gate capacity value of a p-channel power MOSFET 12, and the resistance value of a PNP emitter follower bias. Normally, it is set to a minimum value which can check the through-current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier.

[0002]

2. Description of the Related Art FIG. 6 shows a basic configuration of a conventional power amplifier. In FIG. 6, 101 is a voltage amplification input terminal, 102 is a voltage amplification transistor, 103 is an output stage temperature compensation circuit unit, 104 is a constant current source which is a load of a furnace pressure amplification transistor, 108 is a first gate resistance, 109 Is an N-channel power MOSFET, 110 is a first source resistance, 111 is a second gate resistance, 112 is a P-channel power MOSFET, 113 is a second source resistance,
114 is an output terminal, 115 is a positive power terminal, 116 is a negative power terminal, 117 is an output stage including a voltage amplifier and a power amplifier,
118 is a non-inverted signal input end, 119 is an inverted signal input end,
120 and 121 are first-stage differential transistors; 122 is a constant current source; 123 and 124 are first-stage current mirror loads;
5 is a first stage amplifying unit, 126 is a speaker as a load, 127
Is constituted by a ground end.

First, a non-inverting signal input terminal 118 or an inverting signal input terminal 119 has an output terminal 114 to which negative feedback is applied by an appropriate feedback resistor. Obtains power amplification having a predetermined voltage gain at an output stage 117 including a first-stage amplifier 125, a voltage amplifier, and a power amplifier, and reproduces the amplified power through a speaker 126 connected to an output terminal 114. However, a large waveform distortion tends to occur in a relatively high frequency region of several tens KHz or more due to the gate capacitance of the complementary power MOSFETs 109 and 112. FIG. 5 shows a state of waveform distortion of a conventional power amplifier. That is, a waveform distortion of an output signal with respect to a typical 100 KHz input signal occurs.

For this reason, complementary power MOS
The good high frequency characteristics of the FET have been lost due to the presence of the gate capacitance.

[0005]

In such a power amplifying device, it is required to obtain high-frequency characteristics lost due to the presence of the gate capacitance.

The present invention relates to a complementary power MOS.
It is an object of the present invention to provide a power amplifying device that can eliminate the influence of the gate capacitance of an FET and simultaneously exhibit the high frequency characteristics of a complementary power MOSFET.

[0007]

In order to solve this problem, a power amplifying apparatus according to the present invention comprises an emitter follower transistor having a base connected to a voltage amplifying transistor and an emitter connected to one end of a first gate resistor. An emitter follower bias resistor having one end connected to the emitter end of the emitter follower transistor and the other end connected to the source end, and a capacitor having one end connected to the first gate resistance and the other end connected to the second gate resistance. It consists of and.

Accordingly, the complementary power MO
A characteristic is obtained in which deterioration of the high-frequency power amplification characteristic caused by the gate capacitance of the SFET is prevented.

According to a first aspect of the present invention, there is provided a voltage amplifying transistor for receiving an input signal, an output stage temperature compensating circuit, a series circuit of a constant current source which is a load of the voltage amplifying transistor, A first power MOSFET, a series circuit of a second power MOSFET, and a first power MOSFET.
A first gate resistance connected to the gate of the FET, a first source resistance connected to the source of the first power MOSFET, and a second source resistance connected to the gate of the second power MOSFET.
A second source MOSFET connected to the source of the second power MOSFET, an emitter follower transistor having a base connected to the voltage amplifying transistor, and an emitter connected to one end of the first gate resistor; One end is connected to the emitter of the emitter follower transistor, the other end is connected to an emitter follower bias resistor connected to the source of the first power MOSFET, one end is connected to the first gate resistor, and the other end is connected to the second gate. A power amplifying device comprising: a capacitor connected to a resistor.

By adding an emitter follower transistor, the gate capacity of the complementary power MOSFET constituted by the first and second MOSFETs is reduced. Also, by adding a capacitor connected between the first gate resistance and the second gate resistance and set to an appropriate value, a through current unique to a bipolar transistor generated by adding an emitter follower transistor is generated. Can be prevented. This gives M
It has the effect of exhibiting the original characteristics of the OS.

The invention according to claim 2 is the power amplifying device according to claim 1, wherein the voltage amplifying transistor is an NPN transistor. In this case PNP
The generation of a through current peculiar to a bipolar transistor generated by adding an emitter follower transistor is reduced by adding a capacitor connected between a first gate resistance and a second gate resistance and set to an appropriate value. It has the effect of exhibiting the original characteristics.

The invention according to claim 3 is the power amplifying device according to claim 1, wherein the voltage amplifying transistor is a PNP transistor. In this case NPN
The generation of a through current peculiar to a bipolar transistor generated by adding an emitter follower transistor is reduced by adding a capacitor connected between a first gate resistance and a second gate resistance and set to an appropriate value. It has the effect of exhibiting the original characteristics.

According to a fourth aspect of the present invention, there is provided a voltage amplifying transistor for receiving an input signal, an output stage temperature compensating circuit, a series circuit of a constant current source which is a load of the voltage amplifying transistor, and a first power supply. MOSFET and second power M
Series circuit with OSFET and first power MOSFET
A first gate resistance connected to the gate of
A first source resistance connected to the source of the OSFET; a second gate resistance connected to the gate of the second power MOSFET; a second source resistance connected to the source of the second power MOSFET; A first emitter follower transistor having an emitter connected to one end of the first gate resistor, a base connected to the voltage amplifying transistor, and an emitter connected to one end of the second gate resistor; A second emitter follower transistor, a bias resistor having one end connected to the emitter of the first emitter follower transistor, the other end connected to the emitter of the second emitter follower transistor, and one end connected to the first gate resistor. And a capacitor connected at the other end to the second gate resistor. This is a characteristic power amplifying device.
In this case, the generation of a through current peculiar to the bipolar transistor, which is generated by adding the complementary NPN emitter follower transistor and the PNP emitter follower transistor, is controlled by the appropriate connection between the first gate resistance and the second gate resistance. By adding a capacitor set to an appropriate value, there is an effect that the original characteristics of the MOS are exhibited.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 shows a basic configuration of a power amplifier according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a voltage amplification input terminal; Is a constant current source which is a load of a voltage amplifying transistor, 5 is a PNP emitter follower transistor, 6 is a PNP emitter follower bias resistor, 7 is a through current preventing capacitor, and 8 is a first current source.
, 9 is an N-channel power MOSFET,
10 is a first source resistance, 11 is a second gate resistance, 1
2 is a P-channel power MOSFET, 13 is a second source resistance, 14 is an output terminal, 15 is a positive heater terminal, 16 is a negative power supply terminal, 17 is an output stage including an electric amplifier and a power amplifier. It consists of. 26 is a speaker as a load.
The combination of the N-channel power MOSFET 9 and the P-channel power MOSFET 12 is called a complementary power MOSFET.

The first-stage amplifier shown in FIG. 6 is connected to the power amplifier input terminal 1.

The operation of the power amplifier configured as described above will be described below.

First, a signal that has entered the voltage amplification input terminal 1 is voltage-amplified by the voltage amplification transistor 2.

The output stage temperature compensation circuit unit 3 composed of a transistor, a resistor and a capacitor has an N-channel power M
The DC bias current of the OSFET 9, the PNP emitter follower transistor 5, and the P-channel power MOSFET 12 is set to an appropriate value, and the operation is performed so as to maintain the appropriate value even with a temperature change. Thus, AC operation and D
The C operation operates in synergy. The gate capacitance of the P-channel power MOSFET 12 is reduced by the buffer formed by the PNP emitter follower transistor 5. Therefore, P which is a load of the voltage amplifying transistor 2
The gate capacitance of the channel power MOSFET 12 can be ignored. If there is no emitter follower transistor 5, especially for relatively high signals of several tens KHz or more,
The gate capacitance of the P-channel power MOSFET 12 reaches, for example, 1000 PF. This is a non-negligible impedance load of about 1.6 KΩ at a frequency of 100 KHz when viewed from the voltage amplification transistor 2. However, the emitter follower transistor 5
Is provided, the gate capacitance of the P-channel power MOSFET 12 is reduced to, for example, about 10 PF, especially for relatively high signals of several tens KHz or more. This is a negligible impedance load of about 160 KΩ when viewed from the voltage amplification transistor 2.

As described above, by providing the buffer formed by the PNP emitter follower transistor 5,
The gate capacitance of the P-channel power MOSFET 12 can be reduced, but at the same time, a through current unique to a bipolar transistor is generated. Next, the removal of the through current will be described.

FIG. 4 shows the presence or absence of a through current. That is, FIG. 4A shows a complementary MOSF.
The state where the through current obtainable in the ET output stage is 0 (absent) is shown. FIG. 4B shows a state where there is a through current generated in the complementary bipolar power transistor.

This phenomenon generally occurs when the audio signal is 2
It is remarkably observed at 0 KHz or more. The function of preventing this phenomenon is effectively performed by the through current prevention capacitor 7. The value of the through current prevention capacitor 7 has an optimum value from the relationship between the gate capacitance of the N-channel power MOSFET 9, the gate capacitance of the P-channel power MOSFET 12, and the PNP emitter follower bias resistance. Usually, it is set to the minimum value that can prevent the through current.

As described above, according to the present embodiment, it is possible to obtain a characteristic that prevents deterioration of the high-frequency power amplification characteristic caused by the gate capacitance of the complementary power MOSFET.

(Embodiment 2) Next, FIG. 2 shows a basic configuration of a second embodiment. In FIG. 2, 1 is a voltage amplification input terminal, 2 is a voltage amplification transistor, and 3 is an output stage temperature. Compensation circuit section, 4 is a constant current source which is a load of the furnace pressure amplification transistor, 5 is an NPN emitter follower transistor, 6
Is an NPN emitter follower bias resistor, 7 is a capacitor for preventing a through current, 8 is a first gate resistor, 9 is an N-channel power MOSFET, 10 is a first source resistor, 11 is a second gate resistor, and 12 is a P channel. A power MOSFET 13 includes a second source resistor, 14 an output terminal, 15 a positive power supply terminal, 16 a negative power supply terminal, and 17 an output stage including a voltage amplifier and a power amplifier. 2
Reference numeral 6 denotes a speaker as a load. Also, as in FIG. 1, the first-stage amplifier shown in FIG. 6 is connected to the power amplification input terminal 1. The output stage temperature compensation circuit section 3 has the same configuration as that of FIG.

The second embodiment is different from the first embodiment in that
Since the voltage amplifying transistor 2 is configured as a PNP transistor and the emitter follower transistor 5 is configured as an NPN transistor, the same operation and effect as in the first embodiment can be obtained.

(Embodiment 3) FIG. 3 shows a basic configuration of a third embodiment. In FIG. 3, 1 is a voltage amplification input terminal, 2 is a voltage amplification transistor, and 3 is an output stage temperature compensation. A circuit section, 4 is a constant current source which is a load of a voltage amplifying transistor, 5A and 5B are complementary emitter follower transistors, 6 is a complementary emitter follower bias resistor, 7 is a through current prevention capacitor, 8
Is a first gate resistance, 9 is an N-channel power MOSF
ET, 10 is a first source resistance, 11 is a second gate resistance, 12 is a P-channel power MOSFET, 13 is a second source resistance, 14 is an output terminal, 15 is a positive power supply terminal,
Reference numeral 6 denotes a negative power supply terminal, and reference numeral 17 denotes an output stage including a voltage amplifier and a power amplifier.

The third embodiment is different from the first embodiment in that
Since the emitter follower transistor 5 is configured in place of complementary NPN and PNP transistors composed of 5A and 5B, the same operations and effects as those of the first embodiment can be obtained.

Although the voltage amplifying transistor is shown as a bipolar transistor, the same effect can be expected by replacing it with a MOSFET. Although the buffer transistor is shown as a bipolar transistor, the same effect can be expected by replacing it with a MOSFET.

[0029]

As described above, according to the present invention, it is possible to prevent the deterioration of the high-frequency power amplification characteristics caused by the gate capacitance of the complementary power MOSFET and realize the high-frequency characteristics of the MOSFET with a relatively simple configuration. And an economically advantageous effect can be obtained.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a power amplification device according to a first embodiment of the present invention.

FIG. 2 is a basic configuration diagram of a power amplification device according to a second embodiment of the present invention.

FIG. 3 is a basic configuration diagram of a power amplification device according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a state of presence / absence of a through current;

FIG. 5 is a diagram showing a state of waveform distortion of a conventional power amplifier.

FIG. 6 is a basic configuration diagram of a conventional furnace power amplifying device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Voltage amplification input terminal 2 ... Voltage amplification transistor 3 ... Upper and lower stage temperature compensation circuit part 4 ... Constant current source 5 ... Emitter follower transistor 6 ... Emitter follower bias resistance 7. ..Capacitor for preventing through current 8 ... First gate resistance 9 ... N-channel power MOSFET 10 ... First source resistance 11 ... Second gate resistance 12 ... P-channel power MOSFET 13: second source resistance 14: output terminal 15: positive power supply terminal 16: negative power supply terminal 17: output stage 18 including a voltage amplifier and a power amplifier 18 Inverted signal input terminal 18 ... Inverted signal input terminal 20, 21 ... First stage differential transistor 22 ... Constant current source 23, 24 ... First stage current mirror load 25 ... First stage amplifying unit 26 ... Speaker load 27 Grand end

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J091 AA01 AA18 AA41 CA18 CA61 FA10 HA08 HA10 HA17 HA18 HA25 HA26 HA29 KA00 KA02 KA03 KA05 KA09 KA62 MA01 MA23 TA06 UW09

Claims (4)

[Claims] A series circuit including a voltage amplification transistor (2) for receiving an input signal, an output stage temperature compensation circuit section (3), and a constant current source (4) serving as a load of the voltage amplification transistor; Power MOSFET and second power MOSFET
A first gate resistance (8) connected to the gate of the first power MOSFET, a first source resistance (10) connected to the source of the first power MOSFET, and a second power supply. A second gate resistance (11) connected to the gate of the MOSFET, a second source resistance (13) connected to the source of the second power MOSFET, and a base connected to the voltage amplifying transistor (2); Are connected to one end of a first gate resistor (8), one end is connected to the emitter of the emitter follower transistor (5), and the other end is connected to the source of the first power MOSFET. One end is connected to the first gate resistor (8), and the other end is connected to the second
And a capacitor (7) connected to the gate resistor (11). 2. The power amplifying device according to claim 1, wherein the voltage amplifying transistor is an NPN transistor. 3. The voltage amplification transistor (2) is a PNP transistor.
The power amplifying device according to claim 1, wherein the power amplifying device is a transistor. 4. A series circuit comprising a voltage amplifying transistor (2) for receiving an input signal, an output stage temperature compensating circuit (3), and a constant current source (4) which is a load of the voltage amplifying transistor. Power MOSFET and second power MOSFET
A first gate resistance (8) connected to the gate of the first power MOSFET, a first source resistance (10) connected to the source of the first power MOSFET, and a second power supply. A second gate resistance (11) connected to the gate of the MOSFET, a second source resistance (13) connected to the source of the second power MOSFET, and a base connected to the voltage amplifying transistor (2); Are connected to one end of the first gate resistor (8), a first emitter follower transistor (5B) connected to one end of the first gate resistor (8), the base is connected to the voltage amplifying transistor (2), and the emitter is connected to the second gate resistor (11). A second emitter follower transistor (5A) connected to one end, and a first emitter follower transistor (5B) at one end
A bias resistor (6) having the other end connected to the emitter of the second emitter follower transistor (5A), one end connected to the first gate resistor (8), and the other end connected to the second gate follower transistor (8).
And a capacitor (7) connected to the gate resistor (11).