JP2002359193A - Method and device for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To overcome such a problem that the footprint increases and the maintenance cost increases as the size of a substrate increases because a channel doping device is employed for adding an impurity element to a channel part, and the problem that the crystal structure is broken when a crystalline semicon ductor film is subjected to doping. SOLUTION: Plasma is generated in a reaction chamber having an electrode using Ni and B as a material and an amorphous semiconductor film is exposed to the plasma thus adding a catalytic element for accelerating crystallization and an impurity element for imparting p-type required for attaining a desired threshold to the amorphous semiconductor film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device using a semiconductor film having a crystal structure. In particular, the present invention relates to a method for manufacturing a semiconductor device which requires a step of crystallizing a semiconductor film having an amorphous structure.

[0002]

2. Description of the Related Art As a typical example of a semiconductor element using a semiconductor film, a thin film transistor (TF) is used.
T, hereinafter referred to as TFT). Since a TFT can be formed on a glass substrate, it is currently being actively applied as a switching element provided in a pixel of a liquid crystal display device. In particular, by forming an active layer such as a channel formation region with a semiconductor film having a crystal structure, a shift register or a sampling circuit can be operated at a practical driving frequency using a TFT.

An alternative method of forming a semiconductor film having a crystalline structure (hereinafter referred to as a crystalline semiconductor film) is a technique of forming an amorphous semiconductor film on a glass substrate and then crystallizing the film by laser light irradiation. It has been known. According to this technique, a crystalline semiconductor film of random orientation composed of many crystal grains has been obtained.

On the other hand, the techniques disclosed in JP-A-6-232059 and JP-A-7-130652 are disclosed by using a metal element (typically, nickel) which promotes crystallization of silicon. This makes it possible to form a crystalline silicon film having excellent crystallinity by a heat treatment at about 600 ° C. for about 4 hours. The crystalline semiconductor film manufactured by this technique has a feature that the crystal orientation ratio is relatively high.

When an integrated circuit is formed using TFTs, it is necessary to control a threshold voltage (Vth) in order to obtain a desired switching operation. The threshold voltage (Vth) is an important parameter representing the switching characteristics of the TFT, and a deviation from this expected value causes a problem in circuit operation. However, TFT
Is easily changed by fixed charges in the gate insulating film or impurities in the semiconductor film.

For example, in the case of an n-channel TFT,
There is a problem in that the shift to the negative side results in a normally-on state (a state where the gate voltage is turned on when no gate voltage is applied). In order to prevent this, a means is employed to add an impurity (acceptor) imparting p-type to the channel formation region to shift the threshold voltage to the positive side. This process is also called channel doping, and is an important step in a TFT manufacturing process. Usually, ion implantation or ion doping (a method of implanting ions without mass separation) using a diborane (B ₂ H ₆ ) gas is performed.

[0007]

However, the impurity concentration required for controlling the threshold voltage is 10 ¹⁶ to 10 ¹⁸ / c.
A trace amount of about m ³ is sufficient. However, the method of adding boron (B) to a semiconductor film by ion implantation or ion doping has a problem that it is difficult to control a very small amount of the concentration and damages the semiconductor film. For the purpose of controlling the concentration and reducing the damage, means for forming an insulating film of about 100 nm on the semiconductor film is often adopted. By performing such a doping process, the number of manufacturing steps of the TFT is increased, which causes a cost increase and a problem that the productivity is reduced.

Further, if impurities floating in the air adhere to the surface of the amorphous semiconductor film, the element added at a very small concentration as described above does not work effectively in the semiconductor.

The present invention has been made to solve such a problem, and the TF is used without significantly increasing the number of steps.
An object of the present invention is to provide a technique for more reliably controlling the threshold voltage of T with good reproducibility.

[0010]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the configuration of the present invention provides a reaction chamber equipped with a cathode,
By discharging an inert gas under reduced pressure, a plurality of types of elements contained in the cathode are released by sputtering and added to the amorphous semiconductor film, and thereafter, the amorphous semiconductor film is crystallized. .

One of the elements supplied from the cathode and added to the amorphous semiconductor film is an element capable of promoting crystallization of the amorphous semiconductor film or lowering the crystallization temperature. Fe and C are elements that can provide such an effect.
o, Ni, Ru, Rh, Pd, Os, Ir, Pt, C
There is one or more types selected from u and Au. These elements are hereinafter referred to as catalyst elements. The other is an element for imparting p-type to a semiconductor, such as B (boron), Al, Ga,
Although elements of Group 13 of the periodic rule such as In can be used, B is preferably used.

By adding a catalytic element, the amorphous semiconductor film can be easily crystallized by a heat treatment at 600 ° C. or less. The threshold voltage of the TFT can be controlled by adding a p-type impurity element at a desired concentration in advance. According to the present invention, the step of adding the catalyst element and the impurity element imparting the p-type from the formation of the amorphous semiconductor film can be performed continuously under reduced pressure, and the number of steps is significantly increased. A semiconductor device can be manufactured without performing the above.

The same effect can be obtained by adding the catalyst element and the impurity element imparting p-type simultaneously in the same reaction chamber or separately in different reaction chambers.

In the structure of the present invention, an insulating film of silicon oxide, silicon nitride, silicon oxynitride, or the like may be formed under the amorphous semiconductor film.

On the other hand, the configuration of the semiconductor manufacturing apparatus according to the present invention provides a first reaction chamber for forming an amorphous semiconductor film, a catalyst element for promoting crystallization of the amorphous semiconductor film, and a p-type. A second reaction chamber provided with a cathode containing an impurity element; the substrate can be moved between the first reaction chamber and the second reaction chamber without exposing the substrate to the atmosphere; And a means for introducing an inert gas is connected to the second reaction chamber.

In another configuration, a second reaction chamber for forming an amorphous semiconductor film and a second cathode including a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film are provided. And a second reaction chamber containing an impurity element imparting p-type to the semiconductor.
A third reaction chamber having a negative electrode and a fourth reaction chamber for performing heat treatment, wherein the substrate moves between the first reaction chamber and the fourth reaction chamber without exposing the substrate to the atmosphere. And a means for introducing an inert gas is connected to the second reaction chamber and the third reaction chamber.

In another aspect of the invention, a first reaction chamber for forming an amorphous semiconductor film and a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film are provided. A second reaction chamber, and a third reaction chamber including a second cathode containing an impurity element that imparts p-type to the semiconductor, and a first reaction chamber to a third reaction chamber are provided between the first reaction chamber and the third reaction chamber. , So that the substrate can be moved without exposing the substrate to the atmosphere,
A means for introducing an inert gas is connected to the second reaction chamber and the third reaction chamber.

In another aspect of the invention, a first reaction chamber for forming an amorphous semiconductor film, a catalyst element for promoting crystallization of the amorphous semiconductor film, and an impurity element for imparting p-type are formed. A second reaction chamber having a cathode containing the second reaction chamber; and a third reaction chamber for performing a heat treatment. A substrate is provided between the first reaction chamber, the second reaction chamber, and the third reaction chamber. Are connected so that they can be moved without exposing them to the atmosphere, and a means for introducing an inert gas is connected to the second reaction chamber.

In another aspect of the invention, a first step of forming an amorphous semiconductor film on a substrate in a first reaction chamber and a second reaction chamber provided with a cathode under reduced pressure are provided. The cathode is sputtered by a discharge of a mixed gas of an inert gas and a gas containing a Group 13 element, and a catalytic element for promoting crystallization of the amorphous semiconductor film contained in the cathode, A second step of simultaneously adding a group 13 element to the amorphous semiconductor film; and a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. It is characterized by:

With the above structure, the steps from the formation of the amorphous semiconductor film to the addition of the catalytic element and the impurity element imparting the p-type can be continuously performed under reduced pressure, thereby preventing pollution from the environment. . As a result, the concentration of the added element and its effect can be precisely controlled with good reproducibility, and the productivity can be improved by performing the continuous processing.

The method of adding an element emitted from the cathode to the amorphous semiconductor film by using plasma includes adjusting the concentration of the element contained in the cathode, and adjusting discharge power, pressure, and processing time for forming plasma. By adjusting the concentration, the concentration can be controlled, and a trace amount of element can be added with good controllability. As a result, the threshold voltage of the TFT can be controlled with good reproducibility.

[0022]

[Embodiment 1] One embodiment of the present invention will be described below with reference to the drawings. In FIG. 1A, a silicon oxynitride film (A) 101a is formed as an insulating film to a thickness of 10 to 100 nm on a substrate 100 such as glass or quartz. A silicon oxynitride film (B) 10
1b is formed to a thickness of 10 to 100 nm. Further, an amorphous silicon film 102 is formed to a thickness of 20 to 80 nm.
The base silicon oxynitride film (A) exhibits a high blocking effect of alkali metal ions from the glass substrate, which is an advantage of the silicon nitride film. On the other hand, the base silicon oxynitride film (B) has advantages of a silicon oxide film such as a wide band gap, high insulating property, and a low trap level.

Next, as shown in FIG. 1B, Ni, which is a catalytic element for promoting crystallization, and B, which is an impurity element for imparting p-type, are added to the formed amorphous silicon film. Here, the catalyst element that promotes crystallization is F in addition to Ni.
e, Co, Ru, Rh, Pd, Os, Ir, Pt, C
u, Au or the like may be used. As the impurity element imparting p-type, an element of Group 13 of the periodic rule, such as Al or Ga, may be used in addition to B.

FIG. 2 shows a configuration of a semiconductor manufacturing apparatus suitable for the present invention. By providing a plurality of reaction chambers as shown in FIG. 2, formation of an amorphous semiconductor film from an insulating film serving as a base,
It is possible to perform continuous processing under reduced pressure without exposing to the atmosphere until i or B addition. The semiconductor manufacturing apparatus shown in FIG. 2 includes a load lock chamber 201, a transfer chamber 202, and reaction chambers 203 to 206. A substrate set in the load lock chamber 201 includes a transfer robot 207 installed in the transfer chamber 202. To each reaction chamber. Each of the reaction chambers is provided with a plasma generation means, a gas introduction means and an exhaust means. The load lock chamber 201 and the transfer chamber 202 are provided with exhaust means, respectively.

In the reaction chamber 203, an oxynitridation
A silicon film is formed. In the reaction chamber 204, the amorphous silicon
A cone film is formed. The cathode of the reaction chamber 205 is composed of Ni and B.
Made of material that contains. Reaction with such a cathode
Inert gas such as Ar gas or He gas in the chamber 205
By introducing and generating plasma, the reaction chamber 20
4. Ni and B can be added to the film formed in Step 4.
You. The concentration of Ni added here is 1 × 10^Ten~ 1 ×
10¹³/cm^Three, B concentration is 1 × 10¹⁶~ 5 × 10 ¹⁷/cm^Three
It is desirable that After the addition of Ni and B,
The recon film is heated to 500 to 600 ° C. for crystallization. Sa
If necessary, irradiate laser light to improve crystallinity
You may let it.

FIG. 18 shows the structure of a cathode made of a material containing Ni and B applied to the present invention. FIG. 18 (a)
2 shows a cathode made of an alloy of Ni and B. The mixing ratio is
The amount may be determined depending on the amount to be added in consideration of the sputtering efficiency. FIG. 18B shows an arrangement in which a tablet of B or Ni is arranged on a cathode of Ni or B, respectively. In FIG. 18C, the cathode itself or the cathode surface is meshed so that Ni and B tablets can be arranged. FIG. 18D shows the state shown in FIG.
The shape of the cathode is modified so that a rod-shaped tablet can be placed. The cathodes shown in FIGS. 18B to 18C have the advantage that the number and arrangement of tablets can be freely changed. Further, the shape of the tablet is not limited to a square shape, and various shapes such as a circle and a sphere can be used. In the present invention, FIGS.
It is possible to use any of the cathodes having the shapes shown up to (d).

FIG. 3 shows a reaction chamber of the semiconductor manufacturing apparatus of the present invention. In the reaction chamber 301, a cathode 302, a susceptor 3
A high frequency power supply 305 is connected to the cathode, and a heater 304 is connected to the susceptor. In addition, gas system 30
6 and the exhaust system 307 are connected. Gas type is 314 used gas, mass flow controller (MFC)
312 and a valve 313. The exhaust system includes a gate valve 308, an automatic pressure controller (APC) 309, a turbo molecular pump 310, and a dry pump 311. The pressure in the reaction chamber during film formation is 6
The substrate temperature is preferably in the range of 300 to 400 ° C. The high frequency power supply frequency used is 13.56 MHz to 12
The range is 0 MHz.

[Embodiment 2] In addition to the above embodiment, N
There is a method in which i and B are added in separate reaction chambers. The steps up to the formation of the amorphous silicon film are performed in the same manner as in the first embodiment. In FIG. 2, the cathode of the reaction chamber 205 is formed of a material containing Ni, and the cathode of the reaction chamber 206 is formed of a material containing B. First, after adding Ni in the reaction chamber 205, B is added in the reaction chamber 206. Of course, it is also possible to perform Ni addition after performing B addition first. Subsequent steps are the same as in the first embodiment.

[Embodiment 3] When an apparatus having a reaction chamber and a heat treatment furnace via a transfer chamber as shown in FIG. 17 is used, formation of an amorphous silicon film, addition of Ni and B, It is possible to work under reduced pressure until crystallization. Here, the reaction chamber 206 is a heat treatment furnace. Amorphous silicon film formation, Ni and B as in the first or second embodiment.
The added substrate is transferred to the load lock chamber 208 and transferred to the heat treatment furnace 206 by the transfer robot 209. The method for crystallizing an amorphous silicon film is described in Embodiment 1.
Or it may be performed in the same manner as in 2.

[0030]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS. 4 to 7 and FIG. Here, a pixel portion and a driving circuit TFT (an n-channel TFT and a p-channel TF) provided around the pixel portion on the same substrate by using the present invention are used.
The method for simultaneously producing T) will be described in detail.

As the substrate 100, a glass substrate is used. First, as shown in FIG. 4A, a 50-nm-thick silicon oxynitride film 101a is formed over a substrate 100 as an insulating film. Next, the silicon oxynitride film 101b is
Formed to a thickness of In this embodiment, as the insulating film 101, 2
Although a layered structure is used, a single-layered silicon oxynitride film or a structure in which two or more layers are stacked may be used. An amorphous silicon film 102 is formed thereon with a thickness of 55 nm.

Next, Ni, which is a catalyst element for promoting crystallization, and B, which is an impurity element for imparting p-type, are added to the formed amorphous silicon film. As a method therefor, Ar is introduced as an inert gas into a reaction chamber having a cathode made of Ni and B, and the pressure is 6.65 to 1.33 × 10 ² Pa, the high frequency power is 30 to 100 W (power frequency 13.56 ~ 60M
Hz) to generate plasma. Since the cathode is negatively charged by the self-bias, positive ions in the plasma are accelerated by the sheath formed near the cathode and enter the cathode. The elements constituting the cathode, Ni and B, are released by ion bombardment sputtering and adhere to the amorphous silicon film.

The inert gas introduced for generating the plasma may be not only Ar but He, Kr, or Xe. Alternatively, N ₂ may be used. Also, by simultaneously adding hydrogen, the surface of the amorphous silicon film can be terminated and inactivated by hydrogen, and Ni attached to the surface can be inactivated.
Alternatively, the movement of B is promoted, and the distribution of the element can be dispersed.

The processing time may be appropriately set by the operator, but is determined in consideration of the component ratio of Ni and B in the cathode and the applied high frequency power.

In this way, Ni is 1 × 10 ¹⁰ -1 ×
An amorphous silicon film to which 10 ¹³ / cm ² and B are added at a concentration of 1 × 10 ^{13 to} 5 × 10 ¹⁴ / cm ² is obtained. As a catalyst element for promoting crystallization of the amorphous silicon film, in addition to Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, P
t, Cu, Au and the like. In addition, p
As the element for imparting the mold, in addition to B, an element belonging to Group 13 of the periodic law such as Al or Ga is known.

The above steps can be performed continuously under reduced pressure without exposing to the atmosphere until the formation of the insulating film, the formation of the amorphous semiconductor film, and the addition of Ni and B.

After Ni and B are added to the amorphous silicon film, a dehydrogenation treatment is performed at 500 ° C. for 1 hour and a heat treatment is performed at 550 ° C. for 4 hours to obtain a crystalline silicon film 103. Further, laser light irradiation may be performed to improve crystallinity. The crystalline silicon film thus formed contains B as a p-type impurity element in an amount of 1 × 10 ¹⁵ to 1 × 10 ^17.
/ cm ³ concentration.

Then, the crystalline semiconductor film is subjected to a patterning process using a photolithography method to form crystalline silicon layers 104 to 108 divided into islands (FIG. 4C).

When the crystallinity is improved by irradiation with a laser beam, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YLF laser, a YV laser, or the like can be used.
An O ₄ laser can be used. In the case of using these lasers, a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and applied to a semiconductor film is preferable. The conditions for crystallization may be appropriately selected by the practitioner.

Next, the crystalline silicon films 104 to 108
Is formed to cover the gate insulating film 109. Gate insulating film 1
09 is formed by a plasma CVD method or a sputtering method, and is formed of an insulating film containing silicon with a thickness of 40 to 150 nm. Of course, as the gate insulating film, an insulating film containing silicon can be used as a single layer or a stacked structure.

When a silicon oxide film is used, TEOS (Tetraethyl Ortho Silicate) and O ₂ are mixed by a plasma CVD method, the reaction pressure is 40 Pa, and the substrate temperature is 300 to 40.
0 ° C, high frequency (13.56 MHz) power density 0.5 ~
It can be formed by discharging at 0.8 W / cm ² . The silicon oxide film thus formed has a thickness of 400 after formation.
Good characteristics as a gate insulating film can be obtained by thermal annealing at up to 500 ° C.

Next, a film thickness of 20 is formed on the gate insulating film 109.
A first conductive film 110 having a thickness of
A second conductive film 111 of 0 nm is formed by lamination (FIG.
(A)). These conductive films are made of Ta, W, Ti, Mo, A
It may be formed of an element selected from l and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus (P) may be used. Further, the first conductive film is formed of a Ta film, and the second conductive film is formed of W
The first combination is a tantalum nitride film, and the second combination is an Al film.
Is formed of a tantalum nitride film, and the second conductive film is C
A combination with a u film may be used.

Next, as shown in FIG. 5B, the masks 112 to 112 made of resist are formed by photolithography.
117 is formed, and a first etching process for forming electrodes and wirings is performed. In this embodiment, the ICP (Inductiv
ely Coupled Plasma), using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25:25:10,
At a pressure of 1 Pa, a 500 W RF (1
(3.56 MHz) power is supplied to generate plasma to perform etching. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage) and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to make the end of the first conductive layer tapered.

Thereafter, the masks 112 to 112 made of resist are formed.
117 was changed to the second etching condition without removing it, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30:30, and 500 W RF was applied to the coil type electrode at a pressure of 1 Pa. (13.56 MHz) Power is supplied to generate plasma, and etching is performed for about 30 seconds. 20W RF (13.56MHz) on substrate side (sample stage)
Power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, both the W film and the tantalum nitride film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the mask made of resist suitable,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, by the first etching process, the first shape conductive layers 119 to 124 (the first conductive layers 119 a to 124 a and the second conductive layers 119 b to 119 b) including the first conductive layer and the second conductive layer are formed.
4b) is formed. Reference numeral 118 denotes a gate insulating film,
The region not covered with the conductive layers 119 to 124 having the shape of
A region that is etched and thinned by about 50 nm is formed.

Then, the resist mask is removed.
First doping process without adding n-type to the semiconductor layer.
A given impurity element is added (FIG. 5B). Dopin
Can be done by ion doping or ion implantation
Good. The condition of the ion doping method is that the dose amount is 1.5 × 1.
0¹⁵/cm^TwoAnd the acceleration voltage was set to 60 to 100 keV.
U. Element belonging to Group 15 as an impurity element imparting n-type
An element, typically phosphorus (P) or arsenic (As) is used.
In this case, the conductive layers 119 to 123 may have n-type impurities.
Masks the impurity elements and self-aligns the first impurity
Object regions 125 to 129 are formed. First impurity region
1 × 10 for 125-129²⁰~ 1 × 10 ^{twenty one}/cm^ThreeConcentration
An impurity element imparting n-type is added within the range.

Next, a second etching process is performed as shown in FIG. 5C without removing the resist mask. Using CF ₄ , Cl ₂ and O _{2 as} etching gas,
The gas flow ratio was set to 20:20:20, and 500 W of RF (13.56 MHz) was applied to the coil-type electrode at a pressure of 1 Pa.
z) Apply power and generate plasma to perform etching. On the substrate side (sample stage), 20 W RF (13.
(56 MHz) power is applied, and a lower self-bias voltage is applied than in the first etching process. The W film is anisotropically etched under the third etching condition to form second shape conductive layers 131 to 136.

Next, a second doping process is performed as shown in FIG. 6A without removing the resist mask. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, when the acceleration voltage is 70 to 12
The accelerating voltage is 0 keV, 90 keV in this embodiment, and 1.5 ×
At a dose of 10 ¹⁴ / cm ² , a new impurity region is formed in the semiconductor layer inside the first impurity region formed in FIG. The doping is performed on the second shape conductive layer 13.
The semiconductor layers below the first conductive layers 131a to 135a are doped with the impurity elements by using the elements 1 to 135 as masks for the impurity elements.

Thus, the first conductive layers 131a to 131a
Second impurity regions 137 to 141 overlapping with a are formed.

Next, after removing the resist mask, new masks 147 and 148 are formed, and a third etching process is performed as shown in FIG. 6B. SF ₆ and Cl ₂ were used as etching gases, the respective gas flow ratios were set to 50:10, and 1.3 Pa
500W RF (13.56M)
Hz) Power is applied to generate plasma and perform etching for about 30 seconds. 10W R on the substrate side (sample stage)
F (13.56 MHz) power is applied and a substantially negative self-bias voltage is applied. Thus, the p-channel TFT and the TFT in the pixel portion are changed according to the third etching condition.
The tantalum nitride film is etched to form third shape conductive layers 149-152.

After removing the resist mask, the gate insulating film is etched as shown in FIG. Using CHF ₃ as an etching gas,
Plasma is generated by supplying RF power of 35 SCCM and 800 W at a gas flow rate to perform etching. Here, the second shape conductive layers 131 and 133 and the third conductive layers 149 to 1
52 functions as a mask, and the gate insulating film is cut for each TFT (154 to 160).

Next, masks 161 to 163 are formed, and a third doping process is performed as shown in FIG. By this third doping process, the p-channel type T
Second impurity regions 164 to 167 to which an impurity element imparting a conductivity type opposite to the one conductivity type is added are formed in a semiconductor layer to be an active layer of the FT. Third shape conductive layer 14
9 and 153 are used as masks for impurity elements, and p
A third impurity region is formed in a self-aligned manner by adding an impurity element imparting a mold. In the present embodiment, the impurity region 16
4 to 167 are formed by an ion doping method using diborane (B ₂ H ₆ ). In the third doping process, n
The semiconductor layer forming the channel type TFT is covered with masks 161 to 163 made of resist. By the first doping process and the second doping process, the impurity regions 164 to 167 have different concentrations of phosphorus (P), respectively.
Is added, but by performing doping treatment so that the concentration of the impurity element imparting p-type becomes higher in any of the regions, the p-type TFT functions as a source region and a drain region. No problem arises.

Through the above steps, an impurity region is formed in each semiconductor film. In this embodiment, all the impurity regions are formed in a self-aligned manner using the conductive layer as a mask. Third shape conductive layers 131 and 13 overlapping with the semiconductor film
2, 149 and 150 function as gate electrodes. 152 functions as a source wiring, and 151 functions as a second electrode for forming a storage capacitor.

Next, the masks 161 to 163 are removed,
A first interlayer insulating film 168 covering the entire surface is formed. The first interlayer insulating film 168 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 168 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 7B, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As a thermal annealing method, an oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 550.
C. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA)
Law) can be applied.

In this embodiment, at the same time as the activation treatment, the impurity regions 142 to 146, 164 containing high-concentration phosphorus (P) containing Ni used as a catalyst during crystallization are used.
166 can be obtained, and the Ni concentration in crystalline silicon which mainly serves as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Next, a second interlayer insulating film 169 made of an organic insulating material is formed on the first interlayer insulating film 168. Next, a contact hole reaching the source wiring 152 and each of the impurity regions 142, 144, 145a, 164,
Patterning for forming a contact hole reaching 166 is performed.

Then, in the driver circuit 406, wirings 170 to 175 electrically connected to the first impurity region or the third impurity region, respectively, are formed. Note that these wirings include a Ti film having a thickness of 50 to 250 nm and a
A laminated film of a 500 nm alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 407, a pixel electrode 178, a gate conductive film 177, and a connection electrode 176 are formed (FIG. 7C). The connection electrode 176 forms an electrical connection between the source wiring 152 and the pixel TFT 404. Further, the gate conductive film 177 is formed of a first electrode (third electrode).
And an electrical connection is formed.
The pixel electrode 178 is electrically connected to the drain region of the pixel TFT, and is also electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03 and a pixel portion 407 including a pixel TFT 404 and a storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 40 of the driving circuit 406
1 denotes a second impurity region 13 which overlaps with a channel formation region 178 and a third shape conductive layer 131 forming a gate electrode.
7 and a first impurity region 142 functioning as a source region or a drain region. p-channel type TFT4
02 has a channel formation region 179, a third impurity region 165 formed outside the gate electrode, and a third impurity region 164 functioning as a source or drain region. In the n-channel TFT 403, a channel formation region 180, a second impurity region 139 overlapping with the third shape conductive layer 133 forming a gate electrode, and a first impurity region 144 functioning as a source or drain region
have.

The pixel TFT 404 of the pixel portion 407 has a channel forming region 181, a second impurity region 140 formed outside the gate electrode, and a first impurity region 145a functioning as a source or drain region. .
The semiconductor layers 166 and 167 functioning as one electrode of the storage capacitor 405 are each doped with an impurity element imparting p-type at the same concentration as the third impurity region. The storage capacitor 405 is formed by using an insulating film (the same film as the gate insulating film) as a dielectric, the second electrode 151 and the semiconductor layer 1.
66 and 167.

FIG. 10 is a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. Note that the same reference numerals are used for portions corresponding to FIGS. A chain line AA ′ in FIG. 10 corresponds to a cross-sectional view cut along a chain line AA ′ in FIG. Also, the chain line BB ′ in FIG.
This corresponds to a cross-sectional view taken along a chain line BB ′ in FIG. With such a pixel structure, a pixel electrode having a large area can be provided, and the aperture ratio can be improved.

According to the steps shown in this embodiment, the number of photomasks required for manufacturing an active matrix substrate is six (semiconductor layer pattern mask, first wiring pattern mask (first electrode 150, second electrode 150). 151, source wiring 1
52), a pattern mask for forming a conductive layer of a p-channel TFT and a pixel portion TFT, a pattern mask for forming a source region and a drain region of a p-channel TFT, a pattern mask for forming a contact hole, and a second wiring pattern mask (pixel) The electrode 178, the connection electrode 176, and the gate conductive film 177). Further, since the addition of Ni and the addition of B are performed at the same time and the formation of the amorphous semiconductor film is performed continuously, as a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

In the above steps, by adding a catalytic element which promotes crystallization of the amorphous silicon film continuously after the formation of the amorphous silicon film, the contamination of the surface can be prevented, and the crystal with high uniformity can be prevented. A high quality silicon film can be formed.
Furthermore, by performing B doping continuously after the formation of the amorphous silicon film, destruction of the crystal structure of the channel formation region is prevented, so that the threshold voltage can be controlled with good reproducibility. Further, by adding the catalyst element and B at the same time, the productivity can be improved.

FIG. 8 is a sectional view of an active matrix substrate suitable for a transmission type liquid crystal display device. The process up to the formation of the second interlayer film is the same as that of the above-mentioned reflection type. A transparent conductive film is formed over the second interlayer film. Then, patterning is performed to form a transparent conductive film layer 185. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.

Then, wirings 170 to 175 electrically connected to the first impurity region or the third impurity region in the driver circuit 406 are formed. Note that these wirings include a Ti film having a thickness of 50 to 250 nm and a
A laminated film of a 500 nm alloy (an alloy film of Al and Ti) is formed by patterning. In the pixel portion 407, a pixel electrode 185, a gate conductive film 177, and connection electrodes 186 and 187 are formed. Connection electrodes 186, 187
Are formed so as to overlap the pixel electrode 185. Thus, an active matrix substrate suitable for a transmissive liquid crystal display device can be manufactured by increasing the number of masks by one.

[Embodiment 2] In Embodiment 1, the case where different addition methods of Ni and B are used will be described. The drawings used for the description are the same as those in the first embodiment.

In the same manner as in the first embodiment, the layers from the insulating film 101 to the amorphous silicon film 102 are formed. Then, Ni
A plasma is generated in a reaction chamber having a cathode made of B, and after adding Ni by exposing the amorphous silicon film 102 to the plasma, a plasma is generated in a reaction chamber having a cathode made of B. B is added by exposing the amorphous semiconductor film to which Ni has been added to the plasma. Thereafter, dehydrogenation at 500 ° C. for 1 hour, followed by 550 ° C.
For 4 hours to form a crystalline silicon film 103. Irradiation with laser light may be performed to further improve crystallization.

In cases where it is difficult to obtain an alloy of Ni and B or where it is difficult to obtain an appropriate concentration by adding Ni and B in the same reaction chamber, As in the example, a method of adding Ni and B in separate reaction chambers is effective. Subsequent steps may refer to Embodiment 1.

[Embodiment 3] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 or Embodiment 2 will be described below. It is also possible to use an active matrix substrate manufactured in Example 5 described later. FIG. 9 is used for the description.

First, according to the first embodiment or the second embodiment, FIG.
After the active matrix substrate in the state of FIG. 7C is manufactured, an alignment film 567 is formed over the active matrix substrate of FIG. Note that in this embodiment, before forming the alignment film 567, a columnar spacer 572 for maintaining a substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film.

Next, the coloring layer 57 is formed on the counter substrate 569.
0, 571 and a flattening film 573 are formed. The second colored portion is formed by partially overlapping the red colored layer 570 and the blue colored layer 571.

Next, a counter electrode 576 is formed in the pixel portion, an alignment film 574 is formed on the entire surface of the counter substrate, and a rubbing process is performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealant 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer 572. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 9 is completed.

In this embodiment, the substrate shown in the first embodiment is used. Therefore, FIG. 1 shows a top view of the pixel portion of the first embodiment.
0, at least the gate wiring 177 and the pixel electrode 178
, The gap between the gate wiring 177 and the connection electrode 176, and the gap between the connection electrode 176 and the pixel electrode 178 need to be shielded from light. In this embodiment, an opposing substrate is bonded so that the first light-shielding portion and the second light-shielding portion overlap at those positions where light is to be shielded.

The liquid crystal display device manufactured as described above can be used as a display unit of various electronic devices.

[Embodiment 4] In this embodiment, a method for manufacturing a crystalline semiconductor film over a substrate will be described with reference to FIGS.

After forming an insulating film 301 on a substrate 300, an amorphous semiconductor film 302 is formed. A catalyst element Ni for promoting crystallization and an element B for imparting p-type are added to the amorphous semiconductor film 302 (FIG. 19A), and a crystalline semiconductor film 303 is obtained by crystallization (FIG. 19B). )). For the above steps, Example 1 or Example 2 is applied.

On the obtained amorphous semiconductor film 303, a mask layer 304 is formed with a silicon oxide film or the like, and first patterning is performed (FIG. 19C). Using the patterned resist 305 as a mask, the mask layer 304 is etched. Next, a first doping process is performed using the resist 305 and the mask layer 306 as a mask. In the first doping treatment, phosphorus (P) is added to the crystalline semiconductor layer 303 to form an impurity region 307 (FIG. 19D).

Next, heat treatment is performed. In this step, Ni added to the semiconductor layer diffuses into the impurity region 307. After the heat treatment, the impurity region 307 is removed by etching, so that the impurity Ni
Can be removed (FIG. 19E).

The resist 305 and the mask layer 306 are separated to obtain a crystalline semiconductor film 308 (FIG. 19F). Subsequent steps may refer to a known TFT manufacturing method.

In the above steps, the surface element can be prevented from being contaminated by adding a catalytic element for promoting crystallization of the amorphous silicon film continuously after the formation of the amorphous silicon film. A high quality silicon film can be formed.
Furthermore, by performing B doping continuously after the formation of the amorphous silicon film, destruction of the crystal structure of the channel formation region is prevented, so that the threshold voltage can be controlled with good reproducibility. Further, by adding the catalyst element and B at the same time, the productivity can be improved. By removing Ni, which is an impurity, from the channel portion of the TFT, the off-state current value can be reduced, and variation can be reduced.

[Embodiment 5] In this embodiment, an inverted staggered TF is used.
FIGS. 11 to 11 show a method for simultaneously manufacturing a pixel portion and a TFT (an n-channel TFT and a p-channel TFT) for forming a driver circuit around the pixel portion over the same substrate using T. FIGS.
13 will be described.

First, as shown in FIG. 11A, a substrate 1101 made of glass, such as barium borosilicate glass or aluminoborosilicate glass, is preferably provided with Mo,
The gate electrodes 1102 to 1104 and the source wiring 11 are formed from a conductive film containing one or more components selected from W and Ta.
06, 1107, and a capacitor wiring 1105 for forming a storage capacitor of the pixel portion are formed. For example, an alloy of Mo and W is suitable from the viewpoint of low resistance and heat resistance. Alternatively, a gate electrode may be formed by using aluminum and oxidizing the surface.

The gate electrode formed using the first photomask has a thickness of 200 to 400 nm, preferably 2 to 400 nm.
The film is formed to have a thickness of 50 nm, and is formed to have a tapered end in order to improve the coverage (step coverage) of a film formed thereon. The angle of the tapered portion is 5 to 30 degrees, preferably 15 to 25 degrees. The tapered portion is formed by a dry etching method, and its angle is controlled by an etching gas and a bias voltage applied to the substrate side.

Next, as shown in FIG. 11B, the gate electrodes 1102 to 1104 and the source lines 1106 and 11
07, a capacitor line 11 for forming a storage capacitor of a pixel portion
A first insulating layer 1108 that covers the insulating layer 05 is formed. Although a two-layer structure is used as the first insulating layer 1108 in this embodiment, a single-layer film of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or a structure in which two or more layers are stacked may be used. As the first layer of the first insulating layer 1108, S
A silicon oxynitride film 1108a is formed to a thickness of 50 to 100 nm using iH ₄ , NH ₃ , N ₂ O, and H ₂ as reaction gases. Then, as the second layer of the first insulating layer 1108 is formed in lamination deposited is silicon oxynitride film 1108b SiH ₄ and N ₂ O as reaction gases to a thickness of 100 to 150 nm. Next, an amorphous semiconductor film 1109 is formed with a thickness of 30 to 60 nm over the first insulating layer. Although the material of the amorphous semiconductor film is not limited, silicon is preferably used. In the present embodiment, using SiH ₄ gas,
An amorphous silicon film 1109 is formed.

The first insulating layer 1108 has a semiconductor layer formed thereover and is used as a gate insulating film. The first insulating layer 1108 is a blocking layer which prevents impurities such as alkali metals from diffusing from the substrate 1101 into the semiconductor layer. It also has a function as

A catalytic element for promoting crystallization and an impurity element for imparting p-type are added to the formed amorphous silicon film.
The method of Example 1 or Example 2 is applied as a method of adding.

Next, the formed amorphous silicon film is crystallized by a heat treatment. This crystallization method is described in Example 1.
Alternatively, the second embodiment may be referred to.

The obtained crystalline silicon film is formed in a predetermined pattern using a second photomask. FIG.
(C) shows semiconductor layers 1110 to 1213 formed in an island shape.
Is shown. The semiconductor layers 1110 to 1112 are the gate electrodes 1
102 and 1104 are formed so as to partially overlap.

Thereafter, the crystalline silicon films 1110 to 11
An insulating film made of silicon oxide or silicon nitride is formed on the substrate 13 to a thickness of 100 to 200 nm. FIG. 11 (D)
The third insulating layers 1114 to 1118 are used as channel protection films in a self-aligned manner by a backside exposure process using a gate electrode as a mask.
It is formed on 112.

Then, a first doping step for forming an LDD region of the n-channel TFT is performed. The doping may be performed by an ion doping method or an ion implantation method. Phosphorus (P) is added as an n-type impurity (donor), and first impurity regions 1119 to 1122 formed using the third insulating layers 1115 to 1118 as a mask are formed. The donor concentration in this region is 1 × 10 ¹⁶ to 2 × 10
The concentration is ¹⁷ / cm ³ .

In the second doping step, an n-channel type T
In this step, a source region and a drain region of the FT are formed. As shown in FIG. 12A, masks 1123 to 1125 are formed using a third photomask. Masks 1124 and 1125 are n-channel type TFs.
The second impurity region 1 is formed so as to cover the LDD region of T.
To 126 to 1128, a donor impurity is added in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ .

Before or after the second doping step, etching with hydrofluoric acid is performed in a state where the masks 1123 to 1125 have been formed, and the third insulating layers 1114 and 1111 are formed.
Preferably, 18 is removed.

The source region and the drain region of the p-channel type TFT are formed by a third doping process as shown in FIG.
Third impurity regions 1130 and 1131 are formed by adding a type impurity (acceptor). The p-type impurity concentration in this region is set to 2 × 10 ²⁰ to 2 × 10 ²¹ / cm ³ . In this step, a p-type impurity is also added to the semiconductor layer 1113.

Next, as shown in FIG. 12C, a second insulating layer is formed over the semiconductor layer. Preferably, the second insulating layer is formed using a plurality of insulating films. The first layer 1132 of the second insulating layer formed over the semiconductor layer is an inorganic insulator formed of a silicon nitride film or a silicon nitride oxide film containing hydrogen and has a thickness of 50 to 200 nm. Thereafter, a step of activating the impurity added to each semiconductor layer is performed.
In this step, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

By this activation treatment, hydrogen of the silicon nitride film or the silicon nitride oxide film of the first layer 1132 of the second insulating layer is released simultaneously with the activation of the impurity element, and hydrogenation of the semiconductor layer is performed. Can be.

A second layer 1133 of the second insulating layer shown in FIG. 13A is formed of an organic insulating material such as polyimide or acrylic, and has a flat surface. Of course, a silicon oxide film formed using TEOS by a plasma CVD method may be used, but from the viewpoint of improving flatness, it is preferable to use the organic material.

Next, a contact hole is formed using a fifth photomask. Then, the driving circuit 13 is formed using Al, Ti, Ta, or the like using the sixth photomask.
At 05, a connection electrode 1134 and source or drain wirings 1135 to 1137 are formed. The pixel unit 13
At 06, the pixel electrode 1140, the gate wiring 113
9. The connection electrode 1138 is formed.

Thus, the p-channel type T
A driving circuit 1305 having an FT 1301 and an n-channel TFT 1302, a pixel TFT 1303 and a storage capacitor 13
The pixel portion 1306 having the pixel number 04 is formed. Drive circuit 1
A channel formation region 1307 and a source or drain region 1308 including a third impurity region are formed in the p-channel TFT 1301 of 305. A channel forming region 1309 and a first
An LDD region 1310 made of an impurity region and a source or drain region 1311 made of a second impurity region are formed. The pixel TFT 1303 of the pixel portion 1306 is
A multi-gate structure, a channel formation region 1312,
LDD region 1313, source or drain region 131
4, 1316 are formed. The second impurity region 1315 located between the LDD regions is useful for reducing off-state current. The storage capacitor 1304 is a capacitor wiring 1105
And a semiconductor layer 1113 and a first insulating layer formed therebetween.

In the pixel portion 1306, the connection electrode 11
38, the source wiring 1107 is
An electrical connection is formed with the source or drain region 1314 of FIG. Further, the gate wiring 1139 is electrically connected to the first electrode. In addition, the pixel electrode 1140
Is the source or drain region 13 of the pixel TFT 1303
16 and the semiconductor layer 1113 of the storage capacitor 1304.

FIG. 13B illustrates a contact portion between the gate electrode 1104 and the gate wiring 1139. The gate electrode 1104 also serves as one electrode of a storage capacitor of an adjacent pixel, and is connected to the pixel electrode 1145.
The portion overlapping with No. 4 forms a capacitor. FIG.
(C) shows an arrangement relationship between the source wiring 1107, the pixel electrode 1140, and an adjacent pixel electrode 1146. An end portion of the pixel electrode is provided over the source wiring 1107, and an overlapping portion is formed to block stray light and block light. Is increasing.

One of the advantages of forming an inverted staggered TFT is that an LDD region overlapping with a gate electrode in an n-channel TFT can be formed in a self-aligned manner by a backside exposure process. In addition, the characteristic variation of the TFT can be reduced in combination with the feature that the semiconductor layer can be continuously formed. Further, by using the present invention, destruction of the crystal structure of the semiconductor layer can be prevented, so that stable TFT characteristics can be obtained.

Further, by adding a catalytic element that promotes crystallization of the amorphous silicon film continuously after the formation of the amorphous silicon film, contamination of the surface can be prevented, and a highly uniform crystalline silicon film can be obtained. Can be formed. Furthermore, by performing B doping continuously after the formation of the amorphous silicon film, destruction of the crystal structure of the channel formation region is prevented, so that the threshold voltage can be controlled with good reproducibility. Further, by adding the catalyst element and B at the same time, the productivity can be improved.

[Embodiment 6] In this embodiment, a method for manufacturing a crystalline semiconductor film over a substrate will be described with reference to FIGS.

As the substrate 600, a quartz substrate is used. In addition, any material having heat resistance can be used. Substrate 6
An amorphous semiconductor film 601 is formed with a thickness of 30 to 60 nm on the substrate 00. In this embodiment, no insulating film is formed,
Of course, an insulating film can be formed. To the formed amorphous semiconductor film 601, a catalyst element Ni for promoting crystallization and an element B for imparting p-type are added. Example 1 or Example 2 is applied as the addition method.

Next, thermal crystallization is performed (FIG. 20).
(B)). It is good to carry out at 570 to 600 ° C. for about 12 to 14 hours. By this heat treatment, a crystalline semiconductor film 602 is obtained. This crystalline semiconductor film is patterned to obtain a crystalline semiconductor film 603 (FIG. 20C). Subsequent steps may refer to a known TFT manufacturing method.

[Embodiment 7] This embodiment is directed to a method of adding Ni, which is a catalyst element for promoting crystallization, and an impurity element for imparting p-type (group 13 element of the periodic law) to an amorphous silicon film. Another example is shown.

First, an amorphous silicon film is formed in the same manner as in the first embodiment. Then, to add the catalyst element,
Move the substrate to another reaction chamber. The cathode in this reaction chamber is N
It contains i, and for example, a flat electrode or a mesh electrode made of Ni alone can be used.

The inert gas introduced into the reaction chamber for generating plasma may be Ar, and may be He, K
r, Xe, or the like can be used. Further, N ₂ can be added as an inert gas. Further, the inert gas contains a gas containing a Group 13 element of the periodic law in a range of 1 to 1000.
Add ppm. B ₂ H ₆ , BF _3, or the like can be used as a gas containing a Group 13 element of the periodic rule.

A preferred example is a mixed gas of Ar and B ₂ H _6. By generating plasma with this mixed gas,
The sputtering action of Ar ions on the cathode and B ₂
Ni and B can be added to the amorphous silicon film by dissociation of H ₆ . B ₂ H ₆ may be diluted with Ar, or may be diluted with hydrogen.

In the case where it is difficult to obtain an alloy of Ni and B, or in the case where it is difficult to obtain an appropriate concentration when Ni and B are added in the same reaction chamber, the present embodiment will be described. The method shown is effective. The method described in this embodiment can be performed by replacing the method of adding Ni and B described in Embodiment 1.

[Embodiment 8] T produced by carrying out the present invention
The FT can be used for various electro-optical devices (typically, an active matrix type liquid crystal display and the like). That is, the present invention can be applied to all electronic devices incorporating such electro-optical devices and semiconductor circuits as components.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation system, a car stereo, a personal computer, and a portable information terminal device (mobile). Computer, mobile phone, electronic book, or the like). Examples of these are shown in FIGS. 14, 15 and 16.

FIG. 14A shows a personal computer, which includes a main body 1401, an image input section 1402, and a display section 14.
03, a keyboard 1404, and the like. The present invention can be applied to the image input unit 1402, the display unit 1403, and other signal control circuits.

FIG. 14B shows a video camera, which includes a main body 1405, a display portion 1406, an audio input portion 1407, operation switches 1408, a battery 1409, and an image receiving portion 141.
0 and so on. The present invention can be applied to the display portion 1406 and other signal control circuits.

FIG. 14C shows a mobile computer (mobile computer) including a main body 1411, a camera section 1412, an image receiving section 1413, operation switches 1414, a display section 1415, and the like. The present invention can be applied to the display portion 1415 and other signal control circuits.

FIG. 14D shows a goggle type display, which includes a main body 1416, a display section 1417, and an arm section 141.
8 and the like. The present invention can be applied to the display portion 1417 and other signal control circuits.

FIG. 14E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 1419, a display section 1420, and a speaker section 142.
1, a recording medium 1422, an operation switch 1423, and the like. This player uses a DVD (Di
Gital Versatile Disc), CDs, etc., can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 1420 and other signal control circuits.

FIG. 14F shows a digital camera, which includes a main body 1424, a display portion 1425, an eyepiece portion 1426, operation switches 1427, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 1425 and other signal control circuits.

FIG. 15A shows a front type projector, which includes a projection device 1501, a screen 1502, and the like. The present invention can be applied to the liquid crystal display device 1514 forming a part of the projection device 1501 and other signal control circuits.

FIG. 15B shows a rear type projector, which includes a main body 1503, a projection device 1504, and a mirror 150.
5, a screen 1506, and the like. The present invention can be applied to the liquid crystal display device 1514 forming a part of the projection device 1504 and other signal control circuits.

FIG. 15C is a diagram showing an example of the structure of the projection devices 1501 and 1504 in FIGS. 15A and 15B. Projection devices 1501, 15
04 denotes a light source optical system 1507, mirrors 1508 and 151
0 to 1512, dichroic mirror 1509, prism 1513, liquid crystal display device 1514, retardation plate 151
5. It is composed of a projection optical system 1516. Projection optical system 15
Reference numeral 16 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 15D is a diagram showing an example of the structure of the light source optical system 1507 in FIG. 15C. In this embodiment, the light source optical system 1807 includes a reflector 1518, a light source 1519, a lens array 1520,
521, a polarization conversion element 1522, and a condenser lens 1523. Note that the light source optical system shown in FIG. 15D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 15, a case where a transmission type liquid crystal display device is used is shown, and an application example of a reflection type electro-optical device is not shown.

FIG. 16A shows a cellular phone, which includes a display panel 1601, an operation panel 1602, and a connection section 160.
3. Display with built-in sensor 1604, audio output unit 1
605, operation keys 1606, a power switch 1607, a voice input unit 1608, an antenna 1609, and the like. The present invention is applied to a display 1604 with a built-in sensor and an audio output unit 1.
605, the voice input unit 1608, and other signal control circuits.

FIG. 16B shows a portable book (electronic book), which includes a main body 1611, a display section 1612, and a storage medium 161.
3, including an operation switch 1614, an antenna 1615, and the like. The present invention can be applied to the display portion 1612, the storage medium 1613, and other signal circuits.

FIG. 16C shows a display, which includes a main body 1916, a support base 1917, a display portion 1918, and the like. The present invention can be applied to the display portion 1918.
The liquid crystal display device of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to various electronic devices.

[0131]

According to the present invention, the number of steps in manufacturing a TFT is reduced, and a device for channel doping is not required, so that cost reduction can be realized. In addition, by performing the doping process before crystallization, the crystal structure formed by crystallization can be prevented from being destroyed at the time of doping. And high-speed communication.

By adding a catalytic element that promotes crystallization of the amorphous silicon film continuously after the formation of the amorphous silicon film, contamination of the surface can be prevented and a highly uniform crystalline silicon film can be formed. can do. Further, by performing B doping continuously after the formation of the amorphous silicon film,
Since the destruction of the crystal structure of the channel formation region is prevented, the threshold voltage can be controlled with good reproducibility. Further, by adding the catalyst element and B at the same time, the productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a TFT according to a first embodiment.

FIG. 2 is an apparatus diagram of the first embodiment.

FIG. 3 is a sectional view of the apparatus according to the first embodiment.

FIG. 4 is a sectional view of a TFT according to the first embodiment.

FIG. 5 is a sectional view of a TFT according to the first embodiment.

FIG. 6 is a sectional view of a TFT according to the first embodiment.

FIG. 7 is a sectional view of a TFT according to the first embodiment.

FIG. 8 is a sectional view of a TFT according to the first embodiment.

FIG. 9 is a cross-sectional view of an active matrix liquid crystal display device according to a third embodiment.

FIG. 10 is a top view of a pixel portion of an active matrix substrate manufactured in Embodiment 1.

FIG. 11 is a sectional view of a TFT according to a fifth embodiment.

FIG. 12 is a sectional view of a TFT according to a fifth embodiment.

FIG. 13 is a sectional view of a TFT according to a fifth embodiment.

FIG. 14 is a diagram showing various semiconductor devices according to the seventh embodiment.

FIG. 15 is a diagram showing various semiconductor devices according to the seventh embodiment.

FIG. 16 is a view showing various semiconductor devices according to the seventh embodiment.

FIG. 17 is an apparatus diagram of the third embodiment.

FIG. 18 is a diagram of a cathode used for adding Ni and B.

FIG. 19 is a sectional view of a TFT according to the fourth embodiment.

FIG. 20 is a sectional view of a TFT according to the sixth embodiment.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/786 H01L 29/78 627B 618F (72) Inventor Hideo Saito 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka In-house F-term (reference) 2H092 JA25 JA26 JB56 KA04 MA05 MA27 MA29 MA30 MA37 NA13 NA24 NA29 PA01 5C094 AA13 AA43 AA44 BA03 CA19 DA14 DA15 DB01 DB04 EA04 EA07 EB05 5F048 AC04 BA16 BB05 BB09 BC16 BG05 A02A02A EA16 FA06 FA19 HA06 JA01 5F110 AA08 AA16 BB02 BB04 CC02 CC08 DD02 DD03 DD13 DD14 DD15 EE01 EE02 EE03 EE04 EE06 EE09 EE14 EE23 EE28 FF02 FF03 FF04 FF28 FF29 FF30 FF36 J03 H04 GG13 H04 GG13 GG02 HM15 NN04 NN05 NN14 NN22 NN23 NN24 NN27 NN34 NN35 NN72 NN73 PP01 PP03 PP06 PP10 PP29 PP34 PP35 QQ04 QQ09 QQ11 QQ12 QQ19 QQ23 QQ25 QQ28

Claims (30)

[Claims] A first step of forming an amorphous semiconductor film on a substrate and a plurality of types of elements contained in the cathode by discharging an inert gas under reduced pressure in a reaction chamber provided with the cathode. A second step of discharging the amorphous semiconductor film by sputtering and adding the amorphous semiconductor film to the amorphous semiconductor film; and a third step of crystallizing the amorphous semiconductor film after the second step to form a crystalline semiconductor film. A method for manufacturing a semiconductor device, comprising: A first step of forming an insulating film on the substrate, an amorphous semiconductor film on the insulating film, and a discharge of an inert gas under reduced pressure in a reaction chamber provided with a cathode;
A second step in which a plurality of types of elements contained in the cathode are released by sputtering and added to the amorphous semiconductor film; and the amorphous semiconductor film is crystallized by crystallizing the amorphous semiconductor film after the second step. And a third step of obtaining a film. 3. The method according to claim 1, wherein one of the plurality of elements contained in the cathode is a catalyst element that promotes crystallization of the amorphous semiconductor film, and the other one is the catalyst element. A method for manufacturing a semiconductor device, wherein an amorphous semiconductor film contains an impurity element imparting p-type conductivity. 4. The method according to claim 1, wherein
The steps (a) to (c) are continuously performed under reduced pressure without exposing the substrate to the atmosphere. 5. A first step of forming an amorphous semiconductor film on a substrate in a first reaction chamber and a discharge of an inert gas under reduced pressure in a second reaction chamber provided with a cathode. A second step of sputtering a cathode and simultaneously adding a catalyst element for promoting crystallization of the amorphous semiconductor film and an element for imparting p-type to the amorphous semiconductor film; A step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the step. 6. In a first reaction chamber, a first step of forming an insulating film on a substrate and an amorphous semiconductor film on the insulating film, and a second reaction chamber provided with a cathode, The cathode is sputtered by discharge of an inert gas under reduced pressure, and a catalyst element for promoting crystallization of the amorphous semiconductor film and an element for imparting p-type are simultaneously added to the amorphous semiconductor film. A method for manufacturing a semiconductor device, comprising: a second step; and a third step of crystallizing the amorphous semiconductor film after the second step to form a crystalline semiconductor film. 7. A first step of forming an amorphous semiconductor film on a substrate in a first reaction chamber, and an inert gas and a periodic gas under reduced pressure in a second reaction chamber provided with a cathode. The cathode is sputtered by discharge with a gas mixture containing a gas containing a Group 13 element, and the catalyst element that promotes crystallization of the amorphous semiconductor film contained in the cathode and the Group 13 element of the periodic rule are formed. A second step of simultaneously adding the amorphous semiconductor film to the amorphous semiconductor film; and a third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the second step. Of manufacturing a semiconductor device. 8. In a first reaction chamber, a first step of forming an insulating film on a substrate and an amorphous semiconductor film on the insulating film, and a second reaction chamber provided with a cathode, The cathode is sputtered by discharge with a mixed gas of an inert gas and a gas containing a Group 13 element under reduced pressure, and a catalyst element that promotes crystallization of the amorphous semiconductor film contained in the cathode, A second step of simultaneously adding the group 13 element of the periodic rule to the amorphous semiconductor film, and crystallizing the amorphous semiconductor film after the second step to form a crystalline semiconductor film. A method for manufacturing a semiconductor device, comprising: a third step. 9. The method according to claim 5, wherein the first step and the second step are continuously performed under reduced pressure without exposing the substrate to the atmosphere. Of manufacturing a semiconductor device. 10. A first step of forming an amorphous semiconductor film in a first reaction chamber, and discharge of an inert gas under reduced pressure in a second reaction chamber provided with a first cathode. A second step of releasing a catalyst element that promotes crystallization of the amorphous semiconductor film from the elements contained in the first cathode by sputtering and adding the catalyst element to the amorphous semiconductor film; After the step, in the second reaction chamber provided with the second cathode, by discharging the inert gas under reduced pressure,
A third step in which, of the elements contained in the second cathode, an element that imparts p-type to the amorphous semiconductor film is released by sputtering and added to the amorphous semiconductor film; A fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the step. 11. A first step of forming an amorphous semiconductor film in a first reaction chamber and a discharge of an inert gas under reduced pressure in a second reaction chamber provided with a first cathode. Among the elements contained in the first cathode, the amorphous semiconductor film has p
A second step of releasing an element for imparting a mold by sputtering and adding the element to the amorphous semiconductor film; and after the second step, a pressure reduction is performed in a third reaction chamber provided with a second cathode. Due to the discharge of the inert gas below, of the elements contained in the second cathode, a catalytic element that promotes crystallization of the amorphous semiconductor film is released by sputtering and added to the amorphous semiconductor film. A method for manufacturing a semiconductor device, comprising: a third step; and a fourth step of crystallizing the amorphous semiconductor film after the third step to form a crystalline semiconductor film. 12. A first reaction chamber for forming an insulating film on a substrate in a first reaction chamber, an amorphous semiconductor film on the insulating film, and a second reaction chamber provided with a first cathode. Then, by the discharge of the inert gas under reduced pressure, a catalyst element that promotes crystallization of the amorphous semiconductor film among the elements contained in the first cathode is released by sputtering, and the amorphous semiconductor film In the third reaction chamber provided with the second cathode, and discharge of the inert gas under reduced pressure to form the amorphous material among the elements contained in the second cathode. A third step in which an element imparting p-type to the semiconductor film is released by sputtering and added to the amorphous semiconductor film; and the amorphous semiconductor film is crystallized by crystallizing the amorphous semiconductor film after the third step. And a fourth step of forming a film. The method for manufacturing a conductor arrangement. 13. A second reaction chamber provided with an insulating film on a substrate in a first reaction chamber, an amorphous semiconductor film on the insulating film, and a first cathode. Then, by the discharge of the inert gas under reduced pressure, among the elements contained in the first cathode, an element imparting p-type to the amorphous semiconductor film is released by sputtering, and the amorphous semiconductor film is discharged to the amorphous semiconductor film. A second step of adding, and a third step provided with a second cathode.
In the reaction chamber, by discharging an inert gas under reduced pressure, a catalyst element that promotes crystallization of the amorphous semiconductor film among the elements contained in the second cathode is released by sputtering, and the amorphous A semiconductor device comprising: a third step of adding a crystalline semiconductor film to the amorphous semiconductor film; and a fourth step of crystallizing the amorphous semiconductor film after the third step to form a crystalline semiconductor film. Method of manufacturing. 14. A first step of forming an amorphous semiconductor film in a first reaction chamber and sputtering of said cathode by discharge of an inert gas under reduced pressure in a second reaction chamber provided with a cathode. A second step of simultaneously adding a catalyst element that promotes crystallization of the amorphous semiconductor film and an element that imparts p-type to the amorphous semiconductor film; and after the second step, A third step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film, a fourth step of patterning the crystalline semiconductor film to form a semiconductor film divided into islands, Performing a heat treatment after the fifth step of forming an insulating film on the semiconductor film divided into the shape, and performing the heat treatment after the fifth step.
And a sixth step of gettering the catalyst element in the island-shaped divided semiconductor film. 15. A first step of forming an amorphous semiconductor film in a first reaction chamber and a discharge of an inert gas under reduced pressure in a second reaction chamber provided with a first cathode. A second step of releasing a catalyst element that promotes crystallization of the amorphous semiconductor film from the elements contained in the first cathode by sputtering and adding the catalyst element to the amorphous semiconductor film; After the step, in the second reaction chamber provided with the second cathode, by discharging the inert gas under reduced pressure,
A third step in which, of the elements contained in the second cathode, an element that imparts p-type to the amorphous semiconductor film is released by sputtering and added to the amorphous semiconductor film; A fourth step of crystallizing the amorphous semiconductor film to form a crystalline semiconductor film after the step, and a fifth step of patterning the crystalline semiconductor film to form a semiconductor film divided into islands. A sixth step of forming an insulating film on the semiconductor film divided into islands, and performing a heat treatment after the sixth step to getter the catalyst element in the semiconductor film divided into islands. And a seventh step of ringing. 16. A first step of forming an amorphous semiconductor film in a first reaction chamber and a discharge of an inert gas under reduced pressure in a second reaction chamber provided with a first cathode. Among the elements contained in the first cathode, p is added to the amorphous semiconductor film.
A second step of releasing an element for imparting a mold by sputtering and adding the element to the amorphous semiconductor film; and after the second step, a pressure reduction is performed in a third reaction chamber provided with a second cathode. Due to the discharge of the inert gas below, of the elements contained in the second cathode, a catalytic element that promotes crystallization of the amorphous semiconductor film is released by sputtering and added to the amorphous semiconductor film. A third step, a fourth step of crystallizing the amorphous semiconductor film after the third step to form a crystalline semiconductor film, and dividing the crystalline semiconductor film into islands by patterning A fifth step of forming a semiconductor film, a sixth step of forming an insulating film on the semiconductor film divided into islands, and a heat treatment performed after the sixth step to divide the semiconductor film into islands. Gets the catalyst element in the semiconductor film The method for manufacturing a semiconductor device, characterized in that it comprises a seventh step of grayed. 17. The method for manufacturing a semiconductor device according to claim 10, wherein the first to third steps are continuously performed under reduced pressure. 18. The method according to claim 5, wherein the catalytic element is F
e, Co, Ni, Ru, Rh, Pd, Os, Ir, P
A method for manufacturing a semiconductor device, comprising using one or more elements selected from t, Cu, and Au. 19. The p-type impurity element according to claim 5, wherein the impurity element imparting p-type is one or more selected from B, Al, and Ga. A method for manufacturing a semiconductor device, comprising: 20. The method according to claim 5, wherein the method of crystallizing the amorphous semiconductor film is performed by heating by heat conduction or radiation, or A method of irradiating with light such as laser light,
Alternatively, a method for manufacturing a semiconductor device, which is one selected from a method of simultaneously or sequentially combining the two methods. 21. The inert gas according to claim 5, wherein the inert gas is H.
A method for manufacturing a semiconductor device, which is one or more kinds selected from e, Ar, Kr, Ne, and N ₂ . 22. The semiconductor device according to claim 1, wherein hydrogen is added to the inert gas. Production method. 23. A semiconductor device comprising: a first reaction chamber for forming an amorphous semiconductor film; and a cathode containing a catalyst element for promoting crystallization of the amorphous semiconductor film and an impurity element for imparting p-type. A second reaction chamber, wherein the first reaction chamber and the second reaction chamber are connected so as to be able to move without exposing the substrate to the atmosphere, A semiconductor manufacturing apparatus, wherein means for introducing an inert gas is connected to the second reaction chamber. 24. A first reaction chamber for forming an amorphous semiconductor film, and a second reaction chamber having a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film. A third reaction chamber including a second cathode containing an impurity element that imparts p-type to a semiconductor, and a substrate is provided between the first reaction chamber and the third reaction chamber. Connected so as to be able to move without being exposed to the atmosphere,
A means for introducing an inert gas is connected to the first and third reaction chambers. 25. A semiconductor device comprising: a first reaction chamber for forming an amorphous semiconductor film; and a cathode containing a catalyst element for promoting crystallization of the amorphous semiconductor film and an impurity element for imparting p-type. A second reaction chamber and a third reaction chamber for performing heat treatment are provided, and the substrate is exposed to air between the first reaction chamber, the second reaction chamber, and the third reaction chamber. A semiconductor manufacturing apparatus, which is connected so as to be able to move without exposing, and a means for introducing an inert gas is connected to the second reaction chamber. 26. A first reaction chamber for forming an amorphous semiconductor film, and a second reaction chamber having a first cathode containing a catalytic element for promoting crystallization of the amorphous semiconductor film. A third reaction chamber provided with a second cathode containing an impurity element imparting a p-type to the semiconductor, and a fourth reaction chamber for performing a heat treatment, wherein the first to fourth reaction chambers are provided. Between the reaction chamber
The substrate is connected so as to be able to move without exposing the substrate to the atmosphere, and a means for introducing an inert gas is connected to the second reaction chamber and the third reaction chamber. Semiconductor manufacturing equipment. 27. A semiconductor device comprising: a first reaction chamber for forming an amorphous semiconductor film; a second reaction chamber having a cathode and an anode capable of holding a substrate on a side facing the cathode. The first reaction chamber and the second reaction chamber are connected so that the substrate can move without exposing the substrate to the atmosphere, and the second reaction chamber is not connected to the first reaction chamber. A semiconductor manufacturing apparatus to which means for introducing an active gas is connected. 28. The cathode according to claim 27, wherein a target comprising a catalytic element for promoting crystallization of the amorphous semiconductor film and a target comprising an impurity element for imparting p-type to the semiconductor are arranged on the cathode. A semiconductor manufacturing apparatus. 29. The cathode according to claim 27, wherein the cathode has a surface made of a catalyst element that promotes crystallization of the amorphous semiconductor film, and a target made of an impurity element that imparts p-type to the semiconductor is provided. A semiconductor manufacturing apparatus. 30. The cathode according to claim 27, wherein the cathode has a surface made of an impurity element that imparts p-type to the semiconductor, and a target made of a catalyst element that promotes crystallization of the amorphous semiconductor film is provided. A semiconductor manufacturing apparatus.