JP2002354429A - Image signal processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To pass data between asynchronous time bases using a universal memory. SOLUTION: An A/D conversion section 1 converts an analog input image signal to digital input data by an input system CLK. An asynchronous buffer 2 converts input data being driven by the input system CLK to write data being driven by a higher frequency output system CLK than the frequency of the input system CLK. A frame memory 3 having a universal memory composed by a single port memory cell stores write data in the output system CLK, and reads the stored data in the output system CLK for outputting read data. Then, a D/A conversion section 5 converts the read data to an analog display image signal by the output system CLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus having a time axis conversion function for converting data of a video signal driven by a certain clock into data driven by a different clock that is asynchronous with the clock. It is about.

[0002]

2. Description of the Related Art FIG.
FIG. 1 is a block diagram showing a configuration of a conventional video signal processing device disclosed in Japanese Patent Application Laid-Open Publication No. H10-209, in which reference numeral 91 denotes an analog first
AD (Analog) that converts the video signal of the first input into digital first write data by a first input system clk (clock).
A digital (Digital) converter 92, an AD converter for converting an analog second video signal into digital second write data by a second input system clk; 93, a first write data from the AD converter 91; A switching unit that switches the second write data from the AD conversion unit 92 and outputs the first or second write data.

In FIG. 14, reference numeral 94 denotes a dual port memory cell which stores write data in a first input system clk or a second input system clk, and stores the stored data in an output system clk. A read frame memory 95 is a DA for converting read data from the frame memory 94 into an analog display video signal by an output system clk.
(Digital Analog) converter, 96 is the first
A switching instruction signal is output to the switching unit 93 on the basis of the first input synchronization signal of the input video signal or the second input synchronization signal of the second input video signal, and a write / read request signal is output to the frame memory 94. Is a control unit that outputs

Next, the operation will be described. AD converter 9
1 converts an analog first video signal into digital first write data by a first input system clk,
Reference numeral 2 converts an analog second video signal into digital second write data by a second input system clk. Control unit 96
Outputs a switching instruction signal to the switching unit 93 based on the first or second input synchronization signal of the first or second video signal, and outputs the first write data or the first write data from the AD conversion unit 91 for one frame period. The switching unit 93 is controlled so that the second write data from the AD conversion unit 92 is input to the frame memory 94.

The frame memory 94 is composed of a dual-port memory cell, and the first or second memory cell is switched by a write request signal from the control unit 96 at that time.
The AD conversion unit 91 or the AD conversion unit 92
Are stored via one port in the first input system clk or the second input system clk that is operating, and are stored via the other port in the output system clk in response to a read request signal from the control unit 96. Read the data that is stored. DA converter 9
5 is an output system c for reading data from the frame memory 94.
The signal is converted into an analog display video signal by lk and output.

The first and second input video signals to be input and the display video signal to be output are system-synchronized,
Except in the special case where the AD converters 91 and 92 and the DA converter 95 can be operated with the same clock,
As shown in FIG. 14, clocks for AD-converting a plurality of separate video signals are asynchronous with each other.
The clock for A-conversion uses a clock different from the clock for AD-conversion. Therefore, the frame memory 9
In 4, the first or second input system clk for storing the first or second write data and the output system clk for reading the stored data are separate clocks. In this case, data must be exchanged on an asynchronous time axis, and the frame memory 94 needs to be configured with dual-port memory cells.

[0007]

Since the conventional video signal processing apparatus is configured as described above, when data transfer on an asynchronous time axis is required, a frame composed of dual port memory cells is required. A memory must be used, and a general-purpose memory composed of single-port memory cells, such as SRAM (Static RAM) or DR
There is a problem that the cost is higher than that of an AM (Dynamic RAM). Further, even when a VRAM (video memory) having a dual-port configuration by adding a shift register to an SRAM or a DRAM as a general-purpose memory is used, there is a problem that the cost is similarly increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has a general purpose memory such as an SRAM or a DR.
It is an object of the present invention to obtain an inexpensive video signal processing device which can transfer data between asynchronous time axes using AM.

[0009]

A video signal processing apparatus according to the present invention drives input data driven by a first clock by a second clock having a frequency higher than that of the first clock. An asynchronous buffer that converts write data and a general-purpose memory configured with a single-port memory cell that stores the write data with a second clock, reads the stored data with the second clock, and outputs read data And a frame memory.

In the video signal processing apparatus according to the present invention, the asynchronous buffer generates a parallel instruction signal which becomes significant once every two cycles of the first clock, and outputs the input data for one cycle of the first clock, One cycle of input data immediately before one clock is held, and one cycle of input data and one
The input data for the cycle is parallelized with the parallel instruction signal to generate parallel data, and during the period when the parallel instruction signal is insignificant,
A time axis conversion instruction signal that is significant for one cycle of the second clock at a transition point of the second clock is generated, the parallel data is held, and the second clock is output during a period in which the time axis conversion instruction signal is significant. By outputting the parallel data held at the change point of, the parallel data with the time axis converted is generated,
When the time axis conversion instruction signal is reset at a transition point of the second clock during a significant period and generates a state signal that is sequentially incremented at the next transition point of the second clock, and the state signal indicates a predetermined value Then, the parallel data whose time axis has been converted is converted into serial data and output as write data.

In the video signal processing device according to the present invention, the asynchronous buffer drives the input data driven by the first clock with a second clock having a frequency twice or more the frequency of the first clock. This is converted into write data.

[0012] In the video signal processing apparatus according to the present invention, the asynchronous buffer may be configured such that the time base conversion in which the first clock is significant during one significant period of the second clock at the transition point of the second clock is significant. An input signal whose time axis has been converted is generated by generating an instruction signal, holding the input data, and outputting the input data held at the transition point of the second clock during a period in which the time axis conversion instruction signal is significant. Generating data, generating a state signal in which the time axis conversion instruction signal is reset at a transition point of the second clock during a significant period and incremented at the next transition point of the second clock; When indicating a value, the input data whose time axis has been converted is output as write data.

A video signal processing apparatus according to the present invention has a first
Frame memory having a general-purpose memory composed of a single-port memory cell for storing write data driven by a first clock, reading the stored data with a first clock, and outputting read data And read data driven by the first clock,
An asynchronous buffer for converting output data driven by a second clock having a lower frequency than that of the first clock.

In the video signal processing apparatus according to the present invention, the asynchronous buffer holds read data read from the frame memory for a predetermined period by a write pointer that counts a first clock, and an output that counts a second clock. By selecting and outputting the read data held by the pointer, the read data whose time axis has been converted is output as output data.

In the video signal processing device according to the present invention, the asynchronous buffer compares the value of the write pointer with the value of the output pointer and sequentially reads out the read data from the frame memory.

A video signal processing apparatus according to the present invention has a first
A first asynchronous buffer for converting input data driven by the clock of the first clock into write data driven by a third clock having a frequency higher than the frequency of the first clock;
A frame memory having a general-purpose memory composed of a single-port memory cell for storing write data at a third clock, reading the stored data at the third clock, and outputting read data; A second asynchronous buffer for converting the read data being driven into output data driven by a second clock having a lower frequency than the frequency of the third clock.

The video signal processing apparatus according to the present invention has a first
Is used to convert input data driven by the first clock into write data driven by a third clock having a frequency twice or more the frequency of the first clock.

The video signal processing apparatus according to the present invention has the NT
An NTSC decoder for converting an SC-compatible input video signal into digital input data at a first clock, a pixel sample rate conversion filter for converting an image aspect ratio of the input data to output write data, and A frame memory having a general-purpose memory composed of a single-port memory cell for storing data at a first clock, reading stored data at the first clock, and outputting read data; and a frame memory driven by the first clock. Read data having a frequency higher than the frequency of the first clock,
An asynchronous buffer for converting output data driven by a second clock which is a VGA-compliant clock which is a control standard of the graphics display.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of a video signal processing device according to Embodiment 1 of the present invention. In the figure, reference numeral 1 denotes an AD which converts an analog input video signal into digital input data by an input system clk (first clock).
The conversion unit 2 is an asynchronous buffer that converts input data driven by the input system clk into write data driven by the output system clk (second clock).

In FIG. 1, reference numeral 3 denotes an SRAM or D which is a general-purpose memory composed of single-port memory cells.
A frame memory that uses a RAM to store write data from the asynchronous buffer 2 by an output system clk and reads stored data by an output system clk, and 5 stores digital read data read from the frame memory 3. A DA converter 6 for converting an analog display video signal into an analog display video signal in an output system clk 6 outputs an input request signal to an asynchronous buffer 2 based on an input synchronization signal of the input video signal, and outputs an address signal and an output request signal to a frame memory 3. Is a control unit that outputs

Next, the operation will be described. Here, it is assumed that the frequency of the output system clk is higher than the frequency of the input system clk. The AD converter 1 converts an analog input video signal into digital input data by an input system clk. The control unit 6 outputs an input request signal indicating a cycle in which write data is determined to the asynchronous buffer 2 based on the input synchronization signal of the input video signal and the input system clk, and outputs a general-purpose memory used in the frame memory 3. An address signal indicating a write address is output to the frame memory 3.

The asynchronous buffer 2 receives an input request signal from the controller 6 and converts input data from the AD converter 1 driven by the input system clk into write data driven by the output system clk. Output to the frame memory 3 together with the input request signal. The frame memory 3 receives an address signal from the control unit 6, inputs write data output from the asynchronous buffer 2 and an input request signal, and outputs an output signal cl.
The write data is stored using k.

The control unit 6 outputs an output request signal indicating a read cycle of stored data and an address signal indicating a read address of a general-purpose memory based on a display synchronization signal generated by measuring the output clk. Output to The frame memory 3 reads the stored data based on the output request signal and the address signal from the control unit 6 and outputs the read data to the DA conversion unit 5. The DA converter 5 converts the digital read data from the frame memory 3 into an analog display video signal using the output system clk. The display video signal output from the DA converter 5 is input to and displayed on an external display device together with the display synchronization signal output from the controller 6.

FIG. 2 is a block diagram showing the internal configuration of the frame memory 3. The write data input unit 31 receives the write data, the input request signal, and the address signal, and holds and selects the write data for a plurality of words during a standby time necessary for writing the write data to the general-purpose memory without any loss. Output. The operation management unit 33 receives an input request signal and an address signal output from the write data input unit 31, determines an operation to be performed next, and outputs the determined operation as a memory drive signal. The memory IF signal drive unit 34 outputs the write data input unit 3 based on the memory drive signal output from the operation management unit 33.
The write data from 1 is stored in a general-purpose memory 35 such as an SRAM or a DRAM composed of single-port memory cells.

The read data output unit 32 receives an output request signal and an address signal from the control unit 6 and outputs them to the operation management unit 33. The operation management unit 33 receives the output request signal and the address signal, determines an operation to be executed next, and outputs the operation as a memory drive signal. The memory IF signal drive unit 34 reads data stored in the general-purpose memory 35 based on the memory drive signal and outputs the data to the read data output unit 32.
The read data output section 32 holds the read data read from the general-purpose memory 35, selects the data without loss, and outputs the selected data to the DA conversion section 5.

Next, the operation of the asynchronous buffer 2 will be described in detail. FIG. 3 is a block diagram showing the internal configuration of the asynchronous buffer 2. In the figure, reference numeral 21 denotes a DFF (D-type flip-flop) operated by an input system clk, and 22 denotes a TFF (T-type flip-flop) operated by an input system clk. ,
Reference numeral 23 denotes an asynchronous control unit that operates on the output system clk, and 24 denotes a D with an EN (Enable) terminal that operates on the input system clk.
FF, 25 is a DF with an EN terminal that operates on the output system clk.
F and 26 are parallel / serial conversion circuits.

FIG. 4 is a timing chart showing the operation timing of each part of the asynchronous buffer 2. The DFF 21 delays the input data together with the input request signal by one cycle of the input system clk, and outputs the result as input data F including the input request signal. The TFF 22 has an input system clk as shown in FIG.
Is output once every two periods. The DFF 24 inputs and holds the input data L including the input request signal of the current cycle of the input system clk and the input data F including the input request signal of one cycle before held in the DFF 21, and as shown in FIG. When the parallel instruction signal input from the input terminal to the EN terminal is at the H level, the input system cl
At the rising edge of k, input data F and input data L
Is output.

The asynchronous control unit 23, as shown in FIG.
After the parallel instruction signal input from the TFF 22 changes from the H level to the L level, a time axis conversion instruction signal that becomes H level (significant) for one cycle of the output system clk at the rise of the output system clk is output to the DFF 25. I do. DFF25
4, the parallel data A from the DFF 24 is input, and as shown in FIG. 4, when the time axis conversion instruction signal input from the asynchronous control unit 23 to the EN terminal is at the H level, the time axis is input at the rising edge of the output system clk. Is output to the parallel / serial conversion circuit 26.

The asynchronous control unit 23, as shown in FIG.
When the time axis conversion instruction signal is at H level, it is initialized to 0 at the rising edge of the output system clk, incremented to 1 at the next rising edge of the output system clk,
k is incremented to 2 at the next rising edge of k, and is incremented to 2 at the rising edge of the output system clk at the next H level of the time axis conversion instruction signal.
Is output to the parallel-to-serial conversion circuit 26.

The parallel / serial conversion circuit 26 includes the asynchronous control unit 2
3 based on the state signal (0, 1, 2) output from
The parallel data B whose time axis has been converted from the DFF 25 is converted into serial data and output to the frame memory 3 as write data including an input request signal. That is, as shown in FIG. 4, when the status signal is 0, the first data of the parallel data B is output, and when the status signal is 1, the parallel data B is output.
Is output, and when the status signal is 2, no data is output.

FIG. 5 is a diagram for explaining the relationship between the state signal and the write data. As shown in FIG. 5, when the time axis conversion instruction signal is at the H level, the state signal is initialized to 0 at the rising edge of the output system clk, and is incremented to 1 or 2 at each rising edge of the output system clk. When the signal is 0, the first write data D0 of the parallel data B
Is output. When the status signal is 1, the second write data D1 of the parallel data B is output. When the status signal is 2, no write data is output. Thereafter, every time the time axis conversion instruction signal becomes H level, the state signal is reset to 0, and the parallel data B is sequentially converted to serial and the write data is output.

Thus, in the asynchronous buffer 2,
In order to sequentially output the write data synchronized with the output system clk, as shown in FIG. 4, it is sufficient that at least the state signals 0 and 1 always exist during one cycle of the time axis conversion instruction signal. That is, the period of the time axis conversion instruction signal may be two or more periods of the output system clk. Here, the period of the time axis conversion instruction signal is determined by the period of the parallel instruction signal, and the period of the parallel instruction signal is two periods of the input system clk. That is, it is sufficient that two cycles of the input system clk are equal to or more than two cycles of the output system clk, and the frequency of the output system clk is equal to the input system clk.
It suffices if the frequency is higher than lk.

In this embodiment, the H level of the parallel instruction signal and the time axis conversion instruction signal is significant, but it is also possible to adopt a circuit configuration in which the L level is significant. Further, the operation timing is determined at the changing point of the rising edge of the input system clk and the output system clk.
It is also possible to adopt a circuit configuration in which the operation timing is determined at the changing point of each falling edge.

In this embodiment, an A / D converter 1 and a D / A converter 5 are provided as a video signal processing device. Digital input data driven by an input system clk is input from the outside and output. Digital read data driven by the system clk may be output to the outside.

As described above, according to the first embodiment, the asynchronous buffer 2 connected in front of the frame memory 3 converts the input data driven by the input system clk into an output having a higher frequency than the input system clk. The time axis is converted to write data driven by the system clk, and the frame memory 3 writes and reads data with the same output system clk.
In the frame memory 3, a general-purpose memory 35 having a single-port memory structure can be used, and an effect that data can be exchanged between asynchronous time axes without loss at low cost can be obtained.

According to the first embodiment, if the frequency of the output system clk is slightly higher than the frequency of the input system clk, the time base conversion can be performed in the asynchronous buffer 2 and the circuit operation speed can be greatly reduced. Since it is not necessary to increase the power consumption, the effect that the power consumption of the video signal processing device can be suppressed can be obtained.

Embodiment 2 In the first embodiment, an example is shown in which the frequency of the output system clk is higher than the frequency of the input system clk and data transfer between the asynchronous time axes is performed without loss. If the frequency of the output system clk is twice or more higher than the frequency of the input system clk, the input data input to the asynchronous buffer 2 can be output as write data without any loss. The video signal processing apparatus according to the second embodiment is configured such that the frequency of the output system clk is twice or more higher than the frequency of the input system clk, and the overall configuration is the same as that of FIG. 1 of the first embodiment. The internal configuration of the frame memory 3 is the same as that of the first embodiment shown in FIG.

FIG. 6 is a block diagram showing the internal configuration of the asynchronous buffer 2 in the video signal processing device according to the second embodiment of the present invention. In the figure, reference numeral 27 denotes an input system clk.
, An asynchronous control unit that operates in the output system clk, 28 is a DFF with an EN terminal that operates in the output system clk, and 29 is an AND circuit.

Next, the operation will be described. FIG. 7 is a timing chart showing the operation timing of each part of the asynchronous buffer 2. As shown in FIG. 7, the asynchronous control unit 27 sets the time axis at which the output system clk becomes H level (significant) for one cycle of the output system clk at the first rising edge of the output system clk after the rise of the input system clk (significant). Outputs a conversion instruction signal. The DFF 28 receives the input data including the input request signal and, as shown in FIG.
When the time axis conversion instruction signal input to the N terminal is at H level, data C whose data is converted on the time axis at the rising edge of the output system clock is output.

As shown in FIG. 7, the asynchronous control unit 27
When the time axis conversion instruction signal is at the H level, the output system clk
Is initialized to 0 at the first rising edge of
The output system clk is incremented to 1 at the next rising edge of k, and the time axis conversion instruction signal is at the next H level.
Incremented until the first rising edge of
Is output to the AND circuit 29. The AND circuit 29 calculates the logical product of the status signal (0, 1) output from the asynchronous control unit 27 and the data C from the DFF 28, and outputs the result as write data including the input request signal. That is, as shown in FIG. 7, data C is sequentially output when the status signal is 0, and no data is output when the status signal is 1.

FIG. 8 is a diagram for explaining the relationship between the state signal and the write data. As shown in FIG. 8, when the time axis conversion instruction signal is at H level, the state signal is initialized to 0 at the first rising edge of the output system clk, and is incremented to 1 at the next rising edge of the output system clk. When the signal is 0, the write data D0, D1, D2 are sequentially output, and when the state signal is 1, no write data is output.

In the present embodiment, the H level of the input system clk and the time axis conversion instruction signal are significant, but a circuit configuration in which the L level is significant can be employed. Further, the operation timing is determined at the changing point of the rising edge of the input system clk and the output system clk.
It is also possible to adopt a circuit configuration in which the operation timing is determined at the changing point of each falling edge.

As described above, according to the second embodiment, the asynchronous buffer 2 connected in front of the frame memory 3 converts the input data driven by the input system clk to twice the frequency of the input system clk. The time axis is converted into the write data driven by the output system clk having a higher frequency, and the frame memory 3 writes and reads the data with the same output system clk. The memory 35 can be used, and there is an effect that data can be transferred between the asynchronous time axes without loss at low cost.

Further, according to the second embodiment, since the time base conversion can be performed in the asynchronous buffer 2 with a simple configuration, the circuit size can be reduced, and the required resource amount can be reduced. can get.

Embodiment 3 FIG. 9 is a block diagram showing a configuration of a video signal processing device according to a third embodiment of the present invention. In FIG.
This is an asynchronous buffer that converts output data driven by k. In the second embodiment, in the first embodiment,
Instead of the asynchronous buffer 2 provided before the frame memory 3 operating on the output system clk, an asynchronous buffer 4 is provided after the frame memory 3 operating on the input system clk.

In FIG. 9, the input request signal is directly output from the control unit 6 to the frame memory 3, and the asynchronous buffer 4 is transmitted to the frame memory 3 by the output control signal output from the control unit 6 to the asynchronous buffer 4. Outputs an output request signal. Other configurations are the same as those of the first embodiment shown in FIG. Further, the internal configuration of the frame memory 3 is the same as that of the first embodiment shown in FIG.

Next, the operation will be described. Input clk
Is higher than the frequency of the output system clk. The AD converter 1 converts an analog input video signal into digital write data by an input system clk. The control unit 6 outputs to the frame memory 3 an input request signal indicating a cycle in which write data is determined and an address signal indicating a write address of the general-purpose memory 35 based on the input synchronization signal of the input video signal and the input system clk. I do. The frame memory 3 stores the write data from the AD converter 1 using the input system clk based on the input request signal and the address signal from the controller 6.

The control section 6 outputs an output control signal for reading out data stored in the frame memory 3 to the asynchronous buffer 4 based on a display synchronization signal generated by measuring the output clk. The asynchronous buffer 4 outputs an output request signal indicating a read cycle of stored data to the frame memory 3 based on an output control signal from the control unit 6. The frame memory 3 reads the stored data based on the output request signal from the asynchronous buffer 4,
The read data is output to the asynchronous buffer 4.

The asynchronous buffer 4 converts read data driven by the input system clk into output data driven by the output system clk, and outputs the output data to the DA converter 5. The DA converter 5 converts the digital output data from the asynchronous buffer 4 into
The output system clk is used to convert to an analog display video signal. The display video signal output from the DA converter 5 is input to and displayed on an external display device together with the display synchronization signal output from the controller 6.

FIG. 10 is a block diagram showing the internal configuration of the asynchronous buffer 4. Reference numeral 41 denotes an input system clk and an output system clk.
k, a buffer control unit that operates on the frame memory 3
And 43, a selector for sequentially selecting read data stored in the buffer group 42 and outputting the read data to the DA converter 5 as output data. In the buffer controller 41, 41a is a write counter, and 41b is an output counter.

FIG. 11 is a timing chart showing the operation timing of each part of the asynchronous buffer 4. As shown in FIGS. 10 and 11, a display synchronization signal and an output period signal generated by timing the output system clk are input to the buffer control unit 41 as output control signals from the control unit 6. The write counter 41a and the output counter 41b are reset by the input display synchronization signal. The buffer control unit 41 outputs an output request signal that becomes H level (significant) for a predetermined time to the frame memory 3 according to the input display synchronization signal. The time during which the output request signal becomes H level (significant) is shorter than the time until the output period signal becomes H level (significant), and is determined by the capacity of the buffer group 42.

The frame memory 3 reads the stored data in response to the input output request signal, and the read data is input to the buffer group 42 of the asynchronous buffer 4. When the output request signal is at the H level, the write counter 41a of the buffer control unit 41 counts down the input system clk, increments the write pointer, and outputs it to the buffer group 42. The read data input to the buffer group 42 is
The data is written to each buffer in the buffer group 42 specified by the write pointer.

The output counter 41 b receives the output period signal, counts the output system clk, increments the output pointer, and outputs it to the selector 43. The selector 43 selects the data written in the buffer group 42 from each buffer based on the output pointer from the output counter 41b, and sequentially outputs the data as output data. Buffer group 4
When data is output from the buffer group 2 and the buffer group 42 becomes empty, an output request signal is output to the frame memory 3 as shown in FIG. Here, the availability of the buffer group 42 is determined by comparing the value of the write pointer output from the write counter 41a with the value of the output pointer output by the output counter 41b.

As described above, in order to output the data written in the buffer group 42 as output data without loss, the frequency of the input system clk for writing in the buffer group 42 is output from the buffer group 42. What is necessary is just to make it higher than the frequency of an output system clock. That is, the frequency of the output system clock may be lower than the frequency of the input system clk.

In this embodiment, an A / D converter 1 and a D / A converter 5 are provided as a video signal processing apparatus. Digital write data driven by an input system clk is input from the outside, and an output system clk is input. May be output to the outside.

As described above, according to the third embodiment, the asynchronous buffer 4 connected after the frame memory 3 transfers the read data driven by the input system clk to the output system having a lower frequency than the input system clk. The time axis is converted into output data driven by the clk, and the frame memory 3 performs writing and reading of data with the same input system clk.
In the frame memory 3, a general-purpose memory 35 having a single-port memory structure can be used, and an effect that data can be exchanged between asynchronous time axes without loss at low cost can be obtained.

According to the third embodiment, if the frequency of the output system clk is slightly lower than the frequency of the input system clk, the time base conversion in the asynchronous buffer 4 can be executed, and the circuit operation speed can be greatly reduced. Since it is not necessary to increase the power consumption, the effect that the power consumption of the video signal processing device can be suppressed can be obtained.

Embodiment 4 FIG. 12 is a block diagram showing a configuration of a video signal processing device according to a fourth embodiment of the present invention. This embodiment is a combination of the first and third embodiments. Each configuration in FIG. 12 is equivalent to FIG. 1 of the first embodiment and FIG. 9 of the third embodiment, and the frame memory 3 is the same as FIG. 2 of the first embodiment, and the asynchronous buffer 2 (the first asynchronous buffer) is the same as the first embodiment. The asynchronous buffer 4 (second asynchronous buffer) of FIG. 3 of the first embodiment is the same as that of FIG. 10 of the third embodiment.

Next, the operation will be described. In this embodiment, three types of clocks are used: an input system clk used in the AD converter 1, an output system clk used in the DA converter 5, and a memory system clk (third clock) used in the frame memory 3. And the frequency of the memory system clk is
It is higher than the frequency of lk and the frequency of the output system clk.

The asynchronous buffer 2 converts the input data driven by the input system clk from the AD converter 1 into a write data driven by the memory system clk having a higher frequency on a time axis basis, and has a single-port memory structure. The frame memory 3 using the general-purpose memory 35 writes and reads data in the same memory system clk, and the asynchronous buffer 4 transfers read data driven by the memory system clk to the output system clk having a lower frequency. The time axis is converted into output data to be driven.

The operation of the asynchronous buffer 2 is the same as that of the first embodiment shown in FIGS. 3 and 4 in which the output system clk is replaced by a memory system clk. The operation of the asynchronous buffer 4 is also the same as that of the third embodiment. Input system c in FIG.
This is similar to the case where lk is changed to a memory system clk, and the asynchronous buffer 2 and the asynchronous buffer 4 exchange data without loss when performing time axis conversion.

In this embodiment, an A / D converter 1 and a D / A converter 5 are provided as a video signal processing device. Digital input data driven by an input system clk is input from the outside, and an output system clk is input. May be output to the outside.

As described above, according to the fourth embodiment, the asynchronous buffer 2 connected in front of the frame memory 3 converts the input data driven by the input system clk into a memory having a higher frequency than the input system clk. The time axis is converted to write data driven by the system clk, the frame memory 3 writes and reads data in the same memory system clk, and the asynchronous buffer 4 connected after the frame memory 3 is driven by the memory system clk. Read data to be read from the memory system cl.
By converting the time axis into output data driven by the output system clk having a frequency lower than k, the frame memory 3 can use the general-purpose memory 35 having a single-port memory structure, and the asynchronous time axis can be manufactured at low cost. An effect is obtained that data can be transferred between the devices without any loss.

According to the fourth embodiment, the frequency of the memory system clk is equal to the frequency of the input system clk and the output system clk.
If the frequency is slightly higher than the frequency lk, the time base conversion in the asynchronous buffer 2 and the asynchronous buffer 4 can be executed,
Since the circuit operation speed does not need to be significantly increased, the effect that the power consumption of the video signal processing device can be suppressed can be obtained.

Embodiment 5 The configuration of the video signal processing device according to the fifth embodiment of the present invention is similar to that of the fourth embodiment shown in FIG.
The configuration of the asynchronous buffer 2 is the same as the configuration shown in FIG. 6 of the second embodiment.

Next, the operation will be described. The operation of the asynchronous buffer 2 is the same as that of the second embodiment shown in FIGS. 6 and 7 in which the output system clk is replaced with a memory system clk, and the input data driven by the input system clk from the AD converter 1 is used. Is subjected to time axis conversion to write data driven by the memory system clk having a frequency of twice or more the frequency of the input system clk, and data transfer without loss is performed. Other operations are the same as in the fourth embodiment.

As described above, according to the fifth embodiment, the asynchronous buffer 2 connected in front of the frame memory 3 converts the input data driven by the input system clk to twice the frequency of the input system clk. The time axis is converted to write data driven by the memory system clk having the above frequency, the frame memory 3 performs writing and reading of data with the same memory system clk, and the asynchronous buffer 4 connected after the frame memory 3 Read data driven by the system clk is
By converting the time axis to output data driven by the output system clk whose frequency is lower than that of the memory system clk, the frame memory 3 can use the general-purpose memory 35 having a single-port memory structure. An effect is obtained that data can be transferred between time axes without loss.

Further, according to the fifth embodiment, since the time base conversion can be performed in the asynchronous buffer 2 with a simple configuration, the circuit size can be reduced, and the required resource amount can be reduced. can get.

Embodiment 6 FIG. FIG. 13 is a block diagram showing a configuration of a video signal processing apparatus according to Embodiment 6 of the present invention. In FIG. 13, reference numeral 7 denotes an analog NTSC (Nat
ionical Television System C
omitte) is converted to a luminance signal Y
And an NTSC decoder 8 for converting digital YUV data (input data) based on the color difference signals U and V, and a pixel sample rate conversion filter 8 for converting the aspect ratio of an image in the input data, and 720 pixels / 1H (one horizontal period) Is converted to 640 pixels / 1H. Other frame memories 3 (including a high-speed SRAM and an SRAM IF circuit), an asynchronous buffer 4, and a control unit 6 have the same configuration as that of the third embodiment.

Next, the operation will be described. The input system clk used here is an NTSC-compatible clock having a frequency of 27 MHz, and the output system clk has a frequency of 24.576.
MHz, a VGA (Variable Graphics Ars) which is a control standard for graphics displays.
(ray) corresponding clock. That is, this video signal processing device realizes a function as a format conversion device that converts a time axis compatible with NTSC into a time axis compatible with VGA.

Using the input system clk, the NTSC decoder 7 converts an analog NTSC-compatible input video signal into digital YUV data (input data) based on a luminance signal Y and color difference signals U and V, and converts the input data. Output to the pixel sample rate conversion filter 8 and input synchronization signal to the control unit 6
Output to The control unit 6 outputs a filter output instruction signal for converting the aspect ratio of the image to the pixel sample rate conversion filter 8 based on the input synchronization signal, and outputs an address signal supporting a write address of the general-purpose memory 35 to the frame memory 3. Is output.

The pixel sample rate conversion filter 8 receives the filter output instruction signal from the control unit 6 and
Use k to convert the image aspect ratio. That is, the YUV data of 720 pixels / 1H (one horizontal period) is converted into 640 pixels / 1H to prevent a true circle from being displayed as an ellipse.
It outputs to the frame memory 3 write data obtained by converting the aspect ratio of the image and an input request signal indicating a cycle in which the write data is determined. Other operations of the frame memory 3, the asynchronous buffer 4, and the control unit 6 are the same as those in the third embodiment. However, the asynchronous buffer 4 drives read data driven by the input system clk by the output system clk. Performs time axis conversion on output data. That is, the asynchronous buffer 4 converts a time axis corresponding to NTSC into a time axis corresponding to VGA.

As described above, according to the sixth embodiment, the asynchronous buffer 4 connected after the frame memory 3 converts the read data driven by the NTSC-compatible input system clk into a signal having a frequency lower than that of the input system clk. Time base conversion to output data driven by low VGA compatible output system clk,
Since the frame memory 3 performs writing and reading of data with the same input system clk, the frame memory 3 can use the general-purpose memory 35 having a single-port memory structure. An effect is obtained that data can be transferred without loss.

According to the sixth embodiment, the asynchronous buffer 4 has the output system cl having a frequency of 24.576 MHz.
k and an input system clk having a frequency of 27 MHz can be used to perform time-axis conversion, and it is not necessary to significantly increase the circuit operation speed, so that the effect of suppressing power consumption of the video signal processing device can be obtained. .

[0075]

As described above, according to the present invention, the first
An asynchronous buffer for converting input data driven by the clock of the second clock into write data driven by a second clock having a frequency higher than the frequency of the first clock, and storing the write data by a second clock; A frame memory having a single-port memory cell and a general-purpose memory configured of a single-port memory cell for reading the read data at a second clock and outputting the read data. Can be used, data can be exchanged between asynchronous time axes at a low cost without loss, and the circuit operation speed does not need to be significantly increased, so that the power consumption of the video signal processing device is suppressed. There is an effect that can be.

According to the present invention, the asynchronous buffer generates a parallel instruction signal which becomes significant once every two cycles of the first clock, and inputs the input data for one cycle of the first clock and the first clock. The input data for the immediately preceding cycle is held, and the input data for the one cycle and the input data for the immediately preceding cycle are parallelized by a parallel indication signal to generate parallel data. , A time-axis conversion instruction signal that is significant for one cycle of the second clock at the transition point of the second clock is generated, the parallel data is held, and during the period when the time-axis conversion instruction signal is significant, By outputting the parallel data held at the change point of the second clock, the parallel data whose time axis is converted is generated, and the time axis conversion instruction signal is generated at the change point of the second clock during a significant period. Reset and the second clock By generating a state signal which is sequentially incremented at the next change point of the frame, and when the state signal indicates a predetermined value, the parallel data whose time axis is converted is converted into serial data and output as write data, thereby obtaining a frame. As the memory, a general-purpose memory having a single-port memory structure can be used, and data can be transferred between asynchronous time axes without loss at a low cost, and the circuit operation speed does not need to be significantly increased. Therefore, there is an effect that the power consumption of the video signal processing device can be suppressed.

According to the present invention, the asynchronous buffer converts the input data driven by the first clock into the write data driven by the second clock having a frequency twice or more the frequency of the first clock. By converting, a general-purpose memory having a single-port memory structure can be used in the frame memory, and data can be transferred between the asynchronous time axes at a low cost without any loss. Since the time axis conversion can be performed, the circuit scale can be reduced, and the required resource amount can be reduced.

According to the present invention, the asynchronous buffer generates the time axis conversion instruction signal that is significant for one cycle of the second clock at the transition point of the second clock during the significant period of the first clock. Then, the input data is held, and the input data held at the transition point of the second clock is output during the period in which the time axis conversion instruction signal is significant, thereby generating the input data with the time axis converted. When the time base conversion instruction signal is reset at a transition point of the second clock during a significant period to generate a state signal that is incremented at the next transition point of the second clock, and the state signal indicates a predetermined value. In addition, by outputting the input data with the converted time axis as write data, the frame memory can use a general-purpose memory having a single-port memory structure, and can be asynchronous at a low cost. Passing it is possible to do without missing data between between axes, because it requires a small circuit scale, there is an effect that it is possible to suppress the required resource amount.

According to the present invention, a single-port memory for storing write data driven by a first clock by a first clock, reading the stored data by the first clock, and outputting read data. A frame memory having a general-purpose memory composed of cells, and an asynchronous circuit for converting read data driven by a first clock into output data driven by a second clock having a lower frequency than the frequency of the first clock By providing a buffer, a general-purpose memory having a single-port memory structure can be used as the frame memory, so that data can be transferred between asynchronous time axes at a low cost without any loss and the circuit can be used. Since the operating speed does not need to be significantly increased, there is an effect that the power consumption of the video signal processing device can be suppressed. .

According to the present invention, the asynchronous buffer reads the read data read from the frame memory for a predetermined period,
By holding the first clock by a write pointer that has counted the first clock and by using the output pointer that has counted the second clock to select and output the held read data, the read data whose time axis has been converted is output data. As a result, the general-purpose memory having a single-port memory structure can be used in the frame memory, and data can be transferred between the asynchronous time axes without loss at a low cost and the circuit operation speed can be reduced. Therefore, the power consumption of the video signal processing device can be suppressed.

According to the present invention, the asynchronous buffer compares the values of the write pointer and the output pointer and sequentially reads out the read data from the frame memory, so that the frame memory uses the general-purpose memory having a single-port memory structure. Therefore, there is an effect that data can be exchanged between asynchronous time axes without loss at a low cost.

According to the present invention, the first asynchronous buffer for converting input data driven by the first clock into write data driven by the third clock having a higher frequency than the frequency of the first clock A frame memory having a general-purpose memory composed of a single-port memory cell for storing write data at a third clock, reading the stored data at the third clock, and outputting read data; A second asynchronous buffer for converting read data driven by the clock into output data driven by the second clock having a lower frequency than the frequency of the third clock; A general-purpose memory with a port memory structure can be used, eliminating the need to transfer data between asynchronous time axes at low cost. It is possible to do without, because it requires not significantly increase the circuit operating speed, there is an effect that it is possible to reduce power consumption of the video signal processing apparatus.

According to the present invention, the first asynchronous buffer drives the input data driven by the first clock by the third clock having a frequency twice or more the frequency of the first clock. By converting to write data,
In the frame memory, a general-purpose memory having a single-port memory structure can be used, and data can be transferred between asynchronous time axes at a low cost without loss, and the circuit scale can be reduced. There is an effect that the amount of resources can be suppressed.

According to the present invention, an NTSC decoder that converts an NTSC-compatible input video signal into digital input data with a first clock, and a pixel that converts the aspect ratio of an image in the input data to output write data A frame rate memory including a sample rate conversion filter, a general-purpose memory configured of a single-port memory cell for storing write data at a first clock, reading the stored data at the first clock, and outputting read data; The read data driven by the first clock to output data driven by a second clock having a frequency higher than the frequency of the first clock and corresponding to the VGA which is a control standard of the graphics display. With the provision of an asynchronous buffer for converting A general-purpose memory having a memory structure can be used, and data can be transferred between asynchronous time axes at a low cost without any loss. In addition, since the circuit operation speed does not need to be significantly increased, video signal processing can be performed. There is an effect that power consumption of the device can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a frame memory of the video signal processing device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing an internal configuration of an asynchronous buffer of the video signal processing device according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation timing of each part of the asynchronous buffer of the video signal processing device according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between a state signal of an asynchronous buffer and write data of the video signal processing device according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing an internal configuration of an asynchronous buffer of the video signal processing device according to the second embodiment of the present invention.

FIG. 7 is a timing chart showing the operation timing of each part of the asynchronous buffer of the video signal processing device according to the second embodiment of the present invention.

FIG. 8 is a diagram for explaining a relationship between a state signal of an asynchronous buffer and write data of a video signal processing device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a video signal processing device according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing an internal configuration of an asynchronous buffer of a video signal processing device according to a third embodiment of the present invention.

FIG. 11 is a timing chart showing the operation timing of each part of the asynchronous buffer of the video signal processing device according to the third embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a video signal processing device according to a fourth embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a video signal processing device according to Embodiment 6 of the present invention.

FIG. 14 is a block diagram illustrating a configuration of a conventional video signal processing device.

[Explanation of symbols]

1 AD converter, 2 asynchronous buffer, 3 frame memory, 4 asynchronous buffer, 5 DA converter, 6 controller, 7 NTSC decoder, 8 pixel sample rate conversion filter, 21 DFF, 22 TFF, 23 asynchronous controller, 24 DFF, 25 DFF, 26 parallel-serial conversion circuit, 27 asynchronous control unit, 28 DFF, 29 A
ND circuit, 31 write data input section, 32 read data output section, 33 operation management section, 34 memory IF signal drive section, 35 general-purpose memory, 41 buffer control section, 4
2 buffer group, 43 selector.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/391 G09G 5/00 520V H04N 5/907 (72) Inventor Hironobu Abe Marunouchi 2-chome, Chiyoda-ku, Tokyo No.2-3 Mitsubishi Electric Corporation F term (reference) 5C052 AA17 AB04 CC03 DD10 GA03 GB01 GD03 GE04 GF01 5C053 FA27 GA10 KA03 KA08 KA21 KA24 KA25 LA06 5C082 AA02 BB15 BB25 BC19 BD09 DA53 DA61 DA76 MM06

Claims (10)

[Claims] An asynchronous buffer for converting input data driven by a first clock into write data driven by a second clock having a frequency higher than the frequency of the first clock; A frame memory having a general-purpose memory formed of a single-port memory cell for storing the data at the second clock, reading the stored data at the second clock, and outputting the read data. Video signal processing device. 2. An asynchronous buffer generates a parallel instruction signal which is significant once in two cycles of a first clock, and inputs input data for one cycle of the first clock and the input data immediately before the first clock. The input data for one cycle is held, and the input data for one cycle and the input data for the immediately preceding cycle are parallelized by the parallel instruction signal to generate parallel data. During the period, a time axis conversion instruction signal that is significant for one cycle of the second clock at a transition point of the second clock is generated, the parallel data is held, and the time axis conversion instruction signal is significant. By outputting the parallel data held at the transition point of the second clock during the period, the parallel data whose time axis is converted is generated, and during the period when the time axis conversion instruction signal is significant, the second data is output. At the clock transition point A state signal that is set and sequentially incremented at the next transition point of the second clock is generated. When the state signal indicates a predetermined value, the time axis converted parallel data is converted to serial. 2. The video signal processing apparatus according to claim 1, wherein the video signal is output as write data. 3. An asynchronous buffer converts input data driven by a first clock into write data driven by a second clock having a frequency twice or more the frequency of the first clock. The video signal processing device according to claim 1, wherein: 4. An asynchronous buffer generates a time axis conversion instruction signal that is significant for one cycle of the second clock at a change point of the second clock during a period in which the first clock is significant. Holding the data, and outputting the input data held at the transition point of the second clock during the period in which the time axis conversion instruction signal is significant, thereby generating input data with the time axis converted, The time axis conversion instruction signal is reset at a change point of the second clock during a significant period to generate a state signal that is incremented at the next change point of the second clock, and the state signal has a predetermined value. 4. The video signal processing device according to claim 3, wherein the input device outputs the input data obtained by converting the time axis as write data. 5. A single-port memory cell for storing write data driven by a first clock by the first clock, reading the stored data by the first clock, and outputting read data. A frame memory having a configured general-purpose memory; and read data driven by the first clock.
A video signal processing device comprising: an asynchronous buffer that converts output data driven by a second clock having a lower frequency than the frequency of the first clock. 6. An asynchronous buffer holds read data read from a frame memory for a predetermined period by a write pointer that counts a first clock and a read data that is held by an output pointer that counts a second clock. 6. The video signal processing apparatus according to claim 5, wherein by selecting and outputting the data, the read data whose time axis has been converted is output as output data. 7. The video signal processing device according to claim 6, wherein the asynchronous buffer compares the values of the write pointer and the output pointer and sequentially reads out the read data from the frame memory. 8. A first asynchronous buffer for converting input data driven by a first clock into write data driven by a third clock having a higher frequency than the frequency of the first clock; A frame memory for storing write data at the third clock, reading the stored data at the third clock, and outputting read data; Read data driven by the clock of
A video signal processing device, comprising: a second asynchronous buffer that converts output data driven by a second clock having a lower frequency than the frequency of the third clock. 9. A first asynchronous buffer converts input data driven by a first clock to write data driven by a third clock having a frequency twice or more the frequency of the first clock. 9. The method according to claim 8, wherein the conversion is performed.
The video signal processing device according to the above. 10. NTSC (National Tel)
evolution System Committee)
An NTSC decoder for converting a corresponding input video signal into digital input data with a first clock, a pixel sample rate conversion filter for converting an aspect ratio of an image in the input data and outputting write data, A frame memory having a general-purpose memory composed of a single-port memory cell, which stores the data with the first clock, reads out the stored data with the first clock, and outputs the read data; Read data driven by
VGA (Var), which is a control standard of the graphics display and has a higher frequency than the frequency of the first clock,
a video signal processing device comprising: an asynchronous buffer that converts output data driven by a second clock, which is a clock corresponding to an enable graphics array.