JP2005284347A - Communication apparatus and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication apparatus capable of inexpensively performing normal data communication. <P>SOLUTION: An oscillator 81 generates an independent oscillator clock for operating a data processing part 26. A data decoder 25 BPSK-demodulates data to be transmitted from a reader/writer 1, synchronously with an RF clock generated from an RF signal from the reader/writer 1. In a rate converting part 82, data obtained as the result of the BPSK demodulation are written synchronously with the RF clock, and the written data are read synchronously with the independent oscillator clock generated by the oscillator 81. Also, in the rate converting part 82, the data to be transmitted to the reader/writer 1 are written synchronously with the oscillator clock, and the written data are read synchronously with the RF clock. In a data modulator 27, the data are BPSK-modulated, and transmitted to the reader/writer 1. The present invention is applicable to an IC card or a portable telephone or the like having the function of the IC card. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a communication device and a data processing method, and in particular, when an IC (Integrated Circuit) card or the like has a plurality of interfaces, normal data communication is performed at a low cost on each of the plurality of interfaces. The present invention relates to a communication device and a data processing method.

  In recent years, for example, remote IC (Integrated Circuit) card systems that perform non-contact communication have been introduced into railway ticket gates and the like.

  FIG. 1 shows an example of the configuration of a conventional remote IC card system.

  In FIG. 1, the remote IC card system includes a reader / writer 1 and an IC card 2. The reader / writer 1 reads or writes data to or from the IC card 2 by non-contact communication. write).

  That is, in the reader / writer 1, the oscillator 11 generates (generates) a carrier (carrier wave) having a predetermined frequency such as 13.56 MHz, and supplies the carrier to the frequency divider 12, the modulator 14, and the data decoder 17.

  The frequency divider 12 divides the carrier from the oscillator 11 to a frequency of 1 / N (N is an integer), and a clock having a frequency of 1 / N of the carrier (hereinafter referred to as 1 / N clock as appropriate). Is supplied to the data modulator 13.

  In addition to the 1 / N clock from the frequency divider 12, the data modulator 13 is supplied with data to be transmitted and written to the IC card 2. The data modulator 13 performs, for example, BPSK (Binary Phase Shift Keying) modulation (Manchester coding) on the data supplied thereto in synchronization with the 1 / N clock from the frequency divider 12 and obtains the result. Data is supplied to the modulator 14.

Here, the data modulator 13, as described above, since the synchronization with modulated to 1 / N clock from the frequency divider 12, when it represents the frequency of the carrier oscillator 11 outputs at f _c, The data rate of the data output from the data modulator 13 is f _c / N.

  The modulator 14 performs, for example, ASK (Amplitude Shift Keying) modulation on the carrier from the oscillator 11 in accordance with the data supplied from the data modulator 13, and supplies the resulting modulated signal to the antenna 15.

  The antenna 15 outputs an electromagnetic wave (RF (Radio Frequency) signal) corresponding to the modulation signal from the modulator 14. Further, the antenna 15 receives a so-called load-modulated modulated signal by the IC card 2 and supplies it to the demodulator 16.

  The demodulator 16 performs ASK demodulation on the modulation signal from the antenna 16, for example, and supplies data obtained as a result to the data decoder 17.

Data decoder 17, by performing synchronization with the processing clock of a frequency f _c of the carrier from the oscillator 11, the data from the demodulator 16, for example, (decodes Manchester code) by BPSK demodulation, the Output the resulting data.

  On the other hand, in the IC card 2, the antenna 21 receives the RF signal from the reader / writer 1 and supplies it to the RF detector 22 and the demodulator 24. Further, the antenna 21 causes the modulator 28 to vary the load viewed from the reader / writer 1 side, and thereby, the RF signal from the antenna 15 of the reader / writer 1 is load-modulated, thereby transmitting data to the reader / writer 1. To do.

When the reader / writer 1 and the IC card 2 are in close proximity to each other, the RF detector 22 detects the RF signal when the antenna 21 receives a sufficient level of the RF signal, and detects the RF signal from the RF signal. 11 outputs to the same frequency as the frequency f _c of the carrier clock (hereinafter referred to as RF clock) to generate the. The RF clock generated by the FR detector 22 is supplied to the frequency divider 23, the data decoder 25, and the data processing unit 26.

  In addition, when the RF detector 22 detects an RF signal, the RF detector 22 rectifies the RF signal to obtain a DC voltage and supplies it as a power source to necessary blocks constituting the IC card 2.

  The frequency divider 23 divides the RF clock from the RF detection circuit 22 to a frequency of 1 / N, and supplies the 1 / N clock obtained as a result to the data modulator 27.

Here, RF clock because it has the same frequency f _c and a carrier oscillator 11 outputs, by the frequency divider 23 divides the RF clock frequency of 1 / N, the frequency divider of the reader-writer 2 The same 1 / N clock as obtained at 12 is obtained.

  The demodulator 24 performs, for example, ASK demodulation on the RF signal (modulated signal) received from the reader / writer 1 received by the antenna 21 in the same manner as the demodulator 16 and supplies the data obtained as a result to the data decoder 25. .

  The data decoder 25 performs processing in synchronization with the RF clock from the RF detector 22 to demodulate the data from the demodulator 24, for example, as in the data demodulator 17, and the data obtained as a result thereof. Is supplied to the data processing unit 26.

  The data processing unit 26 has a built-in memory 26A composed of, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) or a RAM (Random Access Memory), and is synchronized with the RF clock from the RF detection unit 22. Necessary processing is performed on the data supplied from the data decoder 25 and stored in the memory 26A. The data processing unit 26 reads out data stored in the memory 26 </ b> A and supplies the data to the data modulator 27.

  The data modulator 27 performs, for example, BPSK modulation similarly to the data modulator 13 by processing the data from the data processing unit 26 in synchronization with the 1 / N clock from the frequency divider 23, and obtains the result. Is supplied to the modulator 28.

Here, since the data modulator 27 modulates in synchronization with the 1 / N clock from the frequency divider 23 as described above, the data rate of the data output from the data modulator 27 is the data modulator 13. There as well as data rate of the data to be output, is f c _{/ N.}

  The modulator 28 fluctuates the load of the antenna 21 according to the data supplied from the data modulator 27, thereby load-modulating the RF signal (carrier) output from the antenna 15 of the reader / writer 1, for example, ASK By performing the modulation, the data stored in the memory 26A is transmitted to the reader / writer 2.

  In the remote IC card system configured as described above, when the reader / writer 1 and the IC card 2 come close to each other, non-contact communication is performed between the reader / writer 1 and the IC card 2. Data exchange is performed.

  That is, when the reader / writer 1 writes data to the IC card 2 (when data is transmitted from the reader / writer 1 to the IC card 2), the data is supplied to the data modulator 13.

Data modulator 13, in synchronization with the 1 / N clock from the frequency divider 12, the data supplied thereto to BPSK modulation, the resulting data rate is a data f _{c /} N, modulator 14.

  The modulator 14 ASK-modulates the carrier supplied from the oscillator 11 according to the data supplied from the data modulator 13, and outputs the resulting RF signal (modulated signal) from the antenna 15 as an electromagnetic wave.

  The RF signal from the antenna 15 is received by the antenna 21 and supplied to the RF detector 22 and the demodulator 24.

  The RF detector 22 generates an RF clock from the RF signal from the antenna 21 and supplies the RF clock to the frequency divider 23, the data decoder 25, and the data processing unit 26.

  The demodulator 24 ASK-demodulates the RF signal from the reader / writer 1 received by the antenna 21, and supplies data obtained as a result to the data decoder 25.

  The data decoder 25 performs BPSK demodulation of the data from the demodulator 24 by performing processing in synchronization with the RF clock from the RF detector 22, and supplies the data obtained as a result to the data processing unit 26.

Here, the data rate of data supplied from the demodulator 24 to the data decoder 25 is equal to the data rate f _c / N of data supplied from the data modulator 13 to the modulator 14. Then, the data decoder 25 in synchronization with the RF clock frequency f _c, since the f _{c /} N that is a data rate of 1 / N of the frequency f _c to BPSK demodulation, accurately, extracting data (Data extraction (sampling) at the time of data BPSK demodulation) can be performed.

  In the data processing unit 26, the data supplied from the data decoder 25 is written in, for example, the memory 26A.

  On the other hand, when the reader / writer 1 reads data from the IC card 2 (when data is transmitted from the IC card 2 to the reader / writer 1), the carrier output from the oscillator 11 in the reader / writer 1 is modulated by the modulator 14. Instead, it is output from the antenna 15 as an RF signal.

  In the IC card 2, the RF signal from the reader / writer 1 is received by the antenna 21 and supplied to the RF detector 22 and the demodulator 24.

  The RF detector 22 generates an RF clock from the RF signal from the antenna 21 and supplies the RF clock to the frequency divider 23, the data decoder 25, and the data processing unit 26.

  The frequency divider 23 divides the RF clock from the RF detection circuit 22 to a frequency of 1 / N, and supplies the 1 / N clock obtained as a result to the data modulator 27.

  In the data processing unit 26, data to be transmitted to the reader / writer 1 is read from the memory 26 </ b> A and supplied to the data modulator 27.

  The data modulator 27 performs BPSK modulation on the data from the data processing unit 26 in synchronization with the 1 / N clock from the frequency divider 23, and supplies the resulting data to the modulator 28.

Here, since the data modulator 27 modulates data in synchronization with the 1 / N clock as described above, the data rate of the data supplied from the data modulator 27 to the modulator 28 is f _c / N.

  The modulator 28 varies the load of the antenna 21 viewed from the reader / writer 1 side according to the data supplied from the data modulator 27, and thereby the RF signal (carrier) output from the antenna 15 of the reader / writer 1 is changed. Perform load modulation, for example, ASK modulation.

  In the reader / writer 1, the demodulator 16 receives the RF signal (modulated signal) subjected to load modulation by the modulator 28 of the IC card 2, performs ASK demodulation, and converts the data obtained as a result into a data decoder 17 is supplied.

The data decoder 17, in synchronization with a clock frequency f _c of the carrier from the oscillator 11, the data from the demodulator 16 by BPSK demodulation, and outputs the resultant data.

Here, the data rate of the data supplied from the demodulator 16 to the data decoder 17 is equal to the data rate f _c / N of the data supplied from the data modulator 27 to the modulator 28. Then, the data decoder 17 in synchronization with the frequency f _c of the carrier clock, since the BPSK demodulated data f _{c /} N is a data rate of 1 / N of the frequency f _c, precisely, the data Extraction (data extraction at the time of data BPSK demodulation) can be performed.

As described above, in the remote IC card system of FIG. 1, each block of the reader-writer 1 and the IC card 2, since the process in synchronism with the frequency f _c of the carrier clock, extract the data (demodulated), It can be performed with high accuracy.

  In the IC card 2, for example, an antenna 21, a demodulator 24, a data decoder 25, a data modulator 27, and a modulator 28 are communication interfaces for performing non-contact communication with the reader / writer 1 (hereinafter referred to as appropriate). The non-contact communication interface).

  By the way, for example, Patent Document 1 proposes a mobile phone having the function of the IC card 2 as described above.

  Since the mobile phone having the function of the IC card 2 functions as an IC card as well as a mobile phone, it has a power source and an oscillator independently.

  In other words, the IC card 2 in FIG. 1 operates in a manner dependent on the reader / writer 1 by obtaining a power source and a clock from the RF signal from the reader / writer 1.

  On the other hand, the mobile phone having the function of the IC card 2 described in Patent Document 1 is a mobile phone, and more recently, various applications (for example, transmission / reception of e-mail, browsing of web pages, games, etc.) Since it is necessary to operate independently as a computer that executes the above, it has a built-in power supply and an oscillator that outputs a clock.

  Then, when a sufficient level RF signal from the reader / writer 1 can be detected, the mobile phone described in Patent Document 1 operates in synchronization with a clock obtained (generated) from the RF signal. If an RF signal with a sufficient level cannot be detected, it operates in synchronization with the clock output from the built-in oscillator.

JP 2003-036427 A.

  By the way, similarly to the mobile phone described in Patent Document 1, the IC card can also have the function of the IC card 2 in FIG. 1 and the function of a computer that executes various applications.

  FIG. 2 shows a configuration example of a remote IC card system using such an IC card.

  In FIG. 2, an IC card 31 has the functions of the IC card 2 of FIG. 1 and the functions of a computer that executes various applications.

  That is, the IC card 31 includes an IC card unit 41, a host computer 42, and an oscillator 43.

  The IC card unit 41 is configured similarly to the IC card 2 of FIG. However, like the IC card 2 in FIG. 1, the IC card unit 41 has a non-contact communication interface for performing non-contact communication with the reader / writer 1 and a communication interface for performing communication with the host computer 42. (Hereinafter referred to as computer communication interface as appropriate).

  The host computer 42 is composed of a CPU (Central Processing Unit) and the like, and executes various applications. The host computer 42 can exchange data with the IC card unit 41. Data exchange between the IC card unit 41 and the host computer 42 is performed, for example, by wire.

  The oscillator 43 generates a clock having a predetermined frequency, for example, a frequency similar to the frequency of the carrier output from the oscillator 11 of the reader / writer 1, and supplies the clock to the IC card unit 41.

  The IC card 31 is provided with a power supply for supplying power to the host computer 42 and the oscillator 43, but the illustration thereof is omitted in FIG.

  In the IC card 31 configured as described above, a sufficient level of RF signal from the reader / writer 1 is detected by the RF detector 22 of the IC card unit 41 configured in the same manner as the IC card 2 shown in FIG. If the reader / writer 1 and the IC card 31 are close to each other, an RF clock is generated from the RF signal from the reader / writer 1. The IC card unit 41 can exchange data with the reader / writer 1 by operating in synchronization with the RF clock.

  On the other hand, when the RF detector 22 (FIG. 1) of the IC card unit 41 cannot detect an RF signal with a sufficient level from the reader / writer 1, the IC card unit 41 outputs a clock output from the oscillator 43. For example, data can be exchanged with the host computer 42.

  In FIG. 2, the reader / writer 1 and the host computer 42 share the function of the data processing unit 26 (FIG. 1) of the IC card unit 41, that is, for example, the data processing unit 26 of the IC card unit 41. It is conceivable to exchange data by sharing the memory 26 </ b> A built in the computer.

  However, in this case, the data exchanged between the reader / writer 1 and the IC card unit 41 is not synchronized with the clock with which the reader / writer 1 or the IC card unit 41 is synchronized. At 41, it may be difficult to extract data for BPSK demodulation.

That is, first, the RF detector 22 (FIG. 1) of the IC card unit 41 detects an RF signal of a sufficient level from the reader / writer 1, and the IC card unit 41 generates an RF clock generated from the RF signal. When the non-contact communication C _radio is started between the reader / writer 1 and the IC card unit 41, the data received by the reader / writer 1 from the IC card unit 41 is as follows. The data received by the IC card unit 41 from the reader / writer 1 in synchronization with the clock (clock output from the oscillator 11) synchronized with the reader / writer 1 is also synchronized with the clock (RF detector 22). In the same way as in the case of the reader / writer 1 and the IC card 2 in FIG. 1, the reader / writer 1 and the IC card unit 41 are respectively synchronized with the data at the time of BPSK demodulation. The extraction can be performed accurately.

Thereafter, with the IC card 41 and the host computer 42, the communication C _wire for data exchange is initiated, the communication C _wire is not between the reader writer 1 and the IC card 41 Even if it is performed in parallel with the contact communication C _radio , the communication C _wire between the IC card unit 41 and the host computer 42 can be performed asynchronously (asynchronous communication may be sufficient), so that no particular problem occurs.

However, when the communication C _wire between the IC card unit 41 and the host computer 42 is started first, the IC card unit 41 starts operation in synchronization with the clock from the oscillator 43.

Therefore, after that, when the reader / writer 1 and the IC card unit 41 come close to each other and the non-contact communication _radio is started, the IC card unit 41 operates in synchronization with the clock from the oscillator 43. Therefore, if the clock output from the oscillator 43 is not a clock having a frequency close to the RF signal (carrier) of the reader / writer 1, the data received by the reader / writer 1 from the IC card unit 41 is synchronized with the reader / writer 1. The data that the IC card unit 41 receives from the reader / writer 1 is synchronized with the clock that the IC card unit 41 synchronizes (in this case, the oscillator 43 is connected to the oscillator 43). It may happen that the output clock is not synchronized with the output clock.

  As a result, it becomes difficult for the reader / writer 1 and the IC card unit 41 to extract data at the time of BPSK demodulation, and the IC card 31 has a compatibility problem with the conventional IC card 2.

  Therefore, as the oscillator 43 of the IC card 31, a highly accurate oscillator that outputs a clock having the same frequency as that of the carrier output from the oscillator 11 of the reader / writer 1 is used, so that the reader / writer 1 and the IC card unit 41 are connected. A method for preventing the exchanged data from becoming out of synchronization with the clock with which the reader / writer 1 or the IC card unit 41 is synchronized can be considered.

  However, a highly accurate oscillator is expensive, and when such an oscillator is used as the oscillator 43 of the IC card 31, the cost of the IC card 31 is increased.

  The present invention has been made in view of such circumstances, and for example, to provide a device that performs normal data communication at each of a plurality of interfaces such as a non-contact communication interface and a computer communication interface at a low cost. Is to be able to.

  The first communication device of the present invention includes a first clock generation unit that generates a first clock from a signal transmitted from another device, and a second clock that generates a second clock that is an independent clock. A clock generation means, a processing means for processing data transmitted from another device in synchronization with the first clock, and data processed in the processing means are written in synchronization with the first clock; And storage means for reading in synchronization with the second clock.

  In the first communication device, data to be transmitted to the other device is written in synchronization with the second clock, read out in synchronization with the first clock, and the first clock. Other processing means for processing data read from other storage means in synchronization can be further provided.

  In addition, data reception using the first and second clock generation means and processing means of the first communication device can be performed in a contactless manner, and data transmission to other devices can also be performed in a contactless manner. it can.

  The first data processing method of the present invention includes a writing step in which data processed by the processing means is written to the storage means in synchronization with a first clock generated from a signal transmitted from another device. And a reading step in which the data written in the storage means is read out in synchronization with the independent second clock.

  The second communication device of the present invention includes a first clock generating means for generating a first clock from a signal transmitted from another device, and a second clock for generating a second clock that is an independent clock. The clock generation means and the data to be transmitted to the other device are written in synchronization with the second clock, the storage means is read in synchronization with the first clock, and the data is stored in synchronization with the first clock. And processing means for processing data read from the means.

  Data reception using the first and second clock generation means and processing means of the second communication device can be performed in a contactless manner, and data transmission to other devices can also be performed in a contactless manner. .

  According to the second data processing method of the present invention, the data transmitted to the other device is written in the storage means in synchronization with the independent second clock, and the data written in the storage means is And a reading step that is read out in synchronization with a first clock generated from a signal transmitted from another device and is supplied to the processing means.

  In the first communication device and data processing method of the present invention, the data processed by the processing means is written to the storage means in synchronization with the first clock generated from the signal transmitted from the other device. It is. Further, the data written in the storage means is read in synchronization with the independent second clock.

  In the second communication apparatus and data processing method of the present invention, data transmitted to another apparatus is written to the storage means in synchronization with the independent second clock. Furthermore, the data written in the storage means is read in synchronization with the first clock generated from the signal transmitted from another device.

  According to the present invention, normal data communication can be performed at low cost.

  Embodiments of the present invention will be described below. Correspondences between constituent elements described in the claims and specific examples in the embodiments of the present invention are exemplified as follows. This description is to confirm that specific examples supporting the invention described in the claims are described in the embodiments of the invention. Therefore, even if there are specific examples that are described in the embodiment of the invention but are not described here as corresponding to the configuration requirements, the specific examples are not included in the configuration. It does not mean that it does not correspond to a requirement. On the contrary, even if a specific example is described here as corresponding to a configuration requirement, this means that the specific example does not correspond to a configuration requirement other than the configuration requirement. not.

  Further, this description does not mean that all the inventions corresponding to the specific examples described in the embodiments of the invention are described in the claims. In other words, this description is an invention corresponding to the specific example described in the embodiment of the invention, and the existence of an invention not described in the claims of this application, that is, in the future, a divisional application will be made. Nor does it deny the existence of an invention added by amendment.

The communication device according to claim 1 is:
In a communication device (for example, the IC card 71 in FIG. 4) that communicates with another device (for example, the reader / writer 1 in FIG. 4),
First clock generation means (for example, RF detector 22 in FIG. 4) that generates a first clock from a signal transmitted from the other device;
Second clock generation means (for example, the oscillator 81 in FIG. 4) for generating a second clock which is an independent clock;
Processing means (for example, the data decoder 25 in FIG. 4) for processing data transmitted from the other device in synchronization with the first clock;
Storage means (for example, the shift register 101 in FIG. 5) in which data processed by the processing means is written in synchronization with the first clock and read out in synchronization with the second clock. Features.

The communication device according to claim 2 is:
Data to be transmitted to the other device is written in synchronization with the second clock and read out in synchronization with the first clock (for example, the shift register 104 in FIG. 5);
In addition to the first clock, it further comprises other processing means (for example, the data modulator 27 in FIG. 4) for processing data read from the other storage means.

The communication device according to claim 3 is:
In a data processing method of a communication device (for example, IC card 71 in FIG. 4) that communicates with another device (for example, reader / writer 1 in FIG. 4),
The communication device
First clock generation means (for example, RF detector 22 in FIG. 4) that generates a first clock from a signal transmitted from the other device;
Second clock generation means (for example, the oscillator 81 in FIG. 4) for generating a second clock which is an independent clock;
Processing means (for example, the data decoder 25 in FIG. 4) for processing data transmitted from the other device in synchronization with the first clock;
Storage means for storing data processed in the processing means (for example, shift register 101 in FIG. 5),
A writing step (for example, step S1 in FIG. 6) in which the data processed in the processing unit is written in the storage unit in synchronization with the first clock;
The data written in the storage means includes a reading step (for example, step S4 in FIG. 6) in which the data is read in synchronization with the second clock.

The communication device according to claim 4 is:
In a communication device (for example, the IC card 71 in FIG. 4) that communicates with another device (for example, the reader / writer 1 in FIG. 4),
First clock generation means (for example, RF detector 22 in FIG. 4) that generates a first clock from a signal transmitted from the other device;
Second clock generation means (for example, the oscillator 81 in FIG. 4) for generating a second clock which is an independent clock;
Data to be transmitted to the other device is written in synchronization with the second clock and read out in synchronization with the first clock (for example, the shift register 104 in FIG. 5);
Processing means (for example, the data modulator 27 in FIG. 4) for processing data read from the storage means in synchronization with the first clock is provided.

The data processing method according to claim 5 is:
In a data processing method of a communication device (for example, IC card 71 in FIG. 4) that communicates with another device (for example, reader / writer 1 in FIG. 4),
First clock generation means (for example, RF detector 22 in FIG. 4) that generates a first clock from a signal transmitted from the other device;
Second clock generation means (for example, the oscillator 81 in FIG. 4) for generating a second clock which is an independent clock;
Storage means for storing data transmitted to the other device (for example, the register 104 in FIG. 5);
Processing means (for example, the data modulator 27 in FIG. 4) for processing data stored in the other storage means in synchronization with the first clock;
A writing step (for example, step S11 in FIG. 7) in which data transmitted to the other device is written in the storage means in synchronization with the second clock;
The data written in the storage means is read out in synchronization with the first clock, and is supplied to the processing means (for example, step S12 in FIG. 7).

  Next, an IC card that operates in synchronization with an independent clock will be described as a preparation for the previous stage of describing the embodiment of the present invention.

  FIG. 3 shows a configuration example of a remote IC card system using an IC card 51 which is an IC card that operates in synchronization with an independent clock. In the figure, portions corresponding to those in FIG. 1 or 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

In FIG. 3, an IC card 51 is provided with an oscillator 61 instead of the RF detector 22, and the host computer 42 of FIG. 2 and a power supply _Vcc are newly provided. The same configuration as the IC card 2 of FIG.

However, in the IC card 51, the data processing unit 26 operates by receiving power from the power source _Vcc . Furthermore, the data processing unit 26 has K interfaces I / F # 1 to I / F # K (K is an integer equal to or greater than 1), and the interface I / F # 1 is one of them. The host computer 42 is connected. Therefore, the data processing unit 26 and the host computer 42 can exchange data by communication via the interface I / F # 1.

In FIG. 3, the power supply V _cc supplies power to necessary blocks such as the oscillator 61 in addition to the data processing unit 26. Further, the oscillator 61 is (independently (regardless of the RF signal)) without using the RF signal transmitted from the reader-writer 1, the frequency generates a clock of f _c, RF detector 22 of FIG. 1 Similarly to the above, the frequency is supplied to the frequency divider 23, the data decoder 25, and the data processing unit 26.

  3, the antenna 21, the frequency divider 23, the demodulator 24, the data decoder 25, the data processing unit 26, the data modulator 27, the modulator 28, and the oscillator 61 are replaced with the IC card unit 41 of FIG. That is, it corresponds to the IC card 2 of FIG. Therefore, the antenna 21, the frequency divider 23, the demodulator 24, the data decoder 25, the data processing unit 26, the data modulator 27, the modulator 28, and the oscillator 61 are referred to as an IC card unit 60.

  In addition, the antenna 21, demodulator 24, data decoder 25, data modulator 27, and modulator 28 in the IC card unit 60 are in contactless communication for performing contactless communication with the reader / writer 1 as described above. Interface. Furthermore, the interface I / F # 1 for communication between the data processing unit 26 in the IC card unit 60 and the host computer 42 is the computer communication interface described above.

  Therefore, the IC card unit 60 has at least a non-contact communication interface and a computer communication interface.

In the IC card unit 60, the oscillator 61 generates a clock having the same frequency f _c and RF signals of the reader-writer 1 (carrier) to the divider 23, the data decoder 25 and the data processing unit 26. Then, the frequency divider 23 divides the clock from the oscillator 61 by 1 / N and supplies it to the data modulator 27.

  Therefore, the IC card unit 60 (the data decoder 25, the data processing unit 26, and the data modulator 27 in FIG. 3) always operates in synchronization with the clock output from the oscillator 61.

  As described above, in the IC card 51, the IC card unit 60 having the non-contact communication interface and the computer communication interface always operates in synchronization with the clock output from the oscillator 61. The difference between the case where communication is started with the IC card unit 60 and the case where communication is first started between the host computer 42 and the IC card unit 60 as described in FIG. Does not occur.

  That is, when communication is first started between the reader / writer 1 and the IC card unit 60, the IC card unit 60 operates in synchronization with the clock output from the oscillator 61 and communicates with the reader / writer 1. , Exchange data.

  After that, when communication is started between the host computer 42 and the IC card unit 60, the IC card unit 60 continues to operate in synchronization with the clock output from the oscillator 61, and communicates with the host computer 42. Exchange data between them.

  On the other hand, even when communication is first started between the host computer 42 and the IC card unit 60, the IC card unit 60 operates in synchronization with the clock output from the oscillator 61. And exchange data.

  After that, when communication is started between the reader / writer 1 and the IC card unit 60, the IC card unit 60 continues to operate in synchronization with the clock output from the oscillator 61 and communicates with the reader / writer 1. Exchange data between them.

However, the IC card 51 of Figure 3, the clock oscillator 61 is generated, and if not the clock of a frequency f _c that is close to the RF signal in the reader-writer 1 (carriers), the reader-writer 1 and the IC card 60 Regardless of the communication between the host computer 42 and the IC card unit 60, the data received by the reader / writer 1 from the IC card unit 60 is synchronized with the clock to which the reader / writer 1 is synchronized. It is not synchronized and the data received by the IC card unit 60 from the reader / writer 1 is not synchronized with the clock (in this case, the clock output by the oscillator 61) with which the IC card unit 60 is synchronized. Can occur.

  As a result, it becomes difficult for the reader / writer 1 and the IC card unit 60 to extract data at the time of BPSK demodulation, and the IC card 51 has a compatibility problem with the conventional IC card 2.

Further, as the oscillator 61 of the IC card 51 (IC card section 60 of), by using a high accuracy to output a clock of the same frequency f _c and a carrier writer 1 (oscillator) outputs oscillator writer It is possible to prevent data exchanged between 1 and the IC card unit 60 from becoming out of synchronization with the clock with which the reader / writer 1 or the IC card unit 60 is synchronized.

  However, a highly accurate oscillator is expensive, and if such an oscillator is used as the oscillator 61, the cost of the IC card 51 is increased.

  FIG. 4 shows a configuration example of an embodiment of a remote IC card system to which the present invention is applied. In the figure, portions corresponding to those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

4, the IC card 71 is the same as the IC card 2 of FIG. 1 except that the host computer 42 of FIG. 2, the power source V _cc , the oscillator 81, and the rate conversion unit 82 of FIG. 3 are newly provided. It is configured.

However, in the IC card 71, the data processing unit 26 operates by receiving power supplied from the power source _Vcc , as in the case of FIG.

  Further, as in the case of FIG. 3, the data processing unit 26 has K interfaces I / F # 1 to I / F # K, and one of them is the interface I / F # 1. A host computer 42 is connected. Therefore, the data processing unit 26 and the host computer 42 can exchange data by communication via the interface I / F # 1.

  The data processor 26 operates in synchronization with the clock output from the oscillator 81, not the RF clock output from the RF detector 22.

4, the oscillator 81, regardless of the RF clock frequency f _c to RF detector 22 generates from the RF signal from the reader-writer 1, independent clock (second clock) (hereinafter, oscillator clock And is supplied to the data processing unit 26. Therefore, in FIG. 4, the data processing unit 26 operates in synchronization with the oscillator clock from the oscillator 81.

Here, the oscillator clock generated by the oscillator 81 is a clock for the data processing unit 26 to exchange data with the host computer 42, and the frequency is, for example, read by the RF detection unit 22. need not be the same as the frequency f _c of the RF clock generated from the RF signal from the writer 1.

That is, the oscillator 81, without considering the frequency f _c of the RF clock, it is possible to select the outputs clock of desired frequency. Therefore, as the oscillator 81, for example, an oscillator using a high-precision but not expensive crystal oscillator or the like, for example, an oscillator using an inexpensive ceramic oscillator or the like with reduced accuracy is employed. it can. In this case, the IC card 71 can be configured at a low cost.

  Data output from the data decoder 25 is supplied to the rate converter 82. The rate converter 82 generates data from the data decoder 25 (data transmitted from the reader / writer 1 in synchronization with a PLL (Phase Lock Loop) clock, which will be described later, generated from the RF clock from the RF detector 22. ) Is temporarily stored, and the stored data is read and supplied to the data processing unit 26.

  The rate conversion unit 82 is supplied with data to be transmitted to the reader / writer 1 from the data processing unit 26 and is obtained by dividing the RF clock from the RF detector 22 from the frequency divider 23. 1 / N clock is supplied. The rate conversion unit 82 temporarily stores the data from the data processing unit 26, reads the stored data in synchronization with the 1 / N clock from the frequency divider 23, and supplies the data to the data modulator 27.

  Here, in FIG. 4, an antenna 21, an RF detector 22, a frequency divider 23, a demodulator 24, a data decoder 25, a data processing unit 26, a data modulator 27, a modulator 28, an oscillator 81, and a rate conversion unit. 82 corresponds to the IC card section 41 of FIG. 2, that is, the IC card 2 of FIG. Therefore, the antenna 21, the RF detector 22, the frequency divider 23, the demodulator 24, the data decoder 25, the data processing unit 26, the data modulator 27, the modulator 28, the oscillator 81, and the rate conversion unit 82 are integrated into an IC card. It will be referred to as part 80.

  In addition, the antenna 21, demodulator 24, data decoder 25, data modulator 27, and modulator 28 in the IC card unit 80 are in contactless communication for performing contactless communication with the reader / writer 1 as described above. Interface. Further, the interface I / F # 1 for the communication between the data processing unit 26 in the IC card unit 80 and the host computer 42 is the computer communication interface described above.

  Therefore, the IC card unit 80 has at least a non-contact communication interface and a computer communication interface.

  In the IC card unit 80, the antenna 21, demodulator 24, data decoder 25, data modulator 27, and modulator 28, which are non-contact communication interfaces, and the RF detector 22 and the frequency divider 23 are shown in FIG. The same processing as in the case of the IC card 2 is performed.

  That is, when the reader / writer 1 writes data to the IC card 2 (when data is transmitted from the reader / writer 1 to the IC card 2), the reader / writer 1 transmits an RF signal corresponding to the data.

  The RF signal from the reader / writer 1 is received by the antenna 21 and supplied to the RF detector 22 and the demodulator 24.

  The RF detector 22 generates an RF clock (first clock) from the RF signal from the antenna 21 and supplies it to the frequency divider 23 and the data decoder 25.

  The demodulator 24 ASK-demodulates the RF signal from the reader / writer 1 received by the antenna 21 and supplies the data obtained as a result to the data decoder 25.

  The data decoder 25 performs processing in synchronization with the RF clock from the RF detector 22, thereby performing BPSK demodulation on the data from the demodulator 24, that is, in synchronization with the RF clock from the RF detector 22, The data from the demodulator 24 is BPSK demodulated and the resulting data is output.

Here, the data rate of the data supplied to the data decoder 25 from the demodulator 24, as described in FIG. 1, f _c is 1 / N of the frequency f _c of the RF signal in the reader-writer 1 (Carrier) / N. Then, the data decoder 25 in synchronization with the RF clock frequency f _c generated from RF signals of the reader-writer 1, BPSK data of a data rate of 1 / N of the frequency f _c f _{c /} N Since demodulation is performed, data extraction (data extraction (sampling) during BPSK demodulation of data) can be performed with high accuracy.

  Data output from the data decoder 25 is supplied to the data processing unit 26 via the rate conversion unit 82.

  The data processing unit 26 performs processing in synchronization with the oscillator clock from the oscillator 81. That is, the data processing unit 26 performs necessary processing on the data supplied via the rate conversion unit 82 in synchronization with the oscillator clock from the oscillator 81 and writes the data in the memory 26A.

  The data processing unit 26 reads the data written in the memory 26 as described above as necessary, and supplies (transmits) the data to the host computer 42 via the interface I / F # 1.

  Next, when the reader / writer 1 reads data from the IC card 2 (when data is transmitted from the IC card 2 to the reader / writer 1), the reader / writer 1 outputs an RF signal (carrier).

  In the IC card 2, the RF signal from the reader / writer 1 is received by the antenna 21 and supplied to the RF detector 22 and the demodulator 24.

  The RF detector 22 generates an RF clock from the RF signal from the antenna 21 and supplies the RF clock to the frequency divider 23 and the data decoder 25.

  The frequency divider 23 divides the RF clock from the RF detection circuit 22 to a frequency of 1 / N, and supplies the 1 / N clock obtained as a result to the data modulator 27 and the rate conversion unit 82.

  On the other hand, the data processing unit 26 performs processing in synchronization with the oscillator clock from the oscillator 81. That is, the data processing unit 26 reads data to be transmitted to the reader / writer 1 from the memory 26 </ b> A in synchronization with the oscillator clock from the oscillator 81, and supplies the data to the data modulator 27 via the rate conversion unit 82.

  The data modulator 27 performs BPSK modulation on the data supplied via the rate conversion unit 82 in synchronization with the 1 / N clock from the frequency divider 23, and supplies the resulting data to the modulator 28. .

Here, since the data modulator 27 modulates data in synchronization with the 1 / N clock as described above, the data rate of the data supplied from the data modulator 27 to the modulator 28 is f _c / N.

  The modulator 28 varies the load of the antenna 21 viewed from the reader / writer 1 side according to the data supplied from the data modulator 27, and thereby the RF signal (carrier) output from the antenna 15 of the reader / writer 1 is changed. Perform load modulation, for example, ASK modulation.

  The reader / writer 1 receives the RF signal (modulated signal) that has been subjected to load modulation by the modulator 28, and as described with reference to FIG. 1, performs ASK demodulation and further BPSK demodulation.

Accordingly, as in FIG. 1, the reader-writer 1, in synchronism with a clock of frequency f _c of the RF signal (carrier), f _{c /} N that is a data rate of 1 / N of the frequency f _c Therefore, data extraction (data extraction at the time of data BPSK demodulation) can be performed with high accuracy.

  As described above, in the IC card unit 80, in particular, the data decoder 25 and the data modulator 27 on the left side of the rate conversion unit 82 always perform processing in synchronization with the RF signal of the reader / writer 1. Data extraction (demodulation) can be performed with high accuracy.

On the other hand, in the IC card unit 80, the data processing unit 26 on the right side of the rate conversion unit 82 performs processing in synchronization with an independent oscillator clock output from the oscillator 81. Further, since the data processing unit 26 is supplied with power from the power source _Vcc , regardless of whether or not power is supplied by the RF signal of the reader / writer 1, that is, the rate of the reader / writer 1 and the IC card unit 80 ( Regardless of whether or not proximity communication is being performed with the converter 82 on the left side), processing can be performed in synchronization with the oscillator clock.

  That is, in FIG. 4, the data processing unit 26 exchanges data with, for example, the host computer 42 regardless of whether or not the reader / writer 1 and the IC card unit 80 perform near field communication. Data can be read from and written to the built-in memory 26A.

  Therefore, in the IC card unit 80, the data decoder 25 and the data modulator 27 always perform processing in synchronization with the RF signal of the reader / writer 1, and the data processing unit 26 and the reader / writer 1 and the IC card unit. Regardless of whether proximity communication is performed with 80, processing is performed in synchronization with the oscillator clock.

  Therefore, even if the reader / writer 1 and the host computer 42 share the function of the data processing unit 26 of the IC card unit 80, that is, for example, the memory 26A built in the data processing unit 26 of the IC card unit 80 is stored. Since data exchanged between the reader / writer 1 and the IC card unit 80 does not synchronize with the clock synchronized with the reader / writer 1 or the IC card unit 80 even if data is shared and exchanged, The reader / writer 1 or the IC card unit 80 can prevent data extraction at the time of BPSK demodulation from being difficult, and can perform data extraction (demodulation) with high accuracy.

  As described above, in the IC card unit 80, the data decoder 25 and the data modulator 27 always perform processing in synchronization with the RF signal of the reader / writer 1, and the data processing unit 26 is connected to the reader / writer 1. Regardless of whether proximity communication is performed with the IC card unit 80, processing is performed in synchronization with the oscillator clock.

  Therefore, data synchronized with the RF signal of the reader / writer 1 is handled on the left side of the rate conversion unit 82, and data synchronized with the oscillator clock output from the oscillator 81 is handled on the right side. Therefore, the rate conversion unit 82 performs mutual conversion (data rate mutual conversion) between data synchronized with the RF signal of the reader / writer 1 and data synchronized with the oscillator clock.

  When the frequency of the RF signal (carrier) of the reader / writer 1 and the frequency of the oscillator clock output from the oscillator 81 coincide by chance (or when they are in an integer multiple relationship). The rate conversion unit 82 may be omitted.

  FIG. 5 shows a configuration example of the rate conversion unit 82 in FIG. 4 that performs mutual conversion (data rate mutual conversion) between data synchronized with the RF signal of the reader / writer 1 and data synchronized with the oscillator clock. Yes.

  In FIG. 5, for convenience of explanation, a configuration example of the data decoding unit 25 of FIG. 4, the data processing unit 26, and the host computer 42 are also illustrated.

  The data decoding unit 25 includes a decoding unit 91 and a clock generator 92.

The decoding unit 91 outputs the demodulator 24 (FIG. 4), the data rate data of _f c / N is supplied. The decoding unit 91 BPSK-demodulates data having a data rate of f _c / N from the demodulator 24 in synchronization with the clock generated by the clock generator 92 and supplies the data to the rate conversion unit 82.

A clock generator 92, from the demodulator 24, along with (signal before BPSK demodulation in the decoding unit 91) is supplied the data in the data rate f _{c /} N, from the RF detector 22, frequency f _c RF clock is supplied. Clock generator 92 has a built-in digital PLL (Phase Lock Loop) circuit not shown, from the demodulator 24, the data of the data rate f _{c /} N, from the RF detector 22, frequency f _c As an input to the PLL circuit, a clock synchronized with the data from the demodulator 24 and the RF clock from the RF detector 22 is generated in the PLL circuit. A clock generated in the PLL circuit of the clock generator 92 (hereinafter, appropriately referred to as a PLL clock) is supplied to the decoding unit 91, and the decoding unit 91 performs BPSK demodulation in synchronization with the PLL clock.

  The PLL clock generated in the PLL circuit of the clock generator 92 is also supplied to the rate conversion unit 82 and other necessary blocks.

  The rate conversion unit 82 includes a shift register 101, a controller 102, an alignment signal generation unit 103, a shift register 104, and an alignment signal generation unit 105.

The shift register 101, together with the PLL clock is supplied from the clock generator 92 of the data decoding unit 25, similarly from the decoding unit 91 of the data decoding unit 25, the data rate data of f _{c /} N is supplied. Shift register 101, for example, in the shift register of 8 bits (1 byte), from the decoding unit 91, the data rate is the data of f _{c /} N, in synchronization with stored PLL clock from the clock generator 92.

  Further, when the shift register 101 stores 1-byte data in synchronization with the PLL clock from the clock generator 92, the shift register 101 supplies a reset signal indicating that to the alignment signal generation unit 103.

  The controller 102 is supplied with a PLL clock from the clock generator 92 of the data decoding unit 25. The controller 102 performs processing such as status control of the shift register 101 and CRC (Cyclic Redundancy Checking) check of data stored in the shift register 101 in synchronization with the PLL clock from the clock generator 92. The processing result is supplied to the host computer 42 or the like via the data processing unit 26 or the data processing unit 26.

  In addition to the reset signal from the shift register 101, the alignment signal generation unit 103 is supplied with a PLL clock from the clock generator 92 of the data decoding unit 25. The alignment signal generator 103 monitors the reset signal from the shift register 101 in synchronization with the PLL clock from the clock generator 92. When the reset signal is supplied from the shift register 101, the alignment signal generator 103 aligns the shift register 101 with the alignment signal. An alignment signal indicating that stored data, that is, 1-byte data is stored is supplied to the host computer 42 or the like via the data processing unit 26 or the data processing unit 26.

  The shift register 104 is supplied with data in units of 1 byte from the data processing unit 26 (memory 26A thereof), and is also supplied with 1 / N clock from the frequency divider 23 (FIG. 4). The shift register 104 is a 1-byte shift register, for example, and stores 1-byte data supplied from the data processing unit 26.

The shift register 104 reads the stored data in synchronization with the 1 / N clock from the frequency divider 23 (FIG. 4) and supplies the data to the data modulator 27. Thus, the data modulator 27 from the shift register 104, the data rate data of f _{c /} N is supplied.

  Furthermore, when the shift register 104 reads 1-byte data in synchronization with the 1 / N clock from the frequency divider 23, the shift register 104 supplies a reset signal indicating that to the alignment signal generation unit 105.

  In addition to the reset signal from the shift register 104, the alignment signal generator 105 is supplied with a 1 / N clock from the frequency divider 23. The alignment signal generation unit 105 monitors the reset signal from the shift register 104 in synchronization with the 1 / N clock from the frequency divider 23, and when the reset signal is supplied from the shift register 104, the alignment signal is generated from the shift register 104. An alignment signal indicating that the data that has been removed, that is, 1-byte data has been read, is supplied to the host computer 42 or the like via the data processing unit 26 or the data processing unit 26.

  Next, the operation of the rate conversion unit 82 in FIG. 5 when data transmitted from the reader / writer 1 (FIG. 4) is written in the memory 26A will be described with reference to the flowchart in FIG.

  The data transmitted from the reader / writer 1 is processed by the decoding unit 91 and supplied to the shift register 101 of the rate conversion unit 82.

  In the shift register 101, the data from the decoding unit 91 is written in synchronization with the PLL clock from the clock generator 92 in step S1. When 1 byte of data is written in the shift register 101, the process proceeds from step S <b> 1 to S <b> 2, and the shift register 101 supplies a reset signal to the alignment signal generation unit 103.

  When the reset signal is supplied from the shift register 101, the alignment signal generation unit 103 supplies the alignment signal to the data processing unit 26 in step S3.

  When the alignment signal is supplied from the alignment signal generation unit 103, the data processing unit 26 reads 1-byte data stored therein from the shift register 101, and transfers and writes it to the memory 26A in step S4.

  That is, the data processing unit 26 reads 1-byte data from the shift register 101 in synchronization with the oscillator clock from the oscillator 81 (FIG. 4), and transfers the data to the memory 26A for storage.

  Thereafter, the processes of steps S1 to S4 are repeated.

  As described above, the data transmitted from the reader / writer 1 (FIG. 4) and output from the decoding unit 91 is written in the register 101 in synchronization with the PLL clock generated from the RF clock, and the oscillator generated by the oscillator 81 It is read from the register 101 in synchronization with the clock and stored in the memory 26A.

  On the other hand, the data processing unit 26 that operates in synchronization with the oscillator clock can perform asynchronous communication with the host computer 42, and the data stored in the memory 26 </ b> A is transferred to the host computer 42 by the communication. Can be sent.

  Accordingly, the data transmitted from the reader / writer 1 (FIG. 4) can be written into the memory 26A, and the data written into the memory 26A can be read out and transmitted (supplied) to the host computer 42.

  Next, the operation of the rate conversion unit 82 in FIG. 5 when the data stored in the memory 26A is read and transmitted to the reader / writer 1 (FIG. 4) will be described with reference to the flowchart in FIG. .

  In step S11, the data processing unit 26 reads 1-byte data to be transmitted to the reader / writer 1 from the memory 26A in synchronization with the oscillator clock from the oscillator 81 (FIG. 4), and stores it in the shift register 104. Transferred and written. That is, 1-byte data read from the memory 26A is written to the shift register 104 in synchronization with the oscillator clock.

In the shift register 104, in step S12, the 1-byte data written therein is read out in synchronization with the 1 / N clock generated from the RF clock in the frequency divider 23 (FIG. 4). obtained by reading the data rate is 1 byte data of f _{c /} N is supplied to the data modulator 27. This data is processed by the data modulator 27 and then transmitted to the reader / writer 1 (FIG. 4) as described above.

  When 1-byte data is read in the shift register 104, the process proceeds from step S 12 to S 13, and the shift register 104 supplies a reset signal to the alignment signal generation unit 105.

  When the reset signal is supplied from the shift register 104, the alignment signal generation unit 105 supplies the alignment signal to the data processing unit 26 in step S14.

  When the alignment signal is supplied from the alignment signal generation unit 105, the data processing unit 26 returns to step S11 and is next transmitted to the reader / writer 1 in synchronization with the oscillator clock from the oscillator 81 (FIG. 4). The byte data is read from the memory 26A.

  Then, the data read from the memory 26A is transferred and written to the shift register 104, and the same processing is repeated thereafter.

  As described above, the data to be transmitted to the reader / writer 1 (FIG. 4) is transferred from the RAM 26A to the register 104 and written in synchronization with the oscillator clock generated by the oscillator 81, and 1 / N generated from the RF clock. In synchronization with the clock, it is read from the register 104 and transmitted to the reader / writer 1.

  On the other hand, the data processing unit 26 that operates in synchronization with the oscillator clock can communicate asynchronously with the host computer 42, receive data from the host computer 42 through the communication, and write it into the memory 26A. be able to.

  Therefore, the data transmitted from the host computer 42 can be written into the memory 26A, and the data written into the memory 26A can be read out and transmitted to the reader / writer 1.

  As described above, in the IC card 71 (FIG. 4), an RF clock is generated from the RF signal transmitted from the reader / writer 1, and an independent oscillator clock for operating the data processing unit 26 is generated. The data transmitted from the reader / writer 1 is BPSK demodulated in synchronization with the RF clock, and the data obtained as a result of the BPSK demodulation is shifted in synchronization with the RF clock (PLL clock generated from the RF clock). The data is written into the register 101 and further read out from the shift register 101 in synchronization with the oscillator clock.

  The data transmitted to the reader / writer 1 is written to the shift register 104 in synchronization with the oscillator clock, and further read from the shift register 104 in synchronization with the RF clock (1 / N clock generated from the clock). And is BPSK modulated and transmitted to the reader / writer 1.

  Therefore, the IC card 71 performs BPSK demodulation in synchronization with the RF clock generated from the RF signal from the reader / writer 1 and synchronizes with the 1 / N clock obtained by dividing the RF clock. Since BPSK modulation can be performed, the reader / writer 1 and the IC card 71 can accurately extract data (data extraction (sampling) during BPSK demodulation of data). Furthermore, as the oscillator 81 that generates an oscillator clock that is not related to communication with the reader / writer 1, for example, a ceramic oscillator or the like is reduced in accuracy, but an inexpensive one can be used.

  As a result, in the IC card unit 80 having a non-contact communication interface for performing non-contact communication with the reader / writer 1 and a computer communication interface for performing communication with the host computer 42, the reader / writer 1 and the host computer 42 In any case, the IC card 71 that performs normal data communication can be provided at low cost.

  The present invention has been described with respect to the case where the present invention is applied to an IC card. is there. Furthermore, the present invention can be applied to any device that generates a clock from a signal transmitted from another device by wire or wirelessly and processes a signal transmitted from another device in synchronization with the clock. It is.

  In the present embodiment, the host computer 42 is connected to only one interface I / F # 1 among the N interfaces I / F # 1 to I / F # N included in the data processing unit 26. However, the host computer 42 and the like can be connected to any one or more of the interfaces I / F # 1 to I / F # N.

It is a block diagram which shows the structure of an example of the conventional remote IC card system. It is a block diagram which shows the structural example of the remote IC card system using the IC card 31 provided with the function of IC card 2, and the function of the computer which performs various applications. It is a block diagram which shows the structural example of the remote IC card system using the IC card 51 which is an IC card which operate | moves synchronizing with an independent clock. It is a block diagram which shows the structural example of one Embodiment of the remote IC card system to which this invention is applied. 3 is a block diagram illustrating a configuration example of a rate conversion unit 82. FIG. 5 is a flowchart for explaining the operation of a rate conversion unit 82. 5 is a flowchart for explaining the operation of a rate conversion unit 82.

Explanation of symbols

  1 Reader / Writer, 21 Antenna, 22 RF Detector, 23 Frequency Divider, 24 Demodulator, 25 Data Decoder, 26 Data Processor, 26A Memory, 27 Data Modulator, 28 Modulator, 42 Host Computer, 71 IC Card , 80 IC card section, 81 oscillator, 82 rate conversion section, 91 decoding section, 92 clock generator, 101 shift register, 102 controller, 103 alignment signal generation section, 104 shift register, 105 alignment signal generation section

Claims (5)

In a communication device that communicates with other devices,
First clock generating means for generating a first clock from a signal transmitted from the other device;
Second clock generating means for generating a second clock which is an independent clock;
Processing means for processing data transmitted from the other device in synchronization with the first clock;
A communication device comprising: storage means in which data processed by the processing means is written in synchronization with the first clock and read out in synchronization with the second clock. Other storage means in which data to be transmitted to the other device is written in synchronization with the second clock and read out in synchronization with the first clock;
The communication apparatus according to claim 1, further comprising: another processing unit that processes data read from the other storage unit in synchronization with the first clock. In a data processing method of a communication device that communicates with another device,
The communication device
First clock generating means for generating a first clock from a signal transmitted from the other device;
Second clock generating means for generating a second clock which is an independent clock;
Processing means for processing data transmitted from the other device in synchronization with the first clock;
Storage means for storing data processed in the processing means,
A writing step in which data processed by the processing means is written to the storage means in synchronization with the first clock;
A data processing method comprising: a step of reading data written in the storage means in synchronization with the second clock. In a communication device that communicates with other devices,
First clock generating means for generating a first clock from a signal transmitted from the other device;
Second clock generating means for generating a second clock which is an independent clock;
Storage means for writing data to be transmitted to the other device in synchronization with the second clock and reading out in synchronization with the first clock;
A communication device comprising: processing means for processing data read from the storage means in synchronization with the first clock. In a data processing method of a communication device that communicates with another device,
First clock generating means for generating a first clock from a signal transmitted from the other device;
Second clock generating means for generating a second clock which is an independent clock;
Storage means for storing data transmitted to the other device;
Processing means for processing data stored in the other storage means in synchronization with the first clock;
A writing step in which data to be transmitted to the other device is written in the storage means in synchronization with the second clock;
A data processing method comprising: a step of reading data written in the storage means in synchronization with the first clock and supplying the data to the processing means.

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