JP2002251179A - Device and method for video signal conversion - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert an inputted 1st video signal into a 2nd video signal having been rotated vertically and horizontally by 180 deg. in real time while not having the input speed changed. SOLUTION: A double-speed clock generation block 20 generates a double- speed clock 2xCLK which has a frequency twice as high as that of the reference clock of the 1st video signal. An address counter 18 specifies an address of an SRAM 24. A write control block 16 controls the writing of pixel data constituting the image data of the 1st video signal to a storage means by controlling the SRAM 24 into a writable state and a readable state alternately with each clock of the double-speed clock. After the pixel data of an (n)th (n: arbitrary integer) field of the 1st video signal are all written to the SRAM 24, pixel data are read out in order from the final pixel data to the starting pixel data of the (n)th field to generate image data of the 2nd video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and a method for converting a video signal, and more particularly to an apparatus for converting an input video signal into 18 vertical, horizontal, and vertical directions.
The present invention relates to a video signal conversion device and method for converting a video signal into a video signal rotated by 0 degrees.

[0002]

2. Description of the Related Art As a device for displaying an image, a cathode ray tube, a liquid crystal display, a P
DP (plasma display panel) and the like are currently in practical use, and all of them receive an image signal and display an image of, for example, 30 fields per second, thereby displaying an image.

A typical video signal supplied to a display device is a television signal, and there are a plurality of standards, such as an SDTV standard such as NTSC and PAL, and an HDTV standard having a higher resolution. Also in the SDTV standard, an analog standard such as NTSC and a digital standard such as D2 which is a digital version of NTSC coexist.

A liquid crystal display device is often mounted on, for example, a video camera or the like in such a manner that the screen itself can be rotated, taking advantage of its thin and lightweight characteristics. According to this, when the screen is rotated to reverse the front and back, the display screen is in a state where the top, bottom, left and right are rotated by 180 degrees with respect to the video camera body.

When a liquid crystal display device is used as a display device of an arbitrary electronic device, it may be necessary to mount the liquid crystal display device in a state in which the liquid crystal display device is rotated 180 degrees up and down and left and right as compared with a normal display state. More specifically, recent liquid crystal display devices often include a display control circuit, which causes a problem in a physical shape when the liquid crystal display device is used as a display device of an electronic device. .

Referring to FIG. 5, the case 100 of the liquid crystal display device has a liquid crystal display section 102 and a display control circuit 104. The display unit 102 may not be disposed at a position symmetrical with respect to the device housing 100. In such a liquid crystal display device, as shown in FIG.
Even if an attempt is made to arrange the display screen 112 at the left end of the front, the display control circuit 104 cannot be arranged as desired because the left margin 106 is large.

Recently, a technique for forming a display control circuit on a glass substrate of a liquid crystal display device has been developed and further miniaturization has been achieved, but such a technique is still expensive. Therefore, in order to realize the arrangement of the display screen 112 shown in FIG. 6 using a relatively inexpensive liquid crystal display device as shown in FIG.
A method of rotating the lens by 0 degrees for use is conceivable. However, according to this, if a video signal is supplied by a normal method, the image is displayed in a state of being rotated 180 degrees up, down, left, and right.

Accordingly, the present invention corresponds to a case where an image is to be displayed in a state of being rotated by 180 degrees as compared with a normal case for the above-described reason. It is an object of the present invention to provide a video signal conversion device and method for performing a conversion process.

[0009]

A video signal converter according to the present invention receives a first video signal input in synchronization with a reference clock, and converts a video displayed on a screen with the first video signal. Second to display video rotated 180 degrees vertically and horizontally
A video signal is generated by converting the first video signal. In particular, it is characterized by the procedure of writing and reading image data to and from high-speed storage means such as SRAM. The double-speed clock generating means generates the reference clock of the first video signal by two times.
A double speed clock having a double frequency is generated. An address designating means such as an address counter designates an address of the storage means. The writing control unit controls the writing of the pixel data constituting the image data of the first video signal to the storage unit by controlling the storage unit to be in a writable state and a readable state alternately with each clock of the double speed clock. I do. When the writing of all the pixel data of the n-th field (n is an arbitrary integer) or the frame of the first video signal to the storage means is completed, the first pixel from the last pixel data of the n-th field or the frame is obtained. Image data of the second video signal is generated by sequentially reading data up to the data.

Further, the address of the storage means from which the pixel data of the n-th field or frame is read out in synchronization with an arbitrary clock of the double-speed clock, and the (n + 1) th clock in synchronization with the clock following the above-mentioned arbitrary clock If the pixel data of the number field or the frame is written, the device according to the present invention can be realized with a small memory capacity. This is because of the two consecutive clocks used by the addressing means to synchronize the reading and writing of the double speed clock,
You can think of it as specifying the same address.

From another viewpoint, according to the present invention, when the first video signal is input in synchronization with the reference clock, the image displayed on the screen by the first video signal is 180 degrees up, down, left, and right. The second video signal for displaying the rotated video is
This is a video signal conversion method generated by converting the first video signal. In the first step, a double-speed clock having a frequency twice as high as the reference clock of the first video signal is generated. In the second step, the storage means is alternately controlled to be in a writable state and a readable state with each clock of the double-speed clock, In the third step, all the pixel data of the n-th field (n is an arbitrary integer) or the frame constituting the image data of the first video signal is written into the storage means. And
As a fourth step, when the third step is completed, the nth
The image data of the second video signal is generated by sequentially reading out from the last pixel data to the first pixel data of the number field or the frame.

In the fourth step, the clock coming next to the arbitrary clock is added to the address of the storage means from which the pixel data of the n-th field or frame is read out in synchronization with the arbitrary clock of the double speed clock. , The pixel data of the (n + 1) th field or frame may be written. According to this, there is an advantage that the storage capacity of the storage means can be reduced as compared with the case where data is written to another address of the storage means.

[0013]

FIG. 1 is a functional block diagram in which each function of a video signal converter according to the present invention is divided into blocks. Here, an HDTV signal which is a digital signal is assumed as the input first video signal. However, the input video signal need not be a television signal as long as it is a digital video signal, and the type is not limited. Further, even if the input video signal is an analog signal, the present invention can be applied by performing analog-to-digital conversion.

The first video signal input to the input amplifying circuit 10 is converted into image data D by the HDTV signal processing circuit 12.
ATA, reference clock PCLK, and vertical and horizontal synchronization signals (V, H synchronization).
(grammable Gate Array) 14. At this time, the image data DATA is composed of pixel data as described below. The FPGA 14 has hundreds of thousands or more gates, and a plurality of functions can be realized by one device by arbitrarily rewriting the logical configuration. Here, the functions executed by the FPGA 14 are indicated by blocks indicated by broken lines. Then, the FPGA 14 operates as a state machine whose state changes according to an input signal.
For this reason, the designer previously writes a logical configuration for implementing the functions described below in the FPGA 14 using a dedicated development tool. The microprocessor (CP
U), the DRAM 14, the ROM, and the HDD may be used by incorporating the FPGA 14 into a part of a system configured by connecting them via a bus. In this case, the operation described below may be executed by the CPU reading a program stored in the HDD or the ROM and supplying an instruction to the FPGA 14.

Next, each functional block realized by a logic circuit formed in the FPGA 14 will be described. The write control block 16 generates a write control signal WE (write enable signal) and supplies it to the SRAM 24 to control whether or not pixel data constituting the image data DATA can be written to the SRAM. Address counter block 1
8 designates the address of the storage cell in the SRAM 24. The address counter 18 changes the designated address with reference to a vertical (V) synchronization signal as described later. The double-speed clock generation block 20 generates a double-speed clock 2xCLK having a frequency twice that of the reference clock PCLK of the first video signal. The data input / output block 22 receives the pixel data of the first video signal according to the reference clock PCLK, and supplies the pixel data to the SRAM 24. When not write enable (write enabled),
The address counter 18 receives pixel data from a designated address (more precisely, a storage cell having the designated address), and outputs it in accordance with a reference clock. In addition,
The reference clock PCLK and the horizontal and vertical (V, H) synchronization signals received by the FPGA 14 are actually output after being delayed in the FPGA 14 in order to synchronize with other signals.

FIG. 2 is a chart showing the timing relationship between the double speed clock 2xCLK and the write control signal WE. As shown in the figure, the SRAM 24 stores the write control signal W
By E, it is controlled to be in a writable state by every other double speed clock 2 × CLK. In other words, SR
The AM 24 is alternately controlled to a writable state and a readable state by each clock of the double speed clock 2 × CLK.

By the way, in order to rotate the display image 180 degrees vertically and horizontally, as shown in FIG. 3, it is necessary to interchange the positions of the pixels in one frame vertically and horizontally. Although FIG. 3 shows an example of 8 × 6 pixel data for simplicity, the same applies to a case where one frame is composed of a larger number of pixels. Therefore, in the present invention, the position of the pixel data is switched by controlling the writing and reading of the pixel data to and from the SRAM 24. In the case where the video signal adopts the interlaced system and two fields constitute one frame, the same applies in that the positions of the pixels in one field are interchanged vertically and horizontally and symmetrically. Only examples will be described.

FIG. 4 is a diagram showing the flow of writing and reading of pixel data to and from the SRAM 24. 4A to 4
It is drawn in the order of F. At this time, for example, F1: L
1 is used to mean the first line having the video signal (pixel data) of the first frame. However, this is used for simplicity. In an actual television signal standard, the first line has only a synchronizing signal, and therefore has a different meaning from the first line L1 in the present application.

Also, since there is no video signal (pixel data) in the vertical blanking period of the video signal and the horizontal blanking period of each line, it should not be subjected to the conversion processing according to the present invention. Therefore, the write control block 16
By using the vertical and horizontal (V, H) synchronization signals separated from the first video signal in the V signal processing circuit 12, the vertical and horizontal blanking periods are distinguished from other portions to perform conversion processing. Specifically, for example, counters (V counter and H counter) for vertical and horizontal may be provided (these can also be realized by adding them to the logic configuration of the FPGA 14). The number of display pixels in one frame is determined as 640 × 480 pixels (in the case of VGA) depending on the display device. Therefore, if the reference clock is counted by these counters for the period in which pixel data exists,
As a result, it is the same as counting the number of pixels. Therefore, for each line, the count value is set such that a portion from the start of the pixel data of each line to the end of counting a predetermined number (one line, 640 pixels, etc.) based on the horizontal synchronization signal is regarded as a portion of the pixel data. Can be distinguished from a certain part of the pixel data and the other part.

At each address of the SRAM 24, no data is initially stored, or even if it is stored, it is ignored. That is, writing and reading can be alternately performed in synchronization with each clock of the double speed clock 2 × CLK, but all the pixel data of the first frame is stored in the SRAM.
Until the data is written to 24, even if data can be read by a read operation, it is ignored.

The operation of the address counter 18 will now be described. An address counter 18 is an SRAM for storing pixel data of an n-th frame (n is an arbitrary integer; in FIG. 4A, a first frame F1).
The addresses of 24 storage cells are designated. Then, in accordance with the control of the write control signal WE, the pixel data of the first video signal is sequentially stored in synchronization with the double speed clock 2xCLK (FIGS. 4A and 4B). When all the pixel data of the first frame F1 is stored in the SRAM 24 (FIG. 4C), the range from the last pixel data (F1-48) to the first pixel data (F1-01) of the first frame F1 is changed. They are read out in order (FIGS. 4D to 4F). Whether the writing of all the pixel data of the first frame is completed is determined by the vertical synchronization (V).
It is determined by referring to the signal. At this time, in more detail, only the pixel data portion is processed by referring to the count values of the above-described V and H counters, and during the horizontal and vertical retrace periods, the processing according to the present invention is temporarily suspended ( (Indling). As a result, the image data R-DATA in which the arrangement order of the pixel data of the first frame is exactly opposite to that of the original video signal is generated. As described above, when the video signal in which the order of the pixel data is reversed from that of the original video signal (the portion other than the pixel data remains unchanged) is displayed on the display screen, the top, bottom, left, and right are displayed as shown in FIG. It will be displayed as an image rotated 180 degrees.

When the writing of all the pixel data of the first frame is completed, the pixel data of the second frame is supplied in synchronization with the reference clock. FIG. 4D shows that the last pixel data (F1-48) on the sixth line (L6) of the first frame is read, and the read address is stored in the first line (2) of the second frame at the next clock. L1), the first pixel data (F2-0)
1) shows a state in which data has been written. In FIG. 4D and thereafter, the boundaries between the pixel data of the first frame and the second frame are indicated by thick lines for emphasis.

In the second and subsequent frames, the order of pixel data can be reversed by writing and reading pixel data to and from the SRAM 24 as in the first frame. At this time, the pixel data of the second frame may be written and read at an address other than the address of the SRAM 24 at which the pixel data of the first frame is written (more precisely, the storage cell at the specified address).
However, by performing writing and reading as shown in FIG. 4, the capacity of the SRAM 24 can be further reduced.

That is, when the writing of all the pixel data of the first frame is completed, and subsequently the reading of the pixel data of the first frame is started, the address at which the pixel data of the first frame that has been read is stored is stored. It is preferable to sequentially write the pixel data of the second frame into the storage cells. The example of FIG. 4 is an example which can be realized with the smallest capacity. After reading out the last pixel data (F1-48) of the first field in synchronization with the double-speed clock, the same address is used for the next clock. The first pixel data (F2-01) of the second frame is written. In other words,
Address counter 18 uses two consecutive clocks of double speed clock 2 × CLK (used for synchronization of read and write)
, The same address is specified. At this time, since the double-speed clock for synchronizing these two operations has twice the frequency of the reference clock, subsequent pixel data supplied in synchronization with the reference clock can be processed without delay.

In the embodiment shown in FIG. 4, the address specified by the address counter 18 is S
With the switching of the frame including the pixel data stored in the RAM, 01 → 48 → 01 → 48 →.
Is repeated. Address counter 18
Is used to switch back such address values.
The vertical (V) synchronization signal output from the DTV signal processing circuit is used.

As described above, according to the present invention, an input first video signal is converted into image data of a second video signal for displaying a video rotated 180 degrees vertically and horizontally in real time at the input speed. Can output.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a video signal conversion device according to the present invention.

FIG. 2 is a timing chart of a double speed clock 2xCLK and a write control signal WE in the present invention.

FIG. 3 is a diagram showing a positional relationship between a pixel of one frame before conversion and a pixel of one frame after conversion for rotating the pixel by 180 degrees vertically, horizontally, and horizontally;

FIG. 4 is a chart showing the flow of writing and reading of pixel data to and from an SRAM according to the present invention.

FIG. 5 is a diagram illustrating an example of a liquid crystal display device (device).

FIG. 6 is a diagram showing a layout example of an electronic device using a liquid crystal display device for a display screen.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 input amplifier circuit 12 HDTV signal processing circuit 14 FPGA 16 write control block 18 address counter 20 double speed clock generation block 22 data input / output block 24 SRAM 100 housing of liquid crystal display device 102 display portion of liquid crystal display device 104 of liquid crystal display device Display control circuit 106 Left margin of liquid crystal display device 108 Right margin of liquid crystal display device 110 Electronic device 112 Display screen of electronic device PCLK Reference clock WE Write control signal 2xCLEK Double speed clock F1-01 First pixel data of first frame F1-48 Last pixel data of the first frame

Claims (4)

[Claims] 1. A first signal input in synchronization with a reference clock.
Upon receiving the video signal, the first video signal is converted into image data of a second video signal that displays a video image whose top, bottom, left and right are rotated by 180 degrees with respect to the video displayed on the screen by the first video signal. A video signal conversion device that generates a double-speed clock having a frequency twice as high as the reference clock; a double-speed clock generating unit that generates a double-speed clock; and an address specifying unit that specifies an address of the storage unit. By controlling the storage means alternately in a writable state and a readable state with each clock of the double-speed clock, writing of pixel data constituting the image data of the first video signal to the storage means is controlled. Writing control means, the memory means for storing all pixel data of an n-th field (n is an arbitrary integer) of the first video signal or a frame. When the writing to the n-th field or the frame is completed, the image data of the second video signal is generated by sequentially reading out from the last pixel data to the first pixel data of the n-th field or the frame. Signal converter. 2. The method according to claim 1, further comprising: synchronizing with an address of said storage means from which pixel data of said n-th field or frame is read out in synchronization with an arbitrary clock of said double speed clock, and synchronizing with a clock coming after said arbitrary clock 2. The video signal conversion device according to claim 1, wherein pixel data of the (n + 1) th field or frame is written by writing. 3. When a first video signal is input in synchronization with a reference clock, a video is displayed by rotating the video up and down and left and right by 180 degrees with respect to a video displayed on a screen by the first video signal. A video signal conversion method for generating image data of two video signals by converting the first video signal, wherein a first step of generating a double-speed clock having a frequency twice as high as the reference clock; A second step of controlling the means to alternately enter a writable state and a readable state with each of the double-speed clocks, and an n-th (n) constituting the image data of the first video signal
Is an arbitrary integer) The third step of writing all the pixel data of the field or frame to the storage means, and when the third step is completed, from the last pixel data to the first pixel data of the nth field or frame In order to generate the image data of the second video signal. 4. In the fourth step, an address of the storage means from which the pixel data of the n-th field or frame is read out in synchronization with an arbitrary clock of the double-speed clock, 4. The video signal conversion method according to claim 3, wherein the pixel data of the (n + 1) th field or frame is written in synchronization with the next clock.