JP2002353570A - Iii nitride-based compound semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of nonuniformity occurring in the thickness or composition ratio of element in a Pd-Ga compound layer and increases the contact resistance of an electrode, having an Au/Pd/Pd-Ga compound structure and used as the p-type electrode of a III nitride-based compound semiconductor element, when an electrode thermal treating step is performed in the course of forming the electrode, and in addition, the nonuniformity produces recessed and projecting sections on the surface of the electrode, causing peeling off, etc., and lowering the production yield of a III nitride-based compound semiconductor device, because no sufficient adhesive strength is obtained at mounting of the semiconductor element on a stem or wiring bonding is made to an electrode portion. SOLUTION: An Mo layer is interposed between Au and Pd, constituting the p-type electrode. The Mo layer has the effect of uniformly forming a Pd-Ga compound to be formed between a III nitride-based compound semiconductor layer which constitutes a base and a Pd layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compound semiconductor electrode structure.

[0002]

BACKGROUND ART In _x Ga _y Al _z N (provided that x + y + z
= 1, 0 ≦ x, y, z ≦ 1) Group III nitride-based semiconductors have a large energy band gap and high thermal stability, and are used in various applications including short-wavelength light-emitting devices and high-temperature devices. Is a promising material system. In particular, as a light emitting element, a light emitting diode (Light Emitting) having an optical output of several cds in a blue to green wavelength range is used.
Diode (LED) has already been put to practical use, and a laser diode (Laser Diode) using the same material system is used.
e; LD) is about to be put to practical use.

When these group III nitride-based semiconductor devices are used by mounting them on actual various devices, it is necessary to sufficiently reduce the power consumed by the devices themselves and the operating voltage. An Au / Pd / Pd-Ga compound electrode has been proposed as a low-resistance p-type electrode suitable for such a group III nitride semiconductor device. (JP-A-10-303504).

By using this Au / Pd / Pd-Ga compound electrode, the contact resistance generated between the p-type electrode and the semiconductor contact layer can be suppressed to a level of 1 × 10 ⁻⁴ Ωcm ² , which has conventionally been improved. Au / used
It can be suppressed lower than the Ni electrode. Therefore Ga
Since the operating voltage of the N-based semiconductor element can be reduced, it is possible to achieve a reduction in element operating power and a reduction in heat generation, and it is possible to further improve the life and characteristics of the element.

[0005]

However, in the case of a semiconductor device using the above Au / Pd / Pd-Ga compound electrode as a p-type electrode, the device has to be operated for a long time due to variations in operating voltage for each wafer lot or large current injection. There is a problem that the operating voltage rises when driving and the element is degraded.In addition, when mounting the element on a stem or the like and when crimping the power supply line to the electrode, the adhesion often decreases, and the production yield is reduced. There was a problem of falling.

Examination of the cause of such a problem reveals that the Au / Pd / Pd-Ga compound electrode has a great effect on reducing the device operating voltage and at the same time includes the cause of the above problem. It has become.

In forming an Au / Pd / Pd-Ga compound electrode, for example, for a GaN contact layer, a Pd-Ga compound layer is formed by heat treatment after forming an Au / Pd / GaN contact layer structure. Au /
A method of completing a Pd / Pd-Ga compound electrode structure,
Alternatively, there is a method in which a Pd-Ga compound layer, a Pd layer, and an Au layer are sequentially formed directly on the GaN contact layer by an appropriate film forming method to complete an Au / Pd / Pd-Ga compound electrode structure.

In the case where an Au / Pd / Pd-Ga compound electrode is formed by the former method, even if a good electrode is formed at the stage of forming the electrode, if a current is injected when a semiconductor element is used, Pd may be reduced. The reaction proceeds between the -Ga compound layer and the GaN contact layer or between the Pd layer and the Pd-Ga compound layer, and as a result, the Pd-Ga compound layer becomes non-uniform.

On the other hand, Au / Pd / Pd-G
The problem becomes more pronounced when an a-compound electrode is formed. The heat treatment step is often performed at a temperature of 500 to 900 ° C. in a vacuum or an inert gas atmosphere. One of the problems of the Au / Pd / Pd-Ga compound electrode structure is that, in this heat treatment step, the surface state of the GaN contact layer, such as the presence of an oxide film, causes Pd
This means that the interface reaction between the layer and the GaN layer may cause non-uniformity in the wafer plane.

[0010] Such non-uniformity is caused by variations in the thickness of the Pd-Ga compound layer and element composition ratio, or in the Pd-Ga compound layer and the Gd.
This leads to variation in the contact condition of the aN layer. As a result, a characteristic distribution occurs in which the contact resistance of the electrode, which should be uniform in the electrode plane, becomes extremely large in part, and the contact resistance increases when viewed as the entire electrode, and the operating voltage of the element increases. This has led to adverse effects such as a rise.

As another problem of the Au / Pd / Pd-Ga compound electrode structure, it has been confirmed that in the above-mentioned heat treatment step, irregularities are generated on the electrode surface. Due to the non-uniformity of the interface reaction between the Pd layer and the GaN layer that occurs during the heat treatment step described above, unevenness occurs at this interface or the thickness of the formed Pd-Ga compound layer varies. Due to the irregularities, irregularities are formed on the electrode surface even after the Au layer is laminated on the Pd layer. Usually, as a method of supplying power to the electrodes of the semiconductor element, there are often used methods such as wire bonding in which an Al wire or an Au wire is pressure-bonded to the electrode surface, and a stem mount in which the electrode surface is directly welded to the stem surface. If there are irregularities in the surface, it will lead to the problem that the ease of bonding (bondability) will decrease,
Ultimately, it was found that this had the adverse effect of lowering the product yield.

Among the problems caused by the non-uniformity of the Pd-Ga interface caused by the electrode heat treatment process, the simplest method for avoiding a decrease in bondability is an Au layer or a Pd layer. Is formed sufficiently thick to the order of μm to minimize the influence of unevenness. However, if the thickness of each layer is simply increased, the metal film is easily peeled off, and the mechanical strength of the electrode is reduced. Further, Au and Pd are expensive, and it is not preferable to use them in a large amount for the electrode portion, which may increase the chip cost of the semiconductor element. As for the deterioration of the characteristics of the p-type electrode, no effective and simple solution has been found so far.

[0013]

A group III nitride compound semiconductor device according to the present invention comprises a group III nitride semiconductor layer containing a p-type impurity and a p-type electrode in contact with the group III nitride semiconductor layer. In the group III nitride compound semiconductor device, the p-type electrode is formed of a first metal and a compound of gallium in order from a portion in contact with the group III nitride semiconductor layer.
A second layer made of a first metal, a third layer made of a second metal, and a fourth layer made of a third metal.

In the group III nitride compound semiconductor device according to the present invention, the first metal is Pd, Pt, Ni, Ir, O
It is characterized by including at least one of s, Rh, and Ru.

In the group III nitride compound semiconductor device of the present invention, the thickness of the second layer is 3 nm or more.

The third layer of the group III nitride compound semiconductor device according to the present invention is characterized in that the third layer contains at least one of Mo, W, Ir, Rh and Ru.

The third layer of the group III nitride compound semiconductor device according to the present invention is characterized in that the thickness of the third layer is 3 nm or more and 50 nm or less.

The method of manufacturing a group III nitride compound semiconductor device according to the present invention is a method of manufacturing a group III nitride compound semiconductor device including a p-type impurity and a group III nitride compound semiconductor device including a p-type electrode. A second layer made of a first metal on the group III nitride semiconductor layer containing the p-type impurity;
Forming a third layer of a third metal and a fourth layer of a third metal in sequence, and then performing a heat treatment at 500 ° C. to 900 ° C. to form a third layer between the group III nitride-based semiconductor and the second layer. Forming a first layer made of a compound of one metal and gallium.

The method for manufacturing a group III nitride compound semiconductor device according to the present invention is a method for manufacturing a group III nitride compound semiconductor device including a p-type impurity and a group III nitride compound semiconductor device including a p-type electrode. A first layer made of a compound of a first metal and gallium, a second layer made of a first metal, a third layer made of a second metal, on the group III nitride-based semiconductor layer containing the p-type impurity, A fourth layer made of a third metal is sequentially formed.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 are schematic sectional views of an electrode structure embodying the present invention. The electrode structure of this example was manufactured by the following method.

First, metal organic chemical vapor deposition (MOCVD)
A p-type GaN layer 102 was epitaxially grown as a group III nitride semiconductor layer on a sapphire substrate 101 by a method to form a semiconductor contact layer serving as a base of the electrode structure. The p-type GaN layer 102 is doped with Mg at a concentration of 10 ²⁰ cm ⁻³ so as to have a carrier concentration of 5 × 10 ¹⁷ cm ⁻³ . Further, after ultrasonically cleaning the surface of the p-type GaN layer 102 with acetone, ultrasonic cleaning was performed in ethanol or methanol to remove organic impurities attached to the surface of the epitaxial layer.

Next, HCl and deionized water are mixed at a volume ratio of 1: 1.
Dipped in an etchant mixed for 3 minutes with p-type GaN
The moisture adsorbed on the surface of the layer 102 and the oxide layer formed on the surface were removed.

Subsequently, HF and deionized water were mixed at a volume ratio of 1: 1.
Dipped in an etchant mixed for 3 minutes with p-type GaN
The impurities including carbon attached to the surface of the layer 102 were removed.

After the surface of the p-type GaN layer 102 is cleaned by the above procedure, the Pd layer 104 as the second layer, the Mo layer 105 as the third layer, the Mo layer 105 as the third layer are formed by electron beam (EB) evaporation. An Au layer 106 was formed as four layers. The thickness of each metal layer is 50 nm, 15 nm, 20 nm, respectively.
It was set to 0 nm. Prior to the formation of the Pd layer 104, the metal layer was heated to about 80 to 100 ° C. in a vacuum chamber in order to increase the adhesion of the metal layer to the p-type GaN layer 102.

Finally, the electrode structure thus manufactured was subjected to a heat treatment at 600 ° C. in an N ₂ atmosphere or a vacuum atmosphere of about 1 × 10 ⁻⁶ Torr.

Through the heat treatment step, the p-type G
The aN layer 102 and the Pd layer 104 react, and the first p-type electrode
A Pd—Ga compound layer 103 as a layer was formed, and an electrode structure as shown in FIG. 2 was completed. Hereinafter, this electrode is referred to as an electrode structure A for convenience of description.

The electrode structure A manufactured by the above steps
When the contact resistance was measured, about 4 × 10 ^-4 Ωc
A value of m ² was obtained.

FIG. 3 is a schematic cross-sectional view of a conventional electrode structure having no Mo layer 105 as the third layer of the p-type electrode. The manufacturing procedure of the electrode structure of FIG. 3 is similar to that of the electrode shown in FIG. 2, and after cleaning the surface of the p-type GaN layer 302 epitaxially grown on the sapphire substrate 301,
The layer 304 and the Au layer 305 were sequentially formed by the EB evaporation method, and the Pd-Ga compound layer 303 was formed by performing the heat treatment described above. The Mg doping concentration of the p-type GaN layer 302 is 10 ²⁰ Ωcm ⁻³ , the same as that of the electrode structure A, and the carrier concentration is 5 × 10 ¹⁷ cm ⁻³ . Further, regarding the thickness of each metal layer, the Pd layer 304 is 50 nm, and the Au layer 304 is
Was set to 200 nm. Hereinafter, this electrode is referred to as an electrode structure B for convenience of description.

First, the measurement results of the current-voltage characteristics of the two types of electrode structures A and B will be described.

The electrode used for the measurement has a structure as shown in the schematic diagram of FIG. 4, and the electrode pad 403 has a side length of 300 μm.
And the electrode spacing is 50 μm. Also, the sapphire layer 401 and the p-type GaN layer 402 in the figure are the sapphire layers 101 and 301 and the p-type GaN layers 102 and 30 respectively.
Refers to the same as 2.

FIG. 5 shows the current immediately after the fabrication of the two electrodes.
The voltage characteristics are illustrated. In FIG. 5, the characteristics of the electrode structure B (shown by a dotted line) with respect to the electrode structure A (shown by a solid line) are as follows.
Although it shows ohmic properties but higher resistance characteristics, the formation of the Pd—Ga compound layer 303 is not uniform, and the apparent contact resistance is higher than that of the electrode structure A. That is the cause. On the other hand, in the electrode structure A, the formation of the Pd—Ga compound layer 103 is uniform due to the presence of the Mo layer 105, which is the third layer of the p-type electrode that functions as a reaction uniformizing layer, which is a feature of the present invention. The electrode characteristics show good ohmic characteristics.

FIG. 6 shows that the electrode structures A and B have 10K.
It shows a change in contact resistance when a high-density current of A / cm ² is continuously injected. The reason why the contact resistance of the electrode structure B has started to increase significantly after about 500 hours has elapsed is that the non-uniformly formed Pd-Ga
The influence of denaturation of the compound layer due to high-density current injection into the compound layer or heat generation due to current injection to an interface having an apparently large contact resistance is considered. On the other hand,
Regarding the electrode structure A, no change was observed from the initial characteristics, suggesting that the uniform formation of the Pd—Ga compound layer leads to an improvement in the reliability of the electrode.

FIG. 7 shows that the thickness of the Mo layer and the Pd layer in the electrode structure A of the present embodiment are variously changed so that the ohmic property is not impaired and the characteristics are not changed by the heat treatment step or current injection. Is illustrated. In the figure, ● shows the condition where the result was good, × shows the condition that occurred in either loss of the ohmic property or decrease in the bondability, and the hatched part shows the condition range considered to be almost good.

The thickness of the Mo layer is 3 nm to 50 n.
In the range of about m, characteristics excellent in thermal stability and conduction resistance were obtained as described above. When the thickness of the Mo layer is smaller than 3 nm, for example, 1 nm, the Mo layer and the Pd
Layer partially reacts, or a part of the Pd layer
Undesirably, it breaks through the o layer and causes irregularities on the electrode surface. In addition, when the thickness of the Mo layer was set to be greater than 50 nm, a tendency was observed that electrodes would be lifted or peeled off after all the manufacturing steps. Considering the mechanical strength and adhesion of the electrode, which are important in using the electrode in an actual device, the upper limit of the thickness of the Mo layer seems to be about 50 nm.

Regarding the thickness of the Pd layer, when the thickness of the Mo layer was 3 nm or more, almost the same good characteristics as those of the electrode structure A were obtained at a thickness of 3 nm or more. When the thickness of the Pd layer is smaller than 3 nm, for example, 1 nm, the contact resistance of the electrode tends to increase. This is P
Since the film thickness of d is not sufficiently ensured, most of the Pd layer reacts with Ga supplied from the surface of the underlying p-type GaN contact layer by the heat treatment step of the electrode, and the Pd thus formed -Ga compound layer is directly M
This is because the structure comes into contact with the o-layer. Mo is P
Since the work function is smaller than that of d, p-type GaN
The energy barrier height between the contact layer and the contact layer is increased, which leads to an increase in the contact resistance as compared with the case where the Pd film thickness is sufficiently ensured and a structure like the electrode structure A is formed. Guessed.

The upper limit of the Pd layer is 200 nm.
Even if the thickness is increased to the extent, the ohmic characteristics are not lost, the thermal stability and the conduction resistance are not changed, and there is no particular upper limit, but the lift-off process of the electrode is performed in the manufacturing process. Sometimes, P
In view of the fact that the price of d itself is expensive, it is not necessary to make it thicker, and it may be sufficient to use about 50 nm as a guide.

Finally, FIG. 8 is a schematic diagram showing a cross-sectional structure of a group III nitride semiconductor LD device in which the above electrode structure A is applied as a p-type electrode. The LD device structure of FIG. 8 was manufactured according to the following procedure.

First, an n-type GaN buffer layer 70 is placed on an n-type GaN substrate 701 having a {0001} plane orientation.
2. n-type AlGaN cladding layer 703, n-type GaN optical guide layer 704, InGaAsPN multiple quantum well active layer 7
05, p-type GaN optical guide layer 706, p-type AlGaN cladding layer 707, and p-type GaN contact layer 708
Epitaxial growth is sequentially performed by a CVD method to produce a group III nitride-based semiconductor multilayer structure (FIG. 8A).

Next, a ridge structure is formed on the semiconductor laminated structure using a photolithography process and a dry etching process, and the periphery of the ridge structure is buried with an n-type AlGaN buried layer 709 (FIG. 8B). .

Subsequently, the surface of the ridge structure was organically washed with acetone and ethanol or methanol, and HC was washed.
1 and a mixed etchant of deionized water and HF and deionized water, and then cleaned by dipping, and then a Pd layer 710 as a second layer as a p-type electrode is formed on the upper surface of the ridge structure by EB evaporation. Mo layer 711 as the third layer, fourth layer
Au layers 712 as layers are sequentially stacked. The Pd layer 7
Prior to the formation of film No. 10, in order to increase the adhesion of each metal layer to the p-type GaN layer 708, about 80
Heated to ~ 100 <0> C. The thicknesses of the Pd layer, Mo layer and Au layer were 50 nm, 15 nm and 200 nm, respectively.

After the lower surface of the n-type GaN substrate 701 is cleaned by the same method as described above, the Ti layer 71 is used as an n-type electrode.
3. The Al layer 714 is sequentially laminated by the EB evaporation method. T
The thicknesses of the i layer and the Al layer are 15 nm and 150 nm, respectively.
(FIG. 8C).

Finally, the laminated structure shown in FIG.
A heat treatment was performed at 600 ° C. in a vacuum atmosphere of about × 10 ⁻⁶ Torr to form a Pd—Ga compound layer 715 as the first layer of the p-type electrode, thereby completing the semiconductor LD device structure shown in FIG. That is, the p-type electrode of this semiconductor LD element structure is the same as the electrode structure A.

FIG. 10 shows that the semiconductor LD device has a length of 100 m.
7 shows a change with time of the operating voltage of the element when the current A is applied. As a comparative example, the characteristics of an LD element having the same structure as the above-described semiconductor LD element except that the p-type electrode was changed to the electrode structure B are indicated by broken lines. In both devices, the current injection part of the p-type electrode was 2 μm in width and 500 μm in length.
Has a stripe shape.

As shown in the figure, the operating voltage of the comparative element having the electrode structure B gradually starts to increase when the driving time exceeds about 1000 hours. This phenomenon is the same as that already described for the example of only the electrode structure with reference to FIG. 6, and the denaturation of the non-uniformly formed Pd-Ga compound layer due to the current injection into the compound layer or the interface at the interface This is probably due to the effect of heat generation.

On the other hand, in the semiconductor LD device shown in FIG. 9 which employs the electrode structure A, the increase in operating voltage seen in the comparative device is hardly observed, and the reaction uniformizing layer which is a feature of the present invention is formed. Third layer Mo layer 711 of a functioning p-type electrode
Suggests that the existence is working effectively.

Further, the above two types of semiconductor LD elements are represented by L
Mounting on the stem for D and bonding of the Al wire as the feeder line. However, in the comparative device employing the electrode structure B, bonding failure such as peeling of the Al wire or not bonding the electrode and the Al wire often occurs. As a result, the yield of non-defective products decreased. As described above, the cause of this phenomenon is unevenness on the electrode surface due to the non-uniformity of the Pd-Ga compound layer caused by the heat treatment performed at the end of the manufacturing process of the LD element structure.

On the other hand, in the LD element adopting the electrode structure A, no bonding failure or the like occurs at all, and all the elements put into the mounting process are non-defective, and the reaction uniformity which is a feature of the present invention in terms of bondability is also obtained. Mo as activated layer
The existence of the layer suggests that it is working effectively.

In the above example of the LD element, the plane orientation of the n-type GaN substrate used as the substrate is {0001}
Surface, but also {1-100} surface, {11-2}
Similar experiments were performed on each of the 0 ° plane, {1-101} plane, and {01-12} plane, and further, a substrate shifted ± 2 ° from these plane directions. The effect of the barrier layer shown could be confirmed.

In addition, Pd is applied between the p-type GaN contact layers.
As an alternative to the first metal Pd forming the -Ga compound, P
The same experiments as above were attempted for t, Ni, Ir, Os, Rh, and Ru, but there were slight differences in the heat treatment temperature varying from 500 ° C. to 900 ° C., the heat treatment time, and the required layer thickness. However, the effect of the Mo layer, which is the third layer of the p-type electrode functioning as a uniform reaction layer, which is a feature of the present invention, similar to the case of using Pd, can be confirmed using any metal. Incidentally, in the above embodiment, the atmosphere of the heat treatment is a vacuum atmosphere, but may be a gas atmosphere of N ₂ , O ₂ , Ar or the like, or a mixed atmosphere thereof. The effect of the Mo layer, which is the third layer of the p-type electrode, as a uniform reaction layer is that the first metal has P
It was effective not only when each of the single metals d, Pt, Ni, Ir, Os, Rh, and Ru, but also when several kinds of metals were alloyed.

In the above examples, Mo was used as the second metal as the material of the reaction uniformizing layer. However, the same experiment as described above was attempted with W, Ir, Rh, and Ru as alternative metals. As a result, no matter which metal is used, Mo
In the same manner as in the above case, it was confirmed that the layer effectively acted as a uniform reaction layer. The effect of the reaction uniform layer is Mo,
It was also found that not only single metals of W, Ir, Rh, and Ru, but also alloys of several kinds of metals were effective. However, regarding Ir, Rh, and Ru, when the same metal is selected as the first metal, if the same metal is also used for the third layer, an interface reaction between the second layer and the third layer progresses. As a result, the third layer could not exhibit the effect as the interface reaction uniforming layer. Therefore, Ir, Rh, Ru are added to the third layer.
Must not be selected for the first metal at the same time.

In this embodiment, the EB vapor deposition method, which is one of the vacuum vapor deposition methods, is used for depositing each metal of the p-type electrode. However, the characteristics of the present invention are not affected by the film deposition method. There is no problem even if other thin film forming methods such as a chemical vapor deposition method and a high frequency sputtering method are used.

The above-described example of the electrode structure and the semiconductor LD
In each of the examples of the device, a heat treatment process is used for forming the Pd-Ga compound layer, but the Pd-Ga compound is directly applied to the thin film forming method such as the above-described vacuum deposition method, chemical vapor deposition method, and high-frequency sputtering method. The formation of the film does not impair the features of the present invention.

[0054]

According to the present invention, Au / Pd / Pd-Ga which is a p-type low resistance electrode of a group III nitride semiconductor device is provided.
It is possible to improve the thermal stability and the current-carrying resistance of the compound electrode, and it is possible to suppress a temporal change in the electrode characteristics when the electrode is applied to an element and driven. Further, it is possible to prevent a decrease in bondability at the time of wire bonding to the electrode portion, and to improve the yield rate of the LD package.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state of forming a metal layer in a manufacturing process of an electrode structure of the present invention.

FIG. 2 is a schematic cross-sectional view showing a state after a heat treatment in a manufacturing process of the electrode structure of the present invention.

FIG. 3 is a schematic sectional view showing an electrode structure according to a conventional example for the present invention.

FIG. 4 is a schematic diagram showing a sample structure for evaluating characteristics of the electrode structure of the present invention.

FIG. 5 is a schematic diagram showing current-voltage characteristics of the electrode structures of the present invention and a comparative example.

FIG. 6 is a diagram showing a change over time in contact resistance when current is continuously injected into the electrode structures of the present invention and a comparative example.

FIG. 7 is a schematic diagram for judging the quality of electrode characteristics when the thickness of each layer of the electrode structure of the present invention is changed.

FIG. 8 shows a group III nitride semiconductor LD according to an embodiment of the present invention.
6 is a schematic cross-sectional view showing a process of manufacturing the element.

FIG. 9 is a schematic sectional view showing the structure of a group III nitride semiconductor LD device shown in an example of the present invention.

FIG. 10 is a diagram showing a change over time of an operating voltage of the group III nitride semiconductor LD device shown in the example of the present invention.

[Explanation of symbols]

 Reference Signs List 101 sapphire substrate 102 p-type GaN layer 103 Pd-Ga compound layer 104 Pd layer 105 Mo layer 106 Au layer 401 sapphire substrate 402 p-type GaN layer 403 p-type electrode structure 701 n-type GaN Substrate 702: n-type GaN buffer layer 703: n-type AlGaN cladding layer 704: n-type GaN light guide layer 705: InGaAsPN multiple quantum well active layer 706: p-type GaN light guide layer 707: p-type AlGaN cladding layer 708: p-type GaN contact layer 709 n-type AlGaN buried layer 710 Pd layer 711 Mo layer 712 Au layer 713 Ti layer 714 Al layer 715 Pd-Ga compound layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA04 AA10 BB04 BB05 BB07 BB14 CC01 DD22 DD23 DD35 DD37 DD78 DD83 FF02 FF17 GG04 HH15 HH20 5F073 AA07 AA74 CA20 CB02 CB05 CB07 CB22 EA28

Claims (7)

[Claims] 1. A group III nitride-based compound semiconductor device comprising a group III nitride-based semiconductor layer containing a p-type impurity and a p-type electrode in contact with the group III nitride-based semiconductor layer. A first layer made of a compound of a first metal and gallium, a second layer made of a first metal, a third layer made of a second metal,
I is characterized by comprising a fourth layer made of a third metal.
Group II nitride compound semiconductor device. 2. The method according to claim 1, wherein the first metal is Pd, Pt, Ni,
2. The group III nitride-based compound semiconductor device according to claim 1, comprising at least one of Ir, Os, Rh, and Ru. 3. The group III nitride compound semiconductor device according to claim 1, wherein the thickness of the second layer is 3 nm or more. 4. The third layer comprises Mo, W, Ir, Rh,
The group III nitride compound semiconductor device according to claim 1, wherein at least one of Ru is included. 5. The thickness of the third layer is 3 nm or more and 50
2. The compound according to claim 1, wherein the diameter is equal to or less than nm.
Group I nitride compound semiconductor device. 6. A method of manufacturing a group III nitride-based semiconductor including a p-type impurity and a group III nitride-based compound semiconductor including a p-type electrode, wherein the group III nitride-based semiconductor layer includes a p-type impurity. A second layer made of a first metal and a second layer
Forming a third layer of a third metal and a fourth layer of a third metal in sequence, and then performing a heat treatment at 500 ° C. to 900 ° C. to form a third layer between the group III nitride-based semiconductor and the second layer. A method for manufacturing a group III nitride-based compound semiconductor device, comprising a step of forming a first layer made of a compound of metal and gallium. 7. A method for manufacturing a group III nitride-based semiconductor including a p-type impurity and a group III nitride-based compound semiconductor including a p-type electrode, wherein the group III nitride-based semiconductor layer includes a p-type impurity. Forming a first layer made of a compound of a first metal and gallium, a second layer made of a first metal, a third layer made of a second metal, and a fourth layer made of a third metal in this order; A method for manufacturing a group III nitride compound semiconductor device, comprising: