JP2002353431A - Photoelectric transducer and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form the embedded region of a photoelectric transducer, using a threshold modulation-type MOS transistor with satisfactory reproducibility and to provide a pixel and a chip, whose characteristics are adjusted. SOLUTION: The transducer has a photodiode and an insulation gate-type transistor; the embedded region 8 of high impurity concentration for collecting charges generated in the photodiode is arranged, in a well 13 below the gate electrode of the transistor; and the embedded region 8 is self-matched with the source side end part of the gate electrode 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device and a manufacturing method used for an imaging device such as a digital still camera, a video camera recorder, a facsimile, and an image scanner, and more specifically, to a threshold modulation type MOS photoelectric conversion device. The present invention relates to an apparatus and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, a photoelectric conversion device is suitable for an imaging device for inputting a two-dimensional image, mainly a digital still camera or a video camera recorder, or an imaging device for reading a one-dimensional image, mainly a facsimile or a scanner. Demand is growing rapidly.

As these photoelectric conversion devices, CCD (Ch)
For example, an arge coupled device (charge coupled device) or a MOS type photoelectric conversion device is used. The former has higher sensitivity and lower noise than the latter,
Although it is widely used as a high-quality image pickup device, it consumes a large amount of power, has a high drive voltage, cannot be used for a general-purpose semiconductor manufacturing process, is expensive, and it is difficult to integrate peripheral circuits such as a drive circuit. .

For this reason, it is expected that a so-called MOS type photoelectric conversion device using an insulated gate type transistor will be often used for application to portable equipment, for which demand is expected to increase in the future. For that purpose, in order to improve the low image quality, which is a drawback of the MOS photoelectric conversion device, an element structure capable of suppressing noise with a smaller number of transistors is desired.

Since the number of transistors per pixel is small, BCMD (Bulk Charge) has long been used as a photoelectric conversion device capable of obtaining a large aperture ratio even with fine pixels.
Modulated Device) has been devised.

As an improved type of BCMD, electric charges generated in a photodiode are collected in a high-concentration impurity layer buried immediately below a channel of a MOS transistor.
A method of detecting charge by changing the threshold value of the OS transistor can be considered.

FIGS. 14 to 17 are diagrams for explaining the improved BCMD invented by the inventor first.
1 is a circuit diagram of one pixel, FIG. 15 is a plan view thereof, and FIG.
FIG. 6 is a sectional view taken along line AA 'in FIG.

Reference numeral 1 denotes a photodiode for photoelectrically converting incident light; 2, a gate electrode of a MOS transistor whose threshold value is modulated by electric charges generated from the photodiode 1;
Is a source region of the MOS transistor, 4 is a contact region connecting the source region to the wiring, 5 is a source electrode, 6 is M
A contact connecting the drain region of the OS transistor to the wiring, 7 is a drain electrode, 8 is a high-concentration buried region for collecting charges generated in the photodiode 1, and 9 is an element isolation region.

The channel stop region 10 and the well region 13 are made of p-type silicon, and the source region 16 and the drain region 15 are made of n-type silicon. Well region 13 is formed in n-type region 12, and n-type region 12 is formed in p-type substrate 1.
On one. The buried region 8 is of the same conductivity type as the well region 12 and is made of p-type silicon having a higher concentration than the well region 12.

The photodiode 2 has a structure in which a part of the well region 13 serves as an anode and a part of the drain region 15 and the n-type region 12 serves as a cathode. Are accumulated in the well region 13 in a floating state, and are collected and accumulated in the buried region 8 having a low potential for holes.

Referring now to FIG. 17, the manner in which the conductivity of a MOS transistor is modulated by the accumulated charges will be described. FIG. 17 shows an enlarged view of the gate electrode of the MOS transistor and the structure below the gate electrode. The holes 21 generated in the photodiode are accumulated in the buried region 8. This charge generates a mirror image charge 22 on the gate electrode 2. Due to the mirror image charge 22, the MO immediately below the mirror image charge 22
The threshold value of the S transistor changes. With this operation, in an operation state in which a constant read gate voltage is applied to the gate electrode 2, the current flowing between the source and the drain of the MOS transistor changes according to the threshold value.

Next, a method of manufacturing the photoelectric conversion device shown in FIGS. 15 and 16 will be described. An n-type layer 12 is formed by epitaxially growing the p-type silicon 11. Next, the whole is thinly oxidized, then a silicon nitride film is deposited, and the oxide film / silicon nitride film in the element isolation region is removed by etching. After ion implantation of p-type ions to form a channel stop region 10 between pixels, LOCOS oxidation is performed to form an element isolation region 9. A resist pattern is formed, and ions are implanted using the resist pattern as a mask to form a well region 13. Next, a resist pattern for forming a buried region is formed, and ion implantation is performed using the resist pattern as a mask. Next, after forming a gate insulating film 14 on the surface, polysilicon is deposited and patterned into a gate electrode shape. Using this gate electrode 2 as a mask, an n-type source region 16 and a drain region 15 are formed by ion implantation. After that, deposition of insulating film, opening of contact,
By depositing and patterning a wiring metal film, contacts 4 and 6 and source / drain electrodes 5 and 6 are formed.

[0013]

However, in the above manufacturing method, the distance between the buried region 8 and the source region 16 of the MOS transistor varies for each chip of the photoelectric conversion device to be manufactured or for each lot of the wafer at the time of manufacturing. As a result, the sensitivity of the photoelectric conversion device varies.
The reason is that the relative position between the buried region 8 and the source region 16 affects the sensitivity as described below.
The change amount ΔVth of the threshold value of the MOS transistor is represented as follows: ΔVth = Q / C (Equation 1) where Q is the charge amount stored in the buried region C is the charge 21 stored in the buried region and its mirror image Further, as shown in FIG. 17, the capacitance C formed between the charges 22 is the MO directly above the buried region 8.
It comprises a capacitance Cg of the gate insulating film 14 of the S transistor and a series capacitance of the capacitance Csi of the silicon region from below the insulating film 14 to the buried region 8. Therefore, C = Cg · Csi / (Cg + Csi) (Equation 2) Since the detection sensitivity, which is an important characteristic of the photoelectric conversion device, is proportional to the charge conversion coefficient, that is, the output voltage generated by one generated charge, η = E / C (Equation 3) where η is the charge conversion coefficient, e is the elementary charge, and C is the capacity defined by (Equation 2).

When the distance from the buried region 8 to the gate electrode 2 is sufficiently shorter than the distance from the buried region to the source electrode, as shown in FIG. Although the termination ends at the mirror image charge 22 in the electrode, as the buried region 8 approaches the source region 16, the proportion of the lines of electric force generated from the charge 21 that terminate in the source region increases. Therefore, the mirror image charge induced in the gate electrode is reduced accordingly. Therefore, the charge collected in the buried region is effectively MO
It becomes impossible to cause a change in the threshold value of the S transistor. This means that the sensitivity is reduced.

As described above, the sensitivity of the photoelectric conversion device varies depending on the distance between the buried region 8 and the source region 16. If the distance between the buried region and the source region is sufficient, the size of the MOS transistor becomes large, and a fine pixel structure cannot be realized.

Therefore, an object of the present invention is to provide a buried region with good reproducibility, to suppress the non-uniformity in sensitivity of each chip even if the element size is reduced, and to obtain a threshold having uniform characteristics over a large number of pixels. An object of the present invention is to provide a method for manufacturing a photoelectric conversion device capable of manufacturing a modulation type MOS transistor.

[0017]

The first invention of the present application has a photodiode and an insulated gate transistor, and collects electric charges generated by the photodiode in a well below a gate electrode of the transistor. In a photoelectric conversion device provided with a buried region having the same conductivity type as the well and a higher impurity concentration than the well, the buried region is aligned with an end of a gate electrode of the transistor. I do.

According to a second aspect of the present invention, there is provided a photodiode and an insulated gate type transistor, wherein the well is provided under the gate electrode of the transistor to collect electric charges generated by the photodiode and to conduct electricity to the well. Forming a first conductive type well in a semiconductor substrate and forming a gate electrode of the MOS transistor in a method of manufacturing a photoelectric conversion device having a mold and a buried region having a higher impurity concentration than the well; Performing ion implantation into the well so as to align the buried region with an end of a gate electrode of the MOS transistor.

[0019]

(Embodiment 1) A photoelectric conversion device according to Embodiment 1 of the present invention will be described with reference to FIGS.

FIG. 1 is a sectional view of one pixel of the photoelectric conversion device. The planar configuration and the circuit configuration are the same as those in FIGS.

1 is a charge (here, a hole) due to incident light.
Is a gate electrode of a read-out insulated gate transistor (MOS transistor) that performs channel conductivity modulation by generated carriers. Here, the photodiode 1
Is a buried photodiode in which a p-type well 13, an n-type drain region 15, and an n-type region 12 form a pn junction.

The gate electrode 2 can be made of, for example, polysilicon doped with impurities, or a laminate of polysilicon and metal or metal silicide. Reference numeral 3 denotes a source region made of an n-type semiconductor of the MOS transistor, from which a modulated output current of the MOS transistor can be taken. Reference numeral 4 denotes a source contact made of a conductor such as aluminum or tungsten filled in a contact hole of an insulating layer (not shown), and reference numeral 5 denotes a source electrode (source wiring) made of a conductor such as aluminum or copper. Reference numeral 6 denotes a drain contact made of a conductor such as aluminum or tungsten filled in a contact hole of an insulating layer (not shown). Reference numeral 7 denotes a drain electrode (drain wiring) made of a conductor such as aluminum or copper. Connected to power supply for driving. Reference numeral 8 denotes a buried region, which is made of a p-type semiconductor having a high impurity concentration. The buried region 8 matches the source side end 2E of the gate electrode 2.

Reference numeral 9 denotes an element isolation region made of silicon oxide or the like, which prevents crosstalk between adjacent pixels.
Reference numeral 10 denotes a channel stop region made of a p-type semiconductor with a high impurity concentration for element isolation, 11 a substrate made of a p-type semiconductor, 12 a region made of an n-type semiconductor, and a well 13 made of a p-type semiconductor for each pixel. Surrounding the well 13 so as to be independent. 14 is a gate insulating film made of silicon oxide or the like, 15 is a drain region made of a high impurity concentration n-type semiconductor serving as a drain, and the source electrode 5 is a signal output wiring.

Next, the operation of the photoelectric conversion device will be briefly described.

The operation of photoelectric conversion is performed in the order of reset → accumulation → read, and this operation is repeated. In the reset operation, all holes remaining in the p-type well region 13 and the p ⁺ -type buried region 8 are discharged to the substrate 11. For this purpose, a reset bias voltage (for example, about 5 to 10 V) serving as a positive bias is applied to the drain electrode 7 and the gate electrode 2 of the MOS transistor with respect to the substrate 11. At this time, since the depletion layer extending from the upper and lower pn junction interfaces is punched through and depleted in the n-type region 12, the p-type well 13 and the p ⁺ -type buried region 8 are depleted.
Are discharged to the substrate 11 and p
Since the well 13 of the type and the buried region 8 of the p ⁺ type are also depleted, random noise due to thermal fluctuation of carriers does not occur.

In the storage operation after reset, a storage bias voltage (for example, 3 to 5 V) that can reverse bias the photodiode 1 is applied to the drain electrode 7. Further, the gate voltage applied to the gate electrode 2 is set to a voltage equal to or lower than the threshold value of the MOS transistor (for example, -3 volts to +1 volt) so that the channel of the MOS transistor is in an accumulation state or a depletion state. In this state, light is applied to the photodiode 1
Incident on The charges generated by the incident light, that is, the electrons of the electron-hole pair are sucked out to the drain region 15 and the drain electrode 7, and the holes are collected in the buried region 8 through the p-type well 13 by diffusion and drift.
In the present embodiment, holes collect in any of the plurality of buried regions 8. The gap between adjacent buried regions 8 is designed to be small enough that holes are drawn to a potential gradient from any of the buried regions 8. In the read operation, the modulation of the conductivity of the MOS transistor induced by the holes accumulated in the buried region 8 is represented by M
The current is read from the source electrode 5 as the OS transistor current. For the read operation, the voltage applied to the gate electrode 2 of the MOS transistor is set to a threshold voltage or higher.
The gate voltage is determined so that the MOS transistor operates in the pentode region in order to ensure the linearity of the current-voltage characteristic as the photoelectric conversion device.

In the present embodiment, if the buried region 8 is divided into a plurality as necessary, the capacitance at the time of detecting the charge can be reduced, and the sensitivity as the photoelectric conversion device is improved.

As a method of dividing the embedding area 8, MO
By dividing the S transistor in the channel width direction (gate width direction), the sensitivity can be efficiently increased.

The side closer to the photodiode 1 in the source region 3 of the MOS transistor is the direction in which the charges generated by the incident light are diffused and drifted. In a portion without the buried region 8, the charge cannot be captured by the buried region 8 and disappears in the source region 3 of the MOS transistor. Such loss is unlikely to occur on the side of the source region 3 where the photodiode 1 is not provided. By changing the size and density of the buried region 8 according to the positional relationship between the photodiode and the source region of the MOS transistor, a design that maximizes the sensitivity becomes possible.

Next, a method for manufacturing a photoelectric conversion device according to an embodiment of the present invention will be described with reference to FIGS.

An n-type layer 12 is formed by epitaxial growth on a semiconductor substrate 11 made of p-type single crystal silicon. Since the thickness of the n-type layer determines the spectral sensitivity on the long wavelength side, the thickness is determined according to the light to be detected. Next, in order to form the element isolation region 9, the whole is thinly oxidized, a silicon nitride film is deposited, and the oxide film / silicon nitride film in the portion where the element isolation region 9 is to be formed is removed by etching. Channel stop region 10 also acting as element isolation
Is formed by implanting ions of a p-type impurity such as boron by using an ion implanter, and performing LOCOS oxidation to produce element isolation regions 9 and 10. afterwards,
A resist made of a photosensitive resin is applied, exposed to a predetermined pattern, and developed, and then a p-type impurity is implanted into a portion where the well region 13 is to be formed, and heat treatment is performed. The amount of ion implantation of the well region 13 and the heat treatment after the ion implantation are determined so that the voltage can be depleted at a desired voltage during the reset operation, and the saturation charge of the photodiode becomes a desired value.

Next, in order to form a gate electrode, after forming a gate insulating film 14, a conductor such as polysilicon is deposited and patterned to form a gate electrode 2. Thus, the structure shown in FIG. 2 is obtained.

Next, a resist is applied, and the resist in a region for forming a buried region is removed by patterning. The resist pattern PR completely covers the region where the drain region of the MOS transistor is to be formed, but exposes the right end 2E of the gate electrode in the drawing and the region where the source region is to be formed. Next, a p-type buried region 8 is formed by ion implantation of boron. At this time, oblique ion implantation is performed so that the ions are incident in the gate direction as viewed from the source side. Part of the buried region 8 can be formed vertically (directly below) the gate electrode 2 by oblique ion implantation. The inclination angle θ of the ion implantation is 10 with respect to the normal to the substrate surface.
Is suitable. The depth of the buried region 8 is set to a position deeper than the effective channel of the MOS transistor. The concentration of the buried region 8 needs to be sufficiently higher than that of the well region 13 so that holes can be accumulated. However, if the implantation is performed at an excessively high dose, the p-type dopant is replaced with the n-type dopant by ion implantation at the time of forming the source region 3 later. Since it becomes impossible to cancel, it is desirable that the concentration is 1/10 or less of the concentration of the source region 3 to be formed later. Thus, the structure shown in FIG. 3 is obtained.

After removing the resist pattern PR, an n-type source region 3 and a drain region 15 are formed by ion implantation and heat treatment using the gate electrode as a mask.
The portion of the p ⁺ -type region implanted for forming the buried region 8 that is not masked by the gate electrode 2 has a depth of ion implantation lower than that of the p-type dopant implantation so that the n ⁺ -type cancels the p ⁺ -type. Adjust the dose and increase the dose. As a result, only a portion immediately below the gate of the p ⁺ -type region is remaining, a buried region 8 collects charges as p ⁺ -type region. Thus, the structure shown in FIG. 4 is obtained. Thus, the buried region 8 is self-aligned with the end 2E of the gate electrode 2. Thereafter, the deposition of the insulating film, the opening of the contact, the deposition of the wiring metal film, and the patterning are repeated to obtain the structure as shown in FIG. Thereafter, a metal light shielding layer (not shown) is formed as necessary. When a color photoelectric conversion device is manufactured, a color filter layer is formed and a micro lens is formed thereafter.

(Embodiment 2) FIG. 5 is a sectional view of a photoelectric conversion device according to this embodiment. The illustration of contact openings, wiring, and the like is omitted. In this embodiment, the source / drain structure of a MOS transistor is a so-called LDD (Light
(Dropped Drain) structure. In order to form an LDD structure, a side spacer 20 made of an insulating film is formed on a side wall of the gate electrode 2.

The n-type layer 12 is formed by epitaxially growing the p-type silicon 11. Next, in order to form an element isolation region, the whole is thinly oxidized, then a silicon nitride film is deposited, and the oxide film / silicon nitride film in the element isolation region is removed by etching. After ion implantation of a p-type dopant is performed to form a high concentration channel stop region 10 between pixels, LOCOS oxidation is performed to form an element isolation region 9. The well region 13 is formed by resist patterning and ion implantation. The dose of the ion implantation into the well region 13 and the heat treatment after the ion implantation are determined so that the depletion can be performed at a desired voltage during the reset operation, and the saturation charge of the photodiode becomes a desired value. In order to determine the impurity profile of the channel of the MOS transistor, p-type and n-type impurity layers are formed near the channel by ion implantation as necessary. Gate insulating film 14 on the surface
Is formed, polysilicon is deposited, and the gate electrode is patterned. Next, a resist PR is applied, and the resist in a region where a buried region is to be formed is removed by patterning. Although the resist pattern PR completely covers the drain region of the MOS transistor, the source-side end 2
E and the source region are exposed. Next, a p-type buried region 8 is formed by ion implantation of boron. Oblique ion implantation is performed so that ions are obliquely incident in the gate direction as viewed from the source side. Part of the buried region can be formed immediately below the gate electrode by oblique ion implantation. 10 ° to 40 ° is appropriate as the inclination angle θ of the injection. The depth of the buried region 8 is set to a position deeper than the channel of the MOS transistor. The concentration of the buried region 8 needs to be sufficiently higher than that of the well region 13 so as to accumulate holes. Therefore, it is desirable that the concentration be 1/10 or less of the concentration of the source region. Thus, the structure shown in FIG. 6 is obtained.

The operation up to this point is the same as that of the first embodiment.

Next, after removing the resist PR, phosphorus ions are implanted into the n-type source / drain low impurity concentration regions, that is, the electric field relaxation layers 15b, 16c, 16d, 16
forming e. At this time, the depth and concentration of the p ⁺ layer are set in advance so that the p ⁺ -type region of the p ⁺ region 8 by the n-type ion implantation is almost completely canceled out from the p ⁺ -type region. Therefore, the electric field relaxation region of the source region is a region 16c which is close to the silicon surface and remains as an n-type layer, and a part of the buried region is canceled out to be substantially neutral or well region 13.
Are divided into three regions: a region 16d having substantially the same concentration as the above, and a region 16e having no buried region and having the same concentration as the drain side. The buried region 8 is formed below the gate electrode in a self-aligned manner at the end of the gate electrode. Next, after depositing a silicon oxide film or the like by the CVD method, a so-called side spacer 20 is formed by leaving the silicon oxide film only on the side wall of the gate electrode 2 by anisotropic etching. Thus, the structure shown in FIG. 7 is obtained.

Using the gate electrode 2 as a mask, an n-type high concentration source region 16a and drain region 15a are formed by ion implantation. The low-concentration electric field relaxation region remains only under the side spacer 20 due to the formation of the high-concentration n-type regions 15a and 16a, and thus, as shown in FIG. 5, the source electric field relaxation region 16b and the drain electric field relaxation region 15b Is formed. In this manner, the buried region 8 and the source region 3 are formed in a self-aligned manner at the source side end 2E of the gate electrode.

Thereafter, the deposition of the insulating film, the opening of the contact, the deposition of the wiring metal film, and the patterning are repeated, and finally, a metal light-shielding layer (not shown) is formed to complete the process. When a color photoelectric conversion device is manufactured, a color filter layer is formed and a micro lens is formed thereafter.

(Embodiment 3) FIG. 8 shows a threshold-modulated MO.
FIG. 3 is a plan view of one pixel of a photoelectric conversion device in which an S transistor has a ring shape. Reference numeral 1 denotes a photodiode that generates and accumulates charges by incident light, 2a denotes a gate electrode of a read MOS transistor that performs channel conductivity modulation by generated carriers, 2b denotes a gate wiring, 3 denotes a source region of the MOS transistor, and 4 denotes a source region of the MOS transistor. Source contact 5 is a source electrode. Gate electrode 2 a surrounds source region 3 in a ring shape. 6 is a drain contact of the MOS transistor, and 7 is a drain electrode. Reference numeral 8 denotes a plurality of buried regions, which are divided along the shape of the gate electrode so as to surround the source region. 9
Is an element isolation region. FIG. 9 is a sectional view taken along the line BB 'of FIG. 10 is a high-concentration channel stop region for element isolation, 11 is a silicon substrate, 12 is a well-conducting region surrounding the well 13, 14 is a gate insulating film of a MOS transistor, 15 is a drain region, and 16 is a source. Area.

In this embodiment, the gate electrode 2a is formed in a ring shape, and the buried region 8 is formed along the shape of the gate electrode 2a.
Are also arranged so as to surround the source region 15. The ring shape of the gate electrode allows the holes diffused from the photodiode to be surely collected,
Since the gate width of the OS transistor can be increased, a larger output load can be driven. Therefore, it is effective for speeding up the reading.

Next, the manufacturing method will be described.

The steps up to the step of forming the gate electrode are exactly the same as those in the first and second embodiments. That is, the n-type layer 12 is formed by epitaxially growing the p-type silicon 11. Next, in order to form an element isolation region, the whole is thinly oxidized, then a silicon nitride film is deposited, and the oxide film / silicon nitride film in the element isolation region is removed by etching. After implanting p-type dopant ions to form a high concentration channel stop region 10 between pixels, the LOCOS
Oxidation is performed to complete the element isolation region 9. The well region 13 is formed by resist patterning and ion implantation. The dose amount of the ion implantation of the well region 13 and the heat treatment after the ion implantation are determined so that the reset operation can be depleted with a desired voltage and the saturation charge of the photodiode becomes a desired value. In order to determine the impurity profile of the channel region of the MOS transistor, p-type and n-type impurity layers are formed near the channel by ion implantation as necessary. After forming the gate insulating film 14 on the surface, polysilicon is deposited, and the gate electrode is patterned. Thus, the structure shown in FIG. 10 is obtained. next,
As in the first embodiment, a resist is applied, and the resist in the region where the buried region 8 is to be formed is removed by patterning. The resist pattern PR completely covers the drain region of the MOS transistor, but exposes the source side end 2E of the gate electrode and the source region. Next, a p-type buried region 8 is formed by ion implantation of boron.
To form The ion implantation is performed by a so-called rotary ion implantation method in which the wafer is inclined with respect to the silicon surface and the wafer is rotated with respect to a normal line. With this method, a buried region can be formed at a fixed position immediately below the gate electrode in all directions surrounding the source region 16.
10 ° to 40 ° is appropriate as the inclination angle θ of ion implantation. The depth of the buried region is set to a position deeper than the channel of the MOS transistor. The concentration of the buried region needs to be sufficiently higher than that of the well region 13 so that holes can be accumulated. Therefore, it is desirable that the concentration is 1/10 or less of the concentration of the source region. Thus, the structure shown in FIG. 11 is obtained.

After removing the resist PR, the gate electrode 2
Using a as a mask, an n-type source region 16 and a drain region 15 are formed by ion implantation. Of the p ⁺ -type regions implanted to form the buried region, the gate electrode 2
For the portion not masked by a, the depth of ion implantation and the dose are determined so that the n ⁺ type cancels the p ⁺ type. As a result, only a portion immediately below the gate of the p ⁺ -type region is remaining, the buried region collect charge as a p ⁺ -type region. Thus, the structure shown in FIG. 12 is obtained. The buried region 8 is thus the source-side end 2 of the gate electrode.
E, self-aligned here with the inner edge of the ring-shaped gate electrode. After that, deposition of insulating film, opening of contact,
The deposition and patterning of the wiring metal film are repeated, and finally, a metal light shielding layer (not shown) is formed to complete the process. When a color photoelectric conversion device is manufactured, a color filter layer is formed thereafter,
Form a micro lens.

The source and drain of the MOS transistor can have an LDD structure. In that case, it is possible to manufacture by the same method as the method shown in the second embodiment.

According to each of the embodiments, since the buried region is aligned with the gate electrode, it is possible to obtain a threshold modulation type photoelectric conversion device with improved controllability of sensitivity variation.
Specifically, the dimensional variation and the positional variation of the buried region, which were the major factors of the sensitivity variation, were all caused by self-alignment formation with respect to the source type end of the gate electrode.
Since the suppression can be easily performed, a high-sensitivity photoelectric conversion device can be provided with small variations without increasing the manufacturing cost.

The present invention also works effectively with a photoelectric conversion device that does not use a microlens or a monochrome photoelectric conversion device that does not use a color filter.

FIG. 13 is a schematic configuration diagram of an imaging device such as a digital camera employing the photoelectric conversion device of the present invention.

Reference numeral 31 denotes an image forming optical system such as a lens; 32, a photoelectric conversion device of each of the above-described forms; 33, a control circuit;
Is a memory. The image of the subject is exposed to the pixels of the photoelectric conversion device 32 through the imaging optical system 31, and is converted into an electric signal. The obtained electric signal of the image is subjected to appropriate image processing by a controller and stored in a memory.

[0051]

According to the present invention, the relative position between the buried region and the gate electrode can be manufactured with good reproducibility, and a threshold modulation type MOS transistor having uniform characteristics over a chip or a large number of pixels can be manufactured. .

As described above, the characteristics of the MOS type photoelectric conversion device of the threshold modulation type suitable for the fine pixel are improved, so that the application of the portable device, the digital camera and the like can be expanded.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a threshold modulation type photoelectric conversion device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a threshold modulation type photoelectric conversion device according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the second embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the second embodiment of the present invention.

FIG. 8 is a sectional view of a threshold modulation type photoelectric conversion device according to Embodiment 3 of the present invention.

FIG. 9 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the third embodiment of the present invention.

FIG. 10 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the third embodiment of the present invention.

FIG. 11 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the third embodiment of the present invention.

FIG. 12 is a cross-sectional view for explaining a manufacturing process of the threshold modulation type photoelectric conversion device according to the third embodiment of the present invention.

FIG. 13 is a schematic diagram of an imaging device using the threshold modulation type photoelectric conversion device of the present invention.

FIG. 14 illustrates a pixel circuit configuration of a threshold modulation type photoelectric conversion device.

FIG. 15 is a plan view of a pixel of the threshold modulation type photoelectric conversion device.

FIG. 16 is a pixel cross-sectional view of a threshold modulation type photoelectric conversion device.

FIG. 17 is a partially enlarged view of a pixel section of a threshold modulation type photoelectric conversion device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Photodiode 2, 2a Gate electrode of MOS transistor 3, 16 Source region of MOS transistor 4 Source contact 5 Source electrode 6 Drain contact 7 Drain electrode 8 Buried region 9 Element isolation region 13 Well region 14 MOS transistor gate insulating film 15 Drain region

Claims (7)

[Claims] 1. A transistor having a photodiode and an insulated gate transistor, wherein the transistor is of a conduction type with the well for collecting charges generated in the photodiode in a well below a gate electrode of the transistor. A photoelectric conversion device provided with a buried region having a higher impurity concentration than the well, wherein the buried region is aligned with an end of the gate electrode of the transistor. 2. The photoelectric conversion device according to claim 1, wherein the buried region is located immediately below the gate electrode of the transistor and closer to the channel region than a low impurity concentration region constituting a source region of the transistor. . 3. A transistor having a photodiode and an insulated gate transistor, wherein the transistor is of a conduction type with the well for collecting charges generated in the photodiode in a well below a gate electrode of the transistor. A method for manufacturing a photoelectric conversion device provided with a buried region having a higher impurity concentration than the well; a step of forming a first conductivity type well in a semiconductor substrate; a step of forming the gate electrode of the transistor; Performing ion implantation into the well so as to match with the end of the gate electrode of the transistor. 4. The photoelectric conversion device according to claim 1, wherein said buried region is formed by oblique ion implantation after forming said gate electrode of said transistor, and at least a part of said buried region is located immediately below said gate electrode. . 5. The photoelectric conversion device according to claim 3, wherein the source region of the transistor is formed by ion-implanting a counter-conducting dopant so as to cancel the dopant implanted to form the buried region. Production method. 6. After forming the gate electrode of the transistor, ion implantation for forming the buried region is performed to form a side spacer of the gate electrode of the MOS transistor. 4. A high impurity concentration region is formed.
A manufacturing method of the photoelectric conversion device according to the above. 7. The method according to claim 3, wherein, after forming the gate electrode of the transistor, the buried region is formed by rotary ion implantation so as to surround the source region of the transistor.