JP2002353324A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for avoiding malfunction caused by the occurrence of etching residue, and to provide its manufacturing method. SOLUTION: After having formed a lead electrode 3 on a semiconductor substrate, an interlayer dielectric 5 is deposited on the substrate and planarized. Then, holes 6a, 6b are formed in the interlayer dielectric 5, and after having formed a barrier metal layer 7 on a wall surface of the holes 6a, 6b, a conductive plug 8 is buried in the holes 6a, 6b. Subsequently, a lower electrode, an upper electrode facing the lower electrode, and a dielectric film for forming capacitance to intervene between the lower electrode and the upper electrode are sequentially formed on the substrate. By covering a step that is caused between the lower lead electrode 3 and the substrate with the interlayer dielectric 5, when a conductive film for the lower electrode is deposited on the substrate and patterned by etching, there is not the fear that etching residue at the step caused by a conventional manufacturing method may be caused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a conductor-insulating film-conductor (MIM).
The present invention relates to a semiconductor device equipped with a capacitive element having a die structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the performance of semiconductor integrated circuits has been remarkably improved. Among them, in order to advance the development of high frequency integrated circuits such as monolithic microwave integrated circuits (MMICs) for satellite broadcasting and mobile phones. Therefore, a large-capacity and high-precision capacitance element is required.

As a capacitive element incorporated in an integrated circuit, a dielectric oxide (for example, Si
A MOS-type capacitive element in which a conductor member (for example, polysilicon) is provided as an upper electrode with O ₂ ) interposed, and a dielectric nitride (for example, Si ₃ N ₄ ) interposed on a semiconductor substrate to be a lower electrode; An MNS-type capacitance element provided with a conductor member (for example, polysilicon) as an electrode, and a MIM (Metal Insulator Metal) type in which a capacitance-forming dielectric film is interposed between both electrodes using a conductor member as a lower electrode and an upper electrode. There is a capacitance element and the like. Generally, among these capacitive elements,
The values of the parasitic resistance and the parasitic capacitance of the MIM type capacitance element are lower than those of the MOS type capacitance element and the MNS type capacitance element. Therefore, in the MIM-type capacitance element, it is possible to obtain higher accuracy than in the MOS-type capacitance element and the MNS-type capacitance element.

As one of such MIM type capacitive elements, there is one disclosed in Japanese Patent Application Laid-Open No. 8-3066862. FIGS. 4A to 4E are cross-sectional views illustrating a process for manufacturing a semiconductor device having a conventional MIM-type capacitance element.

First, in a step shown in FIG. 4A, a first conductor film is deposited on an insulating film 102 deposited on an upper surface of a semiconductor substrate 101. Then, the first conductor film is patterned to form the lower electrode film 112 and the first wiring layer 104 of the MIM-type capacitance element.

Next, in a step shown in FIG. 4B, after a dielectric 111 is deposited on the substrate, a second conductor film 116 is deposited on the upper surface of the dielectric 111. Thereafter, in the step shown in FIG. 4C, the second conductor film 116 is patterned by anisotropic dry etching to form the upper electrode 113.

Further, in a step shown in FIG. 4D, an interlayer insulating film 5 is deposited on the substrate, and the lower electrode 1 is formed on the interlayer insulating film 5.
Holes 117a reaching the upper electrode 113 and holes 117a reaching the upper electrode 113 are formed by dry etching. Then, in the step shown in FIG.
2 and a lead wiring 118b extending from the hole 117b reaching the upper electrode 113 onto the interlayer insulating film 105, respectively. As a result, an MIM type capacitor is formed.

When the above-described method is used, the formation of the MIM-type capacitance element can be realized by forming a semiconductor element such as a transistor and then adding a few steps to an ordinary multilayer wiring process. For this reason, the MIM type capacitance element has the advantages of high design flexibility and low manufacturing cost.

[0009]

However, the conventional method for manufacturing a semiconductor device has the following disadvantages.

In the above conventional method, the semiconductor substrate 101
And a dielectric film 111 and a conductor film 116 on the substrate where a step is formed between the lower electrode 112 and the first wiring layer 104 formed on the semiconductor substrate 101, as shown in FIG.
Is deposited in the process shown in FIG. Then, in order to form the upper electrode 113, the conductor film 116 is patterned by anisotropic dry etching as shown in FIG. 4C. At this time, an etching residue 119 is generated at the step. If a post-process such as an ashing process or a cleaning process is performed in a state where the etching residue 119 adheres to the step portion, pattern defects and a reduction in yield due to peeling of the etching residue are likely to occur. In particular, when the first wiring layer 104 is formed with the minimum design rule size in the fine wiring process, a large number of etching residues 119 are generated, and pattern defects or stray capacitance between wirings are generated. May cause. On the other hand, in order to completely remove the etching residue 119,
If the overetching is performed during the anisotropic dry etching of the conductor film 116, the dielectric film 11 under the conductor film 116
1 is etched, and since the thickness of the dielectric film 111 is small, the lower electrode 112 and the first wiring layer 104 below the dielectric film are also etched.

In the above conventional method, the dielectric film 11
1 and the upper electrode 113 are formed on the substrate, the interlayer insulating film 105 is formed, and then the hole 1 for forming the lead-out wiring of the upper electrode 113 in the interlayer insulating film 105 is formed.
When 17b is formed by dry etching, charge-up damage to the dielectric film may occur.

Further, in the above conventional method, the dielectric film 1
In the process of flattening 11 by etch-back or CMP, the dielectric film may be damaged, and the reliability of the dielectric film may be degraded.

An object of the present invention is to provide a highly reliable semiconductor device having a capacitance element and a method of manufacturing the same by taking measures for improving the problems caused by the above-described process.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
A lower lead electrode provided on the substrate, an interlayer insulating film covering the lower lead electrode and the substrate, and a conductor material filling holes formed in the interlayer insulating film, and connected to the lower lead electrode A lower electrode provided on the interlayer insulating film and connected to the lower lead-out electrode via the plug; a capacitor forming dielectric film provided on the lower electrode; And an upper electrode provided on the dielectric film.

As a result, the step formed between the lower extraction electrode and the substrate is covered with the interlayer insulating film. Therefore, when the lower electrode is deposited, no etching residue is generated at the step in the conventional method. As a result, it is possible to solve the problem of pattern defects and yield reduction that may be caused by peeling of the etching residue.

In the method of manufacturing a semiconductor device according to the present invention, a step (a) of forming a lower lead electrode on a substrate, an interlayer insulating film covering the lower lead electrode and the substrate are formed, and (B) forming a hole reaching the lower extraction electrode, (c) forming a plug by embedding a conductive material in the hole, and (c) forming the plug on the substrate. Forming a lower electrode connected to the plug, an upper electrode facing the lower electrode, and a dielectric film for capacitance formation interposed between the upper electrode and the lower electrode. .

According to this method, in the step (a), a step formed between the substrate and the lower extraction electrode is
In step (b), it is covered with an interlayer insulating film. Thereafter, in order to form the lower electrode in the step (d), a conductor film for the lower electrode is deposited on the substrate, and the conductor film is patterned by etching. that time,
With the conventional manufacturing method, there is no longer a possibility that an etching residue is generated at a step portion. As a result, it is possible to solve the problem of pattern defects and yield reduction that may be caused by peeling of the etching residue.

In the step (c), a barrier metal layer is formed on the hole and the interlayer insulating film, and the conductor film is deposited on the barrier metal layer. Further, by removing the barrier metal layer until the interlayer insulating film is exposed, it is possible to prevent a chemical reaction that may occur between the insulator forming the wall surface of the hole and the plug.

In the step (c), a barrier metal layer is formed on the hole and the interlayer insulating film, and the conductor film is deposited on the barrier metal layer. It can be removed until the barrier metal layer is exposed. As a result, it is possible to prevent a chemical reaction that may occur between the plug and the insulator forming the wall surface of the hole and the interlayer insulating film. Further, when the plug is formed, the step formed between the plug and the interlayer insulating film can be reduced by leaving the barrier metal layer on the interlayer insulating film. As a result, in step (d), unevenness existing under the capacitor forming dielectric film is reduced, so that a capacitor with high reliability can be formed.

In the step (d), a conductor film and a dielectric film are sequentially deposited, and the conductor film and the dielectric film are patterned to form the lower electrode and the dielectric film for forming a capacitor. By forming the upper electrode on the capacitor forming dielectric film, the process can be simplified.

In the step (d), a conductor film is deposited, and then the lower electrode is formed by patterning the conductor film. Then, a dielectric film is deposited on the substrate, and then the lower electrode is deposited. By forming the upper electrode opposed to the substrate, it is possible to suppress the generation of an etching residue on the side wall of the dielectric film, and further, because the lower electrode and the upper electrode do not come into contact with each other, it is possible to surely eliminate the risk of occurrence of a short circuit. Can be.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

FIGS. 1A to 1E are cross-sectional views showing the steps of manufacturing an MIM type capacitance element according to the first embodiment of the present invention. In the step shown in FIG. 1A, a TiN film (thickness 3) is formed on the insulator film 2 formed on the upper surface of the semiconductor substrate 1.
0 nm) / AlCu film (600 nm thick) / T
iN film (thickness: about 100 nm) / Ti film (thickness: 30 nm)
After depositing a first conductor film made of a laminated film of (about) by sputtering, the first conductor film is patterned by dry etching to form a first lower extraction electrode 3 and a first wiring layer 4.

Here, in FIGS. 1 (a) to 1 (e),
Although the insulator film 2 is drawn so as to have a uniform thickness, the thickness of the insulator film 2 may not be uniform. For example,
The first conductor film may be made of polysilicon, polymetal, polycide, or the like, and the first wiring layer 4 may be used as a gate electrode.
May be a thin gate insulating film below the gate electrode, and a thick element isolating insulating film below the extraction electrode.

Next, in the step shown in FIG. 1B, after an interlayer insulating film 5 is deposited on the substrate, the interlayer insulating film 5 is flattened by etch back using a resist or CMP. Thereafter, holes 6a and 6b that penetrate through the interlayer insulating film 5 and reach the first extraction electrode 3 are formed by forming a resist pattern in the interlayer insulating film 5 and performing dry etching.

Incidentally, the hole 6a is formed in the extraction electrode.
The hole 6b reaches a region located below the lower electrode 12 to be formed later, and the hole 6b reaches a region located below the third wiring layer 14 to be formed later.

Holes 6a and 6 formed in interlayer insulating film 5
A barrier metal layer 7 composed of a laminated film of a TiN film (about 100 nm in thickness) / Ti film (about 30 nm in thickness) is formed on the wall surface by sputtering.
A conductor plug 8 such as W is embedded in a and 6b.

Next, in the step shown in FIG. 1C, a second conductor film 9 is deposited on the substrate by sputtering, and a dielectric film 10 is subsequently deposited by plasma CVD or the like. At this time,
As the conductor film 9, a TiN film (about 100 nm in thickness) or the like is used, and as the dielectric film 10, a plasma nitride film (about 100 nm in thickness) or a plasma TEOS film (60 nm in thickness) is used.
Degree) can be used. The conductor film may be a conductive material, and the dielectric film may be any as long as it functions as a capacitance film. Even if the film type and the film thickness are changed, no problem occurs.

Next, in the step shown in FIG. 1D, the dielectric film 11 for capacitance formation is etched by using a Cl ₂ -based gas so as to leave the capacitance formation region in the dielectric film 10.
Is formed, the conductive film 9 is etched using a CF ₄ gas to form the lower electrode 12 sequentially. still,
Etching of the dielectric film 10 and the conductor film 9 is performed using the same resist mask.

Thereafter, in the step shown in FIG.
Film (about 30 nm thick) / AlCu film (600 nm thick)
) / Third conductor film composed of a stacked layer of Ti film (about 50 nm thick) is deposited by sputtering to form an upper electrode 13, a second lower lead electrode 14, and a second wiring layer (not shown). I do. At this time, the upper electrode 13
Is formed on the region of the dielectric film 11 for capacitance formation except for the edge, thereby forming the lower electrode 12 and the upper electrode 13.
Can be avoided to cause a short circuit.

The formation of a hole (not shown) from the first wiring layer 4 to the second wiring layer, the formation of a barrier metal layer on the wall surface of the hole, and the embedding of a conductor plug include:
This is performed simultaneously with the formation of the holes 6a and 6b, the barrier metal layer 7, and the conductor plug 8 in the step shown in FIG.

According to the above-described manufacturing method, the MIM including the upper electrode 13, the capacitor forming dielectric film 11, and the lower electrode 12 is formed.
A type capacitance element can be obtained.

In the conventional manufacturing method, in the step shown in FIG. 4B, a step is formed between the lower electrode 112 and the first wiring layer 104 and the insulating film 102 serving as a substrate, and a dielectric for forming a capacitor is formed. Since the body film 111 and the conductor film 116 are deposited and then the conductor film 116 is etched, an etching residue of the conductor film 116 is generated at the first step.

On the other hand, in the present embodiment, FIG.
In the process shown in FIG. 5, the lower lead electrode 3 and the first wiring layer 4
Is formed, an interlayer insulating film 5 is deposited. In the step shown in FIG. 1C, since the conductor film 9 is deposited on the interlayer insulating film 5 without any step, the conductor film 9 which is formed by a conventional method is formed.
No etching residue is generated. Therefore, in the present embodiment, the problems of pattern defects and yield reduction that may occur due to the removal of the etching residue are solved.

Further, since the first wiring layer 4 is formed with the minimum design rule size in the fine wiring process, in the conventional manufacturing method, particularly a large amount of etching residue is generated, and pattern defects or stray capacitance between wirings are reduced. Although such a problem may occur, the present embodiment can prevent such a problem.

According to the manufacturing method of the present invention, the third electrode serving as the upper electrode 13 is formed with a step between the lower electrode 12 and the capacitor forming dielectric film 11 and the interlayer insulating film 5 serving as a substrate. Since the conductive film is deposited, an etching residue of the third conductive film may be generated in the stepped portion. However, the lower electrode 12 and the capacitor forming dielectric film 1
1 is thin, and the height of the second step is about 1/3 of the height of the step generated in the conventional manufacturing method. Therefore, the amount of the etching residue generated in the portion having the step Is much less than the amount of residue in conventional methods.
In addition, since the base of the step is the interlayer insulating film 5, when forming the upper electrode 13 by etching, no problem occurs even if overetching is performed to such an extent that etching residues generated on the step are completely removed.

Further, the interlayer insulating film 5 is flattened and holes 6 are formed.
In the process of forming a and 6b, the base is relatively damaged by etching. However, in the present embodiment, in the process of flattening the interlayer insulating film 5 and the process of forming the holes 6a and 6b, the dielectric film 11 for capacitance formation is formed. Since this is a step prior to the above step, a large charge-up damage is not applied to the capacitor forming dielectric film 11, and a highly reliable capacitor element can be obtained.

In the present embodiment, the dielectric film 10 and the conductor film 9 are patterned using the same resist mask.
After the dielectric film 11 for capacitance formation is formed by etching the dielectric film 10 using a Cl ₂ -based gas, the lower electrode 12 is sequentially formed by etching the conductor film 9 using a CF ₄ -based gas. . However, when TiN is used as the conductor film 9, fluorine contained in the CF ₄ -based gas used when etching the dielectric film 10 is adsorbed on the surface of the TiN of the conductor film 9 and is exposed to the atmosphere to form a fluoride. There is also the disadvantage of doing so. As a method of avoiding this disadvantage, a method of simultaneously etching the dielectric film 10 and the conductive film 9 using a Cl ₂ -based etching gas for processing the conductive film 9 is effective. , Pressure: 12 mtorr, BF power: 525 W (upper electrode) / 175 W (lower electrode), BCl ₃ : 20 ml
/ Min, Cl ₂ : 55 ml / min, lower electrode AlS
The selectivity between iCu and the dielectric film plasma nitride film is about 3.6. Under the above conditions, it is sufficiently possible to process a thin dielectric film of about 100 nm, and it is possible to minimize the number of steps by using the same mask.

(Second Embodiment) Hereinafter, a method for manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (d).

FIGS. 2A to 2D are cross-sectional views showing the steps of manufacturing the MIM type capacitance element according to the second embodiment of the present invention.

In the first embodiment, the holes 6a and 6b are formed in the interlayer insulating film 5 (SiO ₂ ) in the step shown in FIG.
b, depositing a barrier metal film 7 (TiN film) on the substrate, and then embedding a conductor plug 8 such as W (hereinafter, a series of steps from the formation of a hole to the embedding of the conductor plug will be described. Process).
Etch back is performed until the interlayer insulating film 5 is exposed. By performing the etch back in this manner, holes 6a and 6b
The barrier metal layer remains only on the wall surface of.

On the other hand, in the present embodiment, FIG.
When performing etch back in the buried formation process shown in
The etch-back is terminated without etching back until the interlayer insulating film 5 is exposed, but with the barrier metal layer 7 remaining on the upper surface. This is a technique often used in the planarization process, and using this technique in the present embodiment has the advantage that there is no problem of TiN particles.

If there are large irregularities on the base surface of the dielectric film 10, the dielectric film 10 is adversely affected, and the reliability of the dielectric film 10 deteriorates. As described above, in the method of the second embodiment, since the barrier metal film 7 remains on the base, the step generated between the conductor plug 8 and the base is smaller than in the method of the first embodiment. As a result, the irregularities on the base surface are reduced. As a result, a highly reliable capacitor can be formed.

In the step shown in FIG. 2B, after a conductor film 9 for a lower electrode is deposited on the barrier metal layer 7 and the conductor plug 8 left on the interlayer insulating film 5, the conductor film 9 is deposited on the conductor film 9. A dielectric film 10 is deposited.

Then, in the step shown in FIG. 2C, a resist pattern is formed using the same mask in the same manner as in the first embodiment, and then the dielectric film is formed by dry etching using the resist pattern. 10 and conductive film 9
And the barrier metal layer 7 are patterned to form a capacitance forming dielectric film 11, a lower electrode 12, and a barrier metal layer 20.
Are sequentially formed. Here, if both the barrier metal layer 20 and the lower electrode 12 are made of TiN, the lower electrode 12
However, the number of steps does not increase only by increasing the substantial film thickness.

Thereafter, in the step shown in FIG. 2D, the upper electrode 13 and the second electrode 13 are formed in the same manner as in the first embodiment.
Is formed.

In the method of manufacturing a semiconductor device according to the present embodiment, the etching is stopped while the barrier metal film 7 is left on the interlayer insulating film 5 in the buried forming step shown in FIG. Since the step between the base 8 and the base is smaller than the step in the first embodiment, a highly reliable capacitive element can be formed.

(Third Embodiment) Hereinafter, a method of manufacturing a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.
This will be described with reference to (a) to (c).

FIGS. 3A to 3C are cross-sectional views showing the steps of manufacturing the MIM type capacitance element according to the third embodiment of the present invention.

In the present embodiment, in the step shown in FIG. 3A, the formation of a hole in the interlayer insulating film 5, the formation of a barrier metal layer on the hole wall surface, and the embedding of a conductor plug are performed in the first embodiment. After performing the same operation as in the embodiment, the lower electrode 12 is formed on the upper surface of the substrate.

Next, in the step shown in FIG. 3B, a capacitor forming dielectric film 11 is deposited on the substrate including the lower electrode 12 by plasma CVD or the like, and an opening 15 is formed in the capacitor forming dielectric film 11. To form The opening 15 is formed at a position where the hole 6b is exposed, and it is better that the opening 15 has a margin with respect to the hole 6b.

Then, in the step shown in FIG. 3C, the upper electrode 13 facing the lower electrode 12 is formed on the dielectric film 11 for forming the capacitor, and at the same time, the second lower extraction electrode 14 filling the opening 15 is formed. To form At this time, it is preferable that the dimension of the second lower extraction electrode 14 has a margin with respect to the opening 15.

In the step shown in FIG. 3A, after the conductor film for the lower electrode is deposited, only the lower electrode 12 is subsequently formed. Even if the conductor film is left in the portion where the hole is formed, no problem occurs.

In the method of manufacturing a semiconductor device according to the present embodiment, when depositing a dielectric film, a step is formed on the lower electrode 12.
Since only the step between the substrate and the base exists, almost no etching residue is generated on the side wall of the dielectric film.

Further, since the upper surface and the side surfaces of the lower electrode 12 are covered with the dielectric film 11 for forming the capacitance, the lower electrode 12 and the upper electrode 13 do not come into contact with each other due to misalignment of the mask. It is not necessary to consider the margin between the lower electrode 12 and the upper electrode 13 when designing the mask because there is no risk of occurrence.

This method can be applied to the second embodiment.

In each of the above embodiments, the lower electrode 12 and the first
Is formed of a metal material, but the plug 8 is formed of a conductive material other than metal.
May be configured. Further, the barrier metal layer 7 is not necessarily required.

[0058]

According to the present invention, the step formed between the lower extraction electrode and the substrate is covered with the interlayer insulating film. Therefore, when the lower electrode is deposited, the etching residue generated at the step in the conventional method is reduced. Does not occur. As a result, it is possible to solve the problem of pattern defects and yield reduction that may be caused by peeling of the etching residue.

[Brief description of the drawings]

FIGS. 1A to 1E are cross-sectional views illustrating a manufacturing process of an MIM-type capacitance element according to a first embodiment of the present invention.

FIGS. 2A to 2D are cross-sectional views illustrating a process of manufacturing an MIM-type capacitance element according to a second embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views illustrating a process of manufacturing an MIM-type capacitance element according to a third embodiment of the present invention.

FIGS. 4A to 4E are cross-sectional views illustrating a process for manufacturing a conventional MIM-type capacitive element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulating film 3 1st lower extraction electrode 4 1st wiring layer 5 Interlayer insulating film 6a, 6b Hole 7 Barrier metal layer 8 Conductor plug 9 Conductor film for lower electrodes 10 Dielectric for dielectric film for capacity formation Body film 11 Dielectric film for capacitance formation 12 Lower electrode 13 Upper electrode 14 Second lower extraction electrode 15 Opening window for second lower extraction electrode 19 Etching residue of conductive film 20 Barrier metal film

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) EZ15 EZ20

Claims (6)

[Claims] A lower lead electrode provided on a substrate, an interlayer insulating film covering the lower lead electrode and the substrate, and a conductive material filling holes formed in the interlayer insulating film; A plug connected to the lower extraction electrode; a lower electrode provided on the interlayer insulating film and connected to the lower extraction electrode via the plug; a dielectric film provided on the lower electrode; A semiconductor device comprising: an upper electrode provided on a body film. 2. A step (a) of forming a lower extraction electrode on a substrate, and forming an interlayer insulating film covering the lower extraction electrode and the substrate, and then reaching the lower extraction electrode on the interlayer insulating film. (B) forming a hole to be formed, (c) forming a plug by burying a conductive material in the hole, and after the step (c), a lower electrode connected to the plug is formed on a substrate. And (d) forming an upper electrode facing the lower electrode and a capacitor forming dielectric film interposed between the upper electrode and the lower electrode. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (c), a step of forming a barrier metal layer on the hole and the interlayer insulating film; A method for manufacturing a semiconductor device, comprising: depositing a conductive film; and removing a conductive film and a barrier metal layer by planarization until the interlayer insulating film is exposed. 4. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (c), a step of forming a barrier metal layer on the hole and the interlayer insulating film, and a step of forming a conductive film on the barrier metal layer And a step of removing the conductor film by a planarization process until the barrier metal layer is exposed. 5. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (d), a conductor film and a dielectric film are sequentially deposited, and the conductor film and the dielectric film are patterned to form a lower electrode. And a step of forming an upper electrode on the capacitor forming dielectric film after forming the capacitor forming dielectric film. 6. The method for manufacturing a semiconductor device according to claim 2, wherein in the step (d), a lower electrode is formed by depositing a conductive film and subsequently patterning the conductive film, and then forming the lower electrode on the substrate. A method for manufacturing a semiconductor device, comprising a step of depositing a dielectric film and subsequently forming an upper electrode facing the lower electrode.