JP2015103724A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2015103724A
JP2015103724A JP2013244620A JP2013244620A JP2015103724A JP 2015103724 A JP2015103724 A JP 2015103724A JP 2013244620 A JP2013244620 A JP 2013244620A JP 2013244620 A JP2013244620 A JP 2013244620A JP 2015103724 A JP2015103724 A JP 2015103724A
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forming
film
semiconductor device
mim capacitor
insulating film
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喜之 小川
Yoshiyuki Ogawa
喜之 小川
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三菱電機株式会社
Mitsubishi Electric Corp
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Abstract

PROBLEM TO BE SOLVED: To obtain a manufacturing method of a semiconductor device which enables a high quality MIM capacitor to be obtained while preventing residues.SOLUTION: An active element 2 is formed on a semiconductor substrate 1. A resin film 4 covering the active element 2 is formed. After the resin film 4 is formed, a base metal film 6 and an insulator film 7 are sequentially formed on an entire surface of the semiconductor substrate 1. An upper metal pattern 8 is formed on the insulator film 7. After the upper metal pattern 8 is formed, the base metal film 6 and the insulator film 7 are patterned to form an MIM capacitor 10.

Description

本発明は、1つの半導体基板上に能動素子とMIM(Metal-Insulator-Metal)キャパシタを集積したMMIC(Monolithic Microwave Integrated Circuit)の製造方法に関する。 The present invention relates to a process for the preparation of the active element and MIM on a single semiconductor substrate (Metal-Insulator-Metal) MMIC integrated capacitor (Monolithic Microwave Integrated Circuit).

MIMキャパシタを形成する際にリフトオフを用いずに下地金属膜と絶縁膜を連続して形成することで、高品質のMIMキャパシタを得ることができる(例えば、特許文献1,2参照)。 By continuously forming a base metal film and the insulating film without using a lift-off in forming the MIM capacitor, it is possible to obtain a high quality of the MIM capacitor (e.g., see Patent Documents 1 and 2). この製造方法をMMICに適用する場合、能動素子とMIMキャパシタのどちらを先に形成するかで2通りの方法がある。 When applying this manufacturing method in MMIC, there are two ways in either form either of an active device and the MIM capacitor first.

特開平10−65110号公報 JP-10-65110 discloses 米国特許第3889476号明細書 US Pat. No. 3889476

能動素子を先に形成する場合、MIMキャパシタの下地金属膜と絶縁膜は基板上の全面に形成されるため、能動素子がそれらで覆われる。 When forming the active element above, the base metal film and the insulating film of the MIM capacitor is to be formed on the entire surface of the substrate, an active element is covered with them. 実際の能動素子は逆テーパーのメサ形状やタブ形状、庇状の電極や絶縁膜やエピタキシャル層を有していて、陰になる部分が生じる。 The actual active element of the reverse tapered mesa shape or tab shape, have an overhanging portion of the electrode and the insulating film and the epitaxial layer, areas of shade occurs. このため、MIMキャパシタ形成の最後に不要な下地金属膜と絶縁膜を除去する工程で、能動素子の陰になる部分に下地金属膜又は絶縁膜が残渣として残る。 Therefore, in the process of removing the last unnecessary underlying metal film and the insulating film of the MIM capacitor formation, the portion to be behind the active element underlying metal film or an insulating film is left as a residue. この残渣は、電気的特性上の寄生成分となり高周波特性を劣化させる要因となる。 This residue is a factor that degrades the high frequency characteristics become parasitic components on the electrical characteristics.

MIMキャパシタを先に形成する場合、能動素子が形成される場所は平面のままであるため、残渣を残すことなく不要な金属膜と絶縁膜を除去できる。 When forming the MIM capacitor earlier, where the active element is formed for remains planar, thereby removing the unnecessary metal film and the insulating film without leaving a residue. しかし、MIMキャパシタによって生じた凹凸が、能動素子形成工程のレジスト塗布ムラの要因となり、パターン寸法バラツキの悪化やレイアウトの配置制約が生じる。 However, irregularities caused by the MIM capacitor, be a factor of the resist coating unevenness of the active element formation step, deterioration or layout placement constraints of pattern dimension variations occur. これを回避するために予めMIMキャパシタを形成する場所を掘り込む方法もあるが、掘り込み部分側壁が逆テーパーとなる方位では金属膜や絶縁膜が除去しきれずに残渣となってしまう。 There is also a method of recessing where to preformed MIM capacitor in order to avoid this, but orientation partial sidewall digging is reversed taper becomes residue not completely removed the metal film or an insulating film. さらに工程が複雑となり、工数が多くなる。 Further, in the step it is complicated, and many man-hours.

本発明は、上述のような課題を解決するためになされたもので、その目的は残渣を防ぎつつ、高品質のMIMキャパシタを得ることができる半導体装置の製造方法を得るものである。 The present invention has been made to solve the above problems, and an object while preventing residue and to obtain a method of manufacturing a semiconductor device capable of obtaining high-quality of the MIM capacitor.

本発明に係る半導体装置の製造方法は、半導体基板上に能動素子を形成する工程と、前記能動素子を覆う樹脂膜を形成する工程と、前記樹脂膜を形成した後に、前記半導体基板上の全面に下地金属膜と絶縁膜を順に連続して形成する工程と、前記絶縁膜上に上地金属パターンを形成する工程と、前記上地金属パターンを形成した後に、前記下地金属膜と前記絶縁膜をパターニングしてMIMキャパシタを形成する工程とを備えることを特徴とする。 The method of manufacturing a semiconductor device according to the present invention includes the steps of forming an active element on a semiconductor substrate, forming a resin film covering the active element, after formation of the resin film, the entire surface on said semiconductor substrate forming continuously a base metal film and an insulating film sequentially, said forming a front cloth metal pattern on the insulating film, after forming the upper base metal pattern, the underlying metal layer and the insulating film patterning the characterized in that it comprises a step of forming a MIM capacitor.

本発明では、MIMキャパシタの形成前に能動素子を樹脂膜で覆って平坦化することで、後の下地金属膜と絶縁膜の除去工程において陰になる部分が無くなるため、残渣を防ぐことができる。 In the present invention, the active element before the formation of the MIM capacitor by flattening covered with a resin film, since the underlying metal film to be a shadow portion in the step of removing the insulating film after disappears, it is possible to prevent the residue . また、下地金属膜と絶縁膜を連続して形成するため、高品質のMIMキャパシタを得ることができる。 Further, in order to form continuous metal seed layer and the insulating film, it is possible to obtain a high quality of the MIM capacitor.

本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a first embodiment of the present invention is a cross-sectional view illustrating. 比較例1に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to Comparative Example 1 is a sectional view showing a. 比較例2に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to Comparative Example 2 is a sectional view showing a. 本発明の実施の形態2に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a second embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態3に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a third embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態4に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a fourth embodiment of the present invention is a cross-sectional view illustrating. 本発明の実施の形態5に係る半導体装置の製造方法を示す断面図である。 The method of manufacturing a semiconductor device according to a fifth embodiment of the present invention is a cross-sectional view illustrating.

本発明の実施の形態に係る半導体装置の製造方法について図面を参照して説明する。 Will be described with reference to the drawings a method of manufacturing a semiconductor device according to the embodiment of the present invention. 同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。 The same or corresponding components are designated by the same reference numerals, it may be omitted and the repeated description.

実施の形態1. The first embodiment.
図1から図9は、本発明の実施の形態1に係る半導体装置の製造方法を示す断面図である。 FIGS. 1-9 are cross-sectional views showing a manufacturing method of a semiconductor device according to a first embodiment of the present invention. まず、図1に示すように、半導体基板1上に能動素子2を形成する。 First, as shown in FIG. 1, forming an active element 2 on a semiconductor substrate 1. 能動素子2を覆う保護膜3を半導体基板1上の全面に形成する。 Forming a protective film 3 that covers the active element 2 over the entire surface of the semiconductor substrate 1.

次に、図2に示すように、能動素子2を覆う感光性の樹脂膜4を半導体基板1上の全面に形成する。 Next, as shown in FIG. 2, to form a photosensitive resin film 4 covering the active element 2 over the entire surface of the semiconductor substrate 1. 次に、図3に示すように、能動素子2以外の領域において樹脂膜4の一部を露光と現像によって除去して開口部5を形成する。 Next, as shown in FIG. 3, in a region other than the active device 2 a portion of the resin film 4 is removed by exposure and development to form an opening 5.

次に、図4に示すように、半導体基板1上の全面に下地金属膜6と絶縁膜7を順に連続して形成する。 Next, as shown in FIG. 4, a base metal film 6 and the insulating film 7 is formed continuously in this order on the entire surface of the semiconductor substrate 1. 下地金属膜6はスパッタにより形成する。 Underlying metal film 6 is formed by sputtering. 次に、図5に示すように、開口部5内において絶縁膜7上に上地金属パターン8を転写とリフトオフによって形成する。 Next, as shown in FIG. 5, the upper base metal pattern 8 on the insulating film 7 in the opening 5 is formed by the transfer and lift-off. 次に、図6に示すように、MIM領域を決めるフォトレジスト9を転写で形成する。 Next, as shown in FIG. 6, formed by transferring the photoresist 9 which determines the MIM area.

次に、図7に示すように、フォトレジスト9をマスクとして不要な絶縁膜7をドライエッチングで、不要な下地金属膜6をイオンミリングで除去する。 Next, as shown in FIG. 7, an unnecessary insulating film 7 using the photoresist 9 as a mask by dry etching, to remove unnecessary underlying metal film 6 by ion milling. このように下地金属膜6と絶縁膜7をパターニングしてMIMキャパシタ10を形成する。 Thus forming a MIM capacitor 10 by patterning the underlying metal film 6 and the insulating film 7.

最後に、図8に示すように、残っている樹脂膜4をアッシャで除去する。 Finally, as shown in FIG. 8, the remaining resin film 4 is removed by ashing. これにより、図9に示すように、能動素子2とMIMキャパシタ10が形成される。 Thus, as shown in FIG. 9, the active element 2 and the MIM capacitor 10 is formed. その後、コンタクトホール加工、真空蒸着による配線形成、メッキによる配線形成などを経て、各回路構成要素を結線してMMICが製造される。 Thereafter, a contact hole processing, wiring formed by vacuum deposition, through such wiring formation by plating, MMIC is fabricated by connecting the respective circuit components.

続いて本実施の形態の効果を比較例1,2と比較して説明する。 Next will be described in comparison with the effects of the present embodiment and Comparative Examples 1 and 2. 図10は、比較例1に係る半導体装置の製造方法を示す断面図である。 Figure 10 is a cross-sectional view showing a manufacturing method of a semiconductor device according to Comparative Example 1. 比較例1では能動素子2を覆う樹脂膜4が無い。 Comparative Example 1 In the resin film 4 covering the active element 2 is no. 能動素子2は逆テーパー形状の陰になる部分を有するため、この部分に下地金属膜6又は絶縁膜7が残渣として残る。 Since the active element 2 having a portion to be behind the reverse tapered, this portion underlying metal film 6 or the insulating film 7 is left as a residue.

図11は、比較例2に係る半導体装置の製造方法を示す断面図である。 Figure 11 is a cross-sectional view showing a manufacturing method of a semiconductor device according to Comparative Example 2. 比較例2はMIMキャパシタ10を先に形成するが、能動素子2の形成工程のレジスト塗布ムラ等を回避するために予めMIMキャパシタ10を形成する場所を掘り込む。 Comparative Example 2 forms a MIM capacitor 10 on the first, but digging where to form the pre MIM capacitor 10 in order to avoid resist coating unevenness of formation of the active element 2 steps. しかし、掘り込み部分側壁が逆テーパーとなる方位では下地金属膜6又は絶縁膜7が除去しきれずに残渣となってしまう。 However, in the orientation as a partial sidewall digging reverse taper it becomes residue not completely base metal film 6 or the insulating film 7 is removed. さらに工程が複雑となり、工数が多くなる。 Further, in the step it is complicated, and many man-hours.

これに対して、本実施の形態では、MIMキャパシタ10の形成前に能動素子2を樹脂膜4で覆って平坦化することで、後の下地金属膜6と絶縁膜7の除去工程において陰になる部分が無くなるため、残渣を防ぐことができる。 In contrast, in the present embodiment, the active element 2 before formation of the MIM capacitor 10 by flattening covered with a resin film 4, a base metal film 6 after the shade in the step of removing the insulating film 7 to become part is eliminated, it is possible to prevent a residue. なお、開口部5において樹脂膜4の段差が生じるが、露光後パターンのプロファイルが順テーパーとなる感光性ポリイミドのような樹脂膜4を用いることで陰になる部分の発生を防ぐことができる。 Although the step of the resin film 4 is produced at the opening 5, it is possible to profile the post-exposure pattern is prevented from occurring using the resin film 4 becomes negative at a portion such as a photosensitive polyimide comprising a forward tapered.

また、リフトオフを挟まずに下地金属膜6と絶縁膜7を連続して形成するため、高品質のMIMキャパシタ10を得ることができる。 Further, in order to form a base metal film 6 and the insulating film 7 without interposing liftoff continuously, it is possible to obtain a MIM capacitor 10 of high quality. また、残っている樹脂膜4をアッシャで除去することで、樹脂膜4が能動素子2の寄生容量となるのを防ぐことができる。 Further, the remaining resin film 4 by removing at ashing, can the resin film 4 is prevented from becoming parasitic capacitance of the active element 2.

なお、本実施の形態はMIMキャパシタを有するMMIC全般に適用可能である。 Note that this embodiment is applicable to MMIC general having MIM capacitor. 半導体基板1の材料はGaAs,GaN,InP等の全てが対象である。 Material of the semiconductor substrate 1 is GaAs, GaN, all such as InP is subject. 能動素子2はバイポーラトランジスタ,FET,pn接合ダイオード,ショットキーバリアダイオード等の全てが対象である。 Active element 2 is a bipolar transistor, FET, pn junction diodes, all such Schottky barrier diode is subject.

実施の形態2. The second embodiment.
図12は、本発明の実施の形態2に係る半導体装置の製造方法を示す断面図である。 Figure 12 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a second embodiment of the present invention. 実施の形態1の工程に加えて、絶縁膜7を形成した後に、半導体基板1上の全面に中間金属膜11と中間絶縁膜12を順に連続して形成する。 In addition to the steps of the first embodiment, after forming the insulating film 7, to form an intermediate metal film 11 and the intermediate insulating film 12 in succession in this order on the entire surface of the semiconductor substrate 1. 中間絶縁膜12上に上地金属パターン8を形成する。 On the intermediate insulating film 12 to form the upper base metal pattern 8. 下地金属膜6と絶縁膜7と中間金属膜11と中間絶縁膜12をパターニングしてMIMキャパシタ10として積層MIMキャパシタを形成する。 Patterning the underlying metal film 6 and the insulating film 7 and the intermediate metal layer 11 and the intermediate insulating film 12 to form a laminated MIM capacitor as a MIM capacitor 10. これによりMIMキャパシタ10の容量値の高集積化も可能になる。 Thereby higher integration of the capacitance value of the MIM capacitor 10 is also made possible.

実施の形態3. Embodiment 3.
図13は、本発明の実施の形態3に係る半導体装置の製造方法を示す断面図である。 Figure 13 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a third embodiment of the present invention. MIMキャパシタ10が形成される領域の樹脂膜4を露光で除去しないで残しておき、その樹脂膜4上にMIMキャパシタ10を形成する。 Leave without the resin film 4 in the region where the MIM capacitor 10 is formed is removed by exposure to form a MIM capacitor 10 on the resin film 4. このMIMキャパシタ10の下方の樹脂膜4を除去せずに残す。 Leaving the resin film 4 below the MIM capacitor 10 without removing. これにより、MIMキャパシタ10が樹脂膜4で平坦化された面上に形成されるので、より異物の影響を受けなくなり、MIMキャパシタ10の信頼性が向上する。 Thus, the MIM capacitor 10 so formed on the planarized surface of a resin film 4, will not undergo more extraneous, reliability of the MIM capacitor 10 is improved. なお、露光を行わない場合は樹脂膜4が感光性である必要はない。 When you do not exposure the resin film 4 need not be photosensitive.

実施の形態4. Embodiment 4.
図14は、本発明の実施の形態4に係る半導体装置の製造方法を示す断面図である。 Figure 14 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a fourth embodiment of the present invention. MIMキャパシタ10を形成した後に樹脂膜4を除去せずに残す。 Leave without removing the resin film 4 after the formation of the MIM capacitor 10. この場合も樹脂膜4は感光性である必要はない。 This is not necessary resin film 4 are photosensitive case. 下地金属膜6のコンタクト部分又はMIMキャパシタ10そのものを樹脂膜4上に形成して樹脂膜4下の構造物と積層することができるので、MMICを高集積化できる。 Since the contact portion or MIM capacitor 10 itself underlying metal film 6 can be formed on the resin film 4 is laminated with the resin film 4 underneath the structure, can be highly integrated MMIC.

実施の形態5. Embodiment 5.
図15は、本発明の実施の形態5に係る半導体装置の製造方法を示す断面図である。 Figure 15 is a cross-sectional view showing a manufacturing method of a semiconductor device according to a fifth embodiment of the present invention. 下地金属膜6をメッキ給電層として用いてメッキ配線13を形成する。 Forming a plated wiring 13 using a base metal film 6 as a plating power feeding layer. これにより、MIMキャパシタ10形成後にメッキ給電層とメッキ配線を別途形成する場合に比べて、工程を省略することができる。 Thus, compared to the case of separately forming the plating power feeding layer and the plating wiring after the MIM capacitor 10 formed to omit the step.

なお、上記の実施の形態では下地金属膜6をスパッタで形成したが、これに限らず下地金属膜6を真空蒸着で形成してもよい。 Incidentally, in the above embodiment has formed the base metal film 6 by sputtering, a base metal film 6 may be formed by vacuum deposition is not limited thereto. これにより下地金属膜6を容易に厚くすることができるため、MIMキャパシタ10の抵抗成分が軽減され、高周波での信号損失が改善される。 Since this makes it possible to easily increase the base metal film 6, it is reduced the resistance component of the MIM capacitor 10, signal loss at high frequencies is improved.

1 半導体基板、2 能動素子、4 樹脂膜、5 開口部、6 下地金属膜、7 絶縁膜、8 上地金属パターン、10 MIMキャパシタ、11 中間金属膜、12 中間絶縁膜、13 メッキ配線 1 semiconductor substrate, 2 the active element, 4 a resin film, 5 opening 6 underlying metal film, 7 insulating film, 8 upper base metal pattern, 10 MIM capacitor, 11 an intermediate metal film, 12 an intermediate insulating film, 13 plated wiring

Claims (7)

  1. 半導体基板上に能動素子を形成する工程と、 Forming an active element on a semiconductor substrate,
    前記能動素子を覆う樹脂膜を形成する工程と、 Forming a resin film covering the active element,
    前記樹脂膜を形成した後に、前記半導体基板上の全面に下地金属膜と絶縁膜を順に連続して形成する工程と、 After forming the resin layer, and forming on the entire surface underlying metal film and an insulating film on the semiconductor substrate successively in this order,
    前記絶縁膜上に上地金属パターンを形成する工程と、 Forming a upper base metal pattern on the insulating film,
    前記上地金属パターンを形成した後に、前記下地金属膜と前記絶縁膜をパターニングしてMIMキャパシタを形成する工程とを備えることを特徴とする半導体装置の製造方法。 Wherein after forming the upper base metal pattern, a method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a MIM capacitor by patterning the insulating film and the underlying metal film.
  2. 前記MIMキャパシタを形成した後に前記樹脂膜を除去する工程を更に備えることを特徴とする請求項1に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises further the step of removing the resin film after forming the MIM capacitor.
  3. 前記能動素子以外の領域において前記樹脂膜の一部を除去して開口部を形成する工程を更に備え、 Further comprising a step of forming an opening by removing a portion of the resin film in the region other than the active element,
    前記開口部を形成した後に前記下地金属膜と前記絶縁膜を形成し、 Said underlying metal layer and the insulating film is formed after forming the opening,
    前記開口部内において前記上地金属パターンを形成することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1 or 2, characterized by forming the upper base metal pattern within the opening.
  4. 前記絶縁膜を形成した後に、前記半導体基板上の全面に中間金属膜と中間絶縁膜を順に連続して形成する工程を更に備え、 Wherein after forming the insulating film, further comprising the step of continuously formed over the entire surface of the semiconductor substrate of the intermediate metal film and the intermediate insulating film in this order,
    前記中間絶縁膜上に前記上地金属パターンを形成し、 Wherein forming a upper base metal pattern on the intermediate insulating film,
    前記下地金属膜と前記絶縁膜と前記中間金属膜と前記中間絶縁膜をパターニングして前記MIMキャパシタとして積層MIMキャパシタを形成することを特徴とする請求項1〜3の何れか1項に記載の半導体装置の製造方法。 According to any one of claims 1 to 3, characterized in that to form a laminated MIM capacitor as the MIM capacitor by patterning the intermediate insulating film above the base metal film and the insulating film and the intermediate metal layer the method of manufacturing a semiconductor device.
  5. 前記MIMキャパシタを前記樹脂膜上に形成し、 The MIM capacitor is formed on the resin film,
    前記MIMキャパシタの下方の前記樹脂膜を除去せずに残すことを特徴とする請求項2に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 2, wherein the leaving without removing the resin film below the MIM capacitor.
  6. 前記MIMキャパシタを形成した後に前記樹脂膜を除去せずに残すことを特徴とする請求項1に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, characterized in that to leave without removing the resin film after forming the MIM capacitor.
  7. 前記下地金属膜をメッキ給電層として用いてメッキ配線を形成する工程を更に備えることを特徴とする請求項1〜6の何れか1項に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to any one of claims 1 to 6, further comprising a step of forming a plated wiring by using the underlying metal film as a plating power feeding layer.
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