JP2002343871A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional semiconductor device such as that the periphery of a switching circuit 105 cannot made into small area since wiring is concentrated inevitably in and around the switching circuit 105, and besides the downsizing of a semiconductor chip 100 is limited. SOLUTION: The concentration of wiring in the periphery of the switching circuit is suppressed by equipping the semiconductor device with a plurality of switching circuits which relay each the connection between a pair of pins of a semiconductor chips and a pair of terminals within the semiconductor chip and switching these, being scattered within the semiconductor chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which can be used for both forward bend specifications and reverse bend specifications. The present invention relates to a semiconductor device in which concentration of wiring in a part is suppressed.

[0002]

2. Description of the Related Art In a semiconductor device, in order to omit stub wiring on a board (to prevent linking or reduce a mounting area), it may be necessary to manufacture a forward / reverse bend product. Therefore, there has been proposed a semiconductor device in which a switching circuit is provided in a semiconductor chip and can be switched to a normal bend product or a reverse bend product by switching by the switching circuit.

FIG. 4 is a diagram showing a conventional semiconductor device having a switching circuit for switching between the above-described normal / reverse bend specification. FIG. 4A is a schematic diagram showing the semiconductor device, and FIG. FIG. 3 is a table showing input / output data of each pin group before and after switching. In the figure, reference numeral 100 denotes a semiconductor chip constituting a conventional semiconductor device, and has a switching circuit 105 for switching between forward / reverse bend specifications. 101,1
Reference numerals 02, 103, and 104 denote logic circuits constituting internal circuits provided in the semiconductor chip 100. Reference numeral 105 denotes a switching circuit provided at the center of the semiconductor chip 100, and includes a pin A group, a pin B group, and a pin C according to an external control signal.
Group and each of the pin D groups and the logic circuit 101, 1
The connection with 02, 103, 104 is switched.

Reference numeral 106a denotes an input wiring group from the pin A group.
The pins constituting the group of pins A are electrically connected to the switching circuit 105 to propagate the input signal from the group of pins A. 106b
Is an output wiring group to the pin A group, and electrically connects the pins constituting the pin A group and the switching circuit 105 to propagate an output signal to the pin A group. Reference numeral 107a denotes an input wiring group from the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 105 to propagate an input signal from the pin B group. 1
Reference numeral 07b denotes an output wiring group to the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 105 to propagate an output signal to the pin B group. Reference numeral 108a denotes an input wiring group from the pin C group.
Are electrically connected to each other to propagate an input signal from the pin C group. Reference numeral 108b denotes an output wiring group to the pin C group, which electrically connects the pins constituting the pin C group and the switching circuit 105 to propagate an output signal to the pin C group. Reference numeral 109a denotes an input wiring group from the pin D group, which electrically connects the pins constituting the pin D group and the switching circuit 105 to propagate an input signal from the pin D group. Reference numeral 109b denotes an output wiring group to the pin D group, which electrically connects the pins constituting the pin D group and the switching circuit 105 to propagate an output signal to the pin D group.

Reference numeral 110a denotes a group of input wires to the logic circuit 101, which electrically connects the switching circuit 105 and the logic circuit 101 to each other, and
Propagate the input signal to 110b is the logic circuit 10
The output wiring group from 1 electrically connects the switching circuit 105 and the logic circuit 101 to propagate an output signal from the logic circuit 101 to the switching circuit 105. Reference numeral 111a denotes a group of input wirings to the logic circuit 102, which electrically connects the switching circuit 105 and the logic circuit 102 to each other.
From the input to the logic circuit 102. 1
Reference numeral 11b denotes an output wiring group from the logic circuit 102, which electrically connects the switching circuit 105 and the logic circuit 102 to transmit an output signal from the logic circuit 102 to the switching circuit 105. An input wiring group 112a to the logic circuit 103 electrically connects the switching circuit 105 and the logic circuit 103 to transmit an input signal from the switching circuit 105 to the logic circuit 103. 112b is the logic circuit 103
From the switching circuit 105 and the logic circuit 1
03 is electrically connected to propagate an output signal from the logic circuit 103 to the switching circuit 105. An input wiring group 113a to the logic circuit 104 includes a switching circuit 105
Switching circuit 1 by electrically connecting the logic circuit 104
5 propagates the input signal to the logic circuit 104. Reference numeral 113b denotes an output wiring group from the logic circuit 104, which electrically connects the switching circuit 105 and the logic circuit 104 to transmit an output signal from the logic circuit 104 to the switching circuit 105.

Next, the outline will be described. In the state where MIRROR is off in FIG. 4B, that is, in the normal bend mode, data input / output to / from each pin group is as follows. Switching circuit 105, input / output wiring group 10
The group of pins A and the logic circuit 101 are electrically connected via 6a, 106b, 110a, and 110b. The input / output data in this connection state is indicated by A in FIG. Further, the switching circuit 105, the input / output wiring group 107a, 1
The group of pins B and the logic circuit 102 are electrically connected via 07b, 111a, and 111b. The input / output data in this connection state is indicated by B in FIG. Further, the switching circuit 105, the input / output wiring groups 108a, 108
The group of pins C and the logic circuit 103 are electrically connected via b, 112a, and 112b. The input / output data in this connection state is indicated by C in FIG. further,
Switching circuit 105, input / output wiring groups 109a, 109b, 1
13a, 113b and the logic circuit 10
4 are electrically connected. The input / output data in this connection state is indicated by D in FIG.

At this time, in the state where MIRROR is turned on in FIG. 4B, that is, in the reverse bend mode, the data input / output to / from each pin group is as follows. The switching of the connection relationship by the switching circuit 105 causes the input / output wiring groups 106a, 106b, 111a,
The group of pins A and the logic circuit 102 are electrically connected via 1b. That is, it is switched to the connection target in the pin B group in the normal bend mode. For this reason, in FIG.
When the RROR is turned on, the connection state of the pin A group becomes B. Switching of the connection relationship by the switching circuit 105 causes the input / output wiring groups 107a, 107b, 110
The group of pins B and the logic circuit 101 are electrically connected via a and 110b. That is, it is switched to the connection target in the pin A group in the normal bend mode. For this reason, FIG.
In this case, the connection state of the group of pins B becomes A by turning on MIRROR. Further, by switching the connection relationship by the switching circuit 105, the input / output wiring groups 108a, 108
The group of pins C and the logic circuit 104 are electrically connected via b, 113a, and 113b. That is, it is switched to the connection target in the pin D group in the normal bend mode. For this reason,
In FIG. 4B, when the MIRROR is turned on, the pin C
The connection state of the group becomes D. Further, by switching the connection relationship by the switching circuit 105, the input / output wiring group 109
The group of pins D and the logic circuit 103 are electrically connected via a, 109b, 112a, and 112b. That is, it is switched to the connection target in the pin C group in the normal bend mode.
For this reason, in FIG. 4B, the connection state of the pin D group becomes C by turning on MIRROR.

In summary, in the semiconductor chip 100, the switching circuit 105 is controlled in accordance with an external control signal.
Are the pin groups and the logic circuits 101, 102, 103,
The connection relationship with the mirror 104 is a mirror inversion (FIG. 4B) which is symmetrical with respect to a symmetrical line shown by a broken line in FIG.
MIRROR in). As described above, the semiconductor chip 100 can freely switch between the normal / reverse bend mode.

[0009]

Since the conventional semiconductor device is configured as described above, the wiring is inevitably concentrated around the switching circuit 105. Therefore, the area around the switching circuit 105 must be reduced. Is not possible, and the semiconductor chip 1
There is a problem that miniaturization is limited.

The above-mentioned problem will be specifically described. FIG. 4 (a)
In consideration of the number of wiring groups on the left side with respect to the symmetry axis at the time of mirror inversion, the wiring groups 106a, 106b, 1
08a, 108b, a wiring group 110 which is a horizontal wiring connecting the logic circuits 101, 103 and the switching circuit 105.
a, 110b, 112a, and 112b, there are a total of eight bundles of wiring groups. Here, for example, one wiring group is 10
Assuming that the circuit is composed of two wires, FIG.
A total of 80 wirings are concentrated in the area surrounded by the broken line in the middle.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a plurality of switching circuits are provided to disperse a function of switching wiring, thereby suppressing concentration of wiring in a peripheral portion of the switching circuit. It is an object to obtain a semiconductor device which can be used.

[0012]

A semiconductor device according to the present invention is provided separately in a semiconductor chip, and relays connection between a pair of pins of the semiconductor chip and a pair of terminals in the semiconductor chip. Are provided with a plurality of switching circuits for switching the connection.

[0013] In the semiconductor device according to the present invention, the switching circuit relays connection of a wiring for transmitting an input signal from a pin of the semiconductor chip to a terminal in the semiconductor chip, and an output signal from the terminal to the pin. And an output-only switching circuit that relays the connection of the wiring that propagates the signal.

In a semiconductor device according to the present invention, an output-only switching circuit is arranged near a pin of a semiconductor chip for switching an output destination.

In the semiconductor device according to the present invention, the switching circuit relays a connection of a wiring for inputting and outputting a signal used for all internal circuits in the semiconductor chip, and an individual internal circuit in the semiconductor chip. And a sub-switching circuit that relays connection of wiring for inputting / outputting a signal used only for the sub-switch.

In a semiconductor device according to the present invention, a sub-switching circuit is arranged near a pin of a semiconductor chip for switching an output destination.

In the semiconductor device according to the present invention, the switching circuit relays a connection of a wiring for inputting and outputting a signal used only for each internal circuit in the semiconductor chip, and is arranged near a pin for switching an output destination. It is.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. 1A and 1B are diagrams showing a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a schematic diagram showing the semiconductor device, and FIG. 1B is a diagram showing input / output data of each pin group before and after switching. FIG. In the figure, reference numeral 1 denotes a semiconductor chip constituting the semiconductor device according to the first embodiment, and has switching circuits 6a, 6b, 6c for switching between forward / reverse bend specifications. Reference numerals 2, 3, 4, and 5 denote logic circuits constituting internal circuits provided in the semiconductor chip 1. Reference numeral 6a denotes a switching circuit (input-only switching circuit, which is provided in the center of the semiconductor chip 1 (that is, the logic circuits 2, 3, 4, and 5 are arranged symmetrically with respect to the position of the switching circuit 6a).
A switching circuit), and a wiring group 7a, 8a, 9a, 10a, which is an input signal line of each of a pin A group, a pin B group, a pin C group, and a pin D group, according to an external control signal, and the logic circuit 2 , 3, 4, and 5, the connection to the wiring groups 11a, 12a, 13a, and 14a, which are the input signal lines, is switched. Reference numeral 6b denotes a switching circuit (output-only switching circuit, switching circuit) provided in the vicinity of the pin A group and the pin C group, and mainly outputs the respective output signals of the pin A group and the pin C group in accordance with an external control signal. Wiring groups 7b and 9b, which are lines, and wiring groups 11b and 13b which are output signal lines of the logic circuits 2 and 4, respectively.
Switch the connection with. 6c is a switching circuit provided near the pin B group and the pin D group (output-only switching circuit, switching circuit)
According to a control signal from the outside, the wiring groups 8b, 1 which are mainly output signal lines of the pin B group and the pin D group, respectively.
The connection between Ob and the wiring groups 12b and 14b, which are output signal lines of the logic circuits 3 and 5, is switched.

Reference numeral 7a denotes an input wiring group from the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6a to propagate an input signal from the pin A group. Reference numeral 7b denotes an output wiring group to the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6b to propagate an output signal to the pin A group. Reference numeral 8a denotes an input wiring group from the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 6a to propagate an input signal from the pin B group. Reference numeral 8b denotes an output wiring group to the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 6c to propagate an output signal to the pin B group.
Reference numeral 9a denotes an input wiring group from the pin C group, which electrically connects the pins constituting the pin C group and the switching circuit 6a to propagate an input signal from the pin C group. Reference numeral 9b denotes an output wiring group to the pin C group, which electrically connects the pins constituting the pin C group and the switching circuit 6b to propagate an output signal to the pin C group. 10a
Is an input wiring group from the pin D group, and electrically connects the pins constituting the pin D group and the switching circuit 6a to propagate an input signal from the pin D group. Reference numeral 10b denotes an output wiring group to the pin D group, which electrically connects the pins constituting the pin D group and the switching circuit 6c to propagate an output signal to the pin D group.

Reference numeral 11a denotes an input wiring group to the logic circuit 2, which electrically connects the switching circuit 6a to the logic circuit 2 and propagates an input signal from the switching circuit 6a to the logic circuit 2. Reference numeral 11b denotes an output wiring group from the logic circuit 2, which electrically connects the switching circuit 6b and the logic circuit 2 and propagates an output signal from the logic circuit 2 to the switching circuit 6b. Reference numeral 12a denotes an input wiring group to the logic circuit 3, which electrically connects the switching circuit 6a to the logic circuit 3 and propagates an input signal from the switching circuit 6a to the logic circuit 3. Reference numeral 12b denotes an output wiring group from the logic circuit 3, which electrically connects the switching circuit 6c and the logic circuit 3 to propagate an output signal from the logic circuit 3 to the switching circuit 6c. Reference numeral 13a denotes an input wiring group to the logic circuit 4, which electrically connects the switching circuit 6a to the logic circuit 4 and propagates an input signal from the switching circuit 6a to the logic circuit 4.
Reference numeral 13b denotes an output wiring group from the logic circuit 4, which electrically connects the switching circuit 6b to the logic circuit 4 and propagates an output signal from the logic circuit 4 to the switching circuit 6b.
Reference numeral 14a denotes a group of input wires to the logic circuit 5, and a switching circuit 6a.
a and the logic circuit 5 are electrically connected to each other to form a switching circuit 6a
From the input to the logic circuit 5. 14b
Is an output wiring group from the logic circuit 5, and electrically connects the switching circuit 6c and the logic circuit 5 to propagate an output signal from the logic circuit 5 to the switching circuit 6c.

Next, the outline will be described. In the state where MIRROR is off in FIG. 1B, that is, in the normal bend mode, data input / output to / from each pin group is as follows, for example. The pin A group and the logic circuit 2 are electrically connected via the switching circuits 6a, 6b and the input / output wiring groups 7a, 7b, 11a, 11b. The input / output data in this connection state is indicated by A in FIG. Further, the switching circuits 6a, 6c, the input / output wiring groups 8a, 8b, 1
The pin B group and the logic circuit 3 are electrically connected via 2a and 12b. The input / output data in this connection state is indicated by B in FIG. Further, the switching circuits 6a,
6b, the pin C group and the logic circuit 4 are electrically connected via the input / output wiring groups 9a, 9b, 13a, 13b. The input / output data in this connection state is indicated by C in FIG. Further, the pin D group and the logic circuit 5 are electrically connected via the switching circuits 6a, 6c and the input / output wiring groups 10a, 10b, 14a, 14b. The input / output data in this connection state is indicated by D in FIG.

At this time, in the state where MIRROR is turned on in FIG. 1B, that is, in the reverse bend mode, the data input / output to / from each pin group is as follows. By switching the connection relationship by the switching circuits 6a and 6b, the pin A group and the logic circuit 4 are electrically connected via the input / output wiring groups 7a, 7b, 13a and 13b. That is, it is switched to the connection target in the pin C group in the normal bend mode. For this reason, in FIG. 1B, the connection state of the pin A group becomes C by turning on MIRROR.

Switching of the connection relationship by the switching circuits 6a, 6c allows the input / output wiring groups 8a, 8b, 14
The pin B group and the logic circuit 5 are electrically connected via a and 14b. That is, it is switched to the connection target in the pin D group in the normal bend mode. For this reason, in FIG.
When the IRROR is turned on, the connection state of the pin B group becomes D.
Becomes

Further, by switching the connection relationship by the switching circuits 6a, 6b, the input / output wiring groups 9a, 9b, 11
The group of pins C and the logic circuit 2 are electrically connected via a and 11b. That is, it is switched to the connection target in the pin A group in the normal bend mode. For this reason, in FIG.
When the IRROR is turned on, the connection state of the pin C group becomes A.
Becomes

Further, by switching the connection relationship by the switching circuits 6a, 6c, the input / output wiring groups 10a, 10b,
The group of pins D and the logic circuit 3 are electrically connected via 12a and 12b. That is, it is switched to the connection target in the pin B group in the normal bend mode. For this reason, in FIG. 1B, the connection state of the pin D group becomes B by turning on MIRROR.

In summary, in the semiconductor chip 1, the switching circuits 6a, 6b,
6c is a so-called mirror inversion (refer to FIG. 1 (b) in FIG. 1 (b)) in which the connection relationship between each pin group and the logic circuits 2, 3, 4, 5 is symmetrical with respect to a symmetrical line indicated by a broken line in FIG. MIRR
OR).

Here, features of the semiconductor device according to the first embodiment will be described. First, switching between the normal / reverse bend mode is performed symmetrically with respect to the symmetry line at the time of mirror inversion in FIG. Thereby, all the output wiring groups 7
b, 8b, 9b, 10b, 11b, 12b, 13b, 1
4b does not need to be connected to the switching circuit 6a (especially, it is not necessary to extend the output wiring groups 7b, 8b, 9b, 10b to the switching circuit 6a), and it is possible to suppress the concentration of wiring groups around the switching circuit 6a. Can be.

Input wiring groups 7a, 8a, 9a, 10a, 1
The switching circuit 6a for switching the connection destinations of 1a, 12a, 13a, and 14a is connected to the central portion of the semiconductor chip 1 (that is, the wiring lengths of the input wiring groups of the logic circuits 2, 3, 4, and 5 are not biased via the switching circuit 6a). (Position where it is arranged). In addition, a switching circuit 6 for switching the connection destination of the output wiring group
b and 6c are output-only switching circuits 6b and 6c to be switched (pin A group and pin C group, pin B group and pin D
) As a set and arranged near the corresponding pin. That is, the output wiring groups 7b and 9 of the pin A group and the pin C group
The switching circuit 6b for switching the connection destination of the pin b is arranged near the pin A group and the pin C group, and the switching circuit 6c for switching the connection destination of the output wiring groups 8b and 10b between the pin B group and the pin D group is connected to the pin B group. And near the pin D group.

In the above-described configuration, the signal input to the switching circuit 6a provided near the center of the semiconductor chip 1 is input to the logic circuits 2, 3, 4, and 5 for processing, and the output signal resulting therefrom is output to each pin group. Logic processing by the logic circuits 2, 3, 4, and 5, such as flowing in the direction, flows from the vicinity of the center of the semiconductor chip 1 to the pin group at the end. That is, like the conventional semiconductor chip 100, the signal input to the switching circuit 105 provided near the center of the semiconductor chip 1 is input to the logic circuits 101, 102, 103, and 104 for processing, and the output signal due to this is output. After returning to the switching circuit 105 again, the output from each pin group does not occur.

Thus, by providing the forward / reverse bend mode switching function, the wiring does not concentrate around the switching circuit. In the example of FIG. 1, considering the number of wiring groups on the left side with respect to the switching circuit 6a in the area surrounded by the broken line in FIG. 1A, the horizontal wiring connecting the pin A group, the pin C group, and the switching circuit 6a is considered. There are a total of four bundles of wiring groups in which certain wiring groups 7a and 9a are added with wiring groups 11a and 13a, which are horizontal wirings that connect the logic circuits 2 and 4 and the switching circuit 6a.
That is, half the number of wiring groups of the conventional semiconductor chip 100 shown in FIG.

As described above, according to the first embodiment, a pair of pins (a group of pins A, a group of pins B, a group of pins C, and a group of pins D) of the semiconductor chip 1 are dispersedly provided in the semiconductor chip 1. Group) and a plurality of switching circuits 6a, 6b which relay the connection between a pair of terminals (input / output terminals (not shown) of the logic circuits 2, 3, 4, 5) in the semiconductor chip 1 and switch these connections. , 6c, it is possible to suppress the concentration of wiring in the peripheral portion of the switching circuit without impairing the function of switching between the forward / reverse bend mode, so that the peripheral portion can be reduced in area. Thereby, the semiconductor chip 1 can be reduced in size.

Further, according to the first embodiment, the switching circuit is changed from the pins (pin A group, pin B group, pin C group, pin D group) of the semiconductor chip 1 to the terminals (logic circuit) in the semiconductor chip 1. An input-only switching circuit 6a for relaying connection of wiring for transmitting an input signal to input terminals 2, 3, 4, 5 (not shown), and terminals (not shown for logic circuits 2, 3, 4, 5); Output terminal) to pin (pin A group, pin B group, pin C)
And the output-only switching circuits 6b and 6c for relaying the connection of the wiring for transmitting the output signal to the group, the pin D group). Therefore, it is possible to suppress the concentration of the wiring around the switching circuit.

Furthermore, according to the first embodiment, since the output-only switching circuits 6b and 6c are arranged near the pins of the semiconductor chip for switching the output destination, the output from each pin group to the switching circuits 6b and 6c is provided. Since the wiring length can be reduced, the output response from the semiconductor chip 1 can be made faster.

Embodiment 2 2A and 2B are diagrams showing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 2A is a schematic diagram showing the semiconductor device, and FIG. 2B is a diagram showing input / output data of each pin group before and after switching. FIG. In the figure, reference numeral 1A is a semiconductor chip constituting the semiconductor device according to the second embodiment, and has switching circuits 6d, 6e, 6f for switching between forward / reverse bend specifications. Reference numeral 6d denotes a switching circuit (main switching circuit, switching circuit) provided in the center of the semiconductor chip 1A (that is, the logic circuits 2, 3, 4, and 5 are symmetrically arranged with reference to the position of the switching circuit 6d). And logic circuits 2, 3, according to an external control signal.
The connection of a wiring (not shown) that propagates a signal (mainly a control signal for the logic circuits 2, 3, 4, and 5) input to all of the circuits 4 and 5 is switched. Reference numeral 6e denotes a switching circuit (sub-switching circuit, switching circuit) provided in the vicinity of the pin A group and the pin C group, and is mainly input / output to each of the pin A group and the pin C group according to an external control signal. Wiring groups 15a, 15b, 17a, 17b for transmitting signals to and from wiring groups 19 for transmitting signals input / output to / from each of the logic circuits 2, 4.
a, 19b, 21a, and 21b are switched. 6
f is a switching circuit (sub-switching circuit, switching circuit) provided in the vicinity of the pin B group and the pin D group, and is input / output mainly to each of the pin B group and the pin D group according to an external control signal. Wiring groups 16a, 16b, 18a, 18
b, and switches the connection between the wiring groups 20a, 20b, 22a, and 22b for transmitting signals input to and output from the logic circuits 3 and 5, respectively.

Reference numeral 15a denotes an input wiring group from the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6e to propagate an input signal from the pin A group. Reference numeral 15b denotes an output wiring group to the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6e to propagate an output signal to the pin A group. Reference numeral 16a denotes an input wiring group from the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 6f to propagate an input signal from the pin B group. 16b is pin B
In the output wiring group to the group, the pins constituting the group of pins B are electrically connected to the switching circuit 6f to propagate the output signal to the group of pins B. 17a is an input wiring group from the pin C group.
The input signal from the pin C group is propagated by electrically connecting the pins constituting the group and the switching circuit 6e. Reference numeral 17b denotes an output wiring group to the pin C group, which electrically connects the pins constituting the pin C group and the switching circuit 6e to propagate an output signal to the pin C group. Reference numeral 18a denotes an input wiring group from the pin D group, which electrically connects the pins constituting the pin D group and the switching circuit 6f to propagate an input signal from the pin D group. Reference numeral 18b denotes an output wiring group to the pin D group.
f is electrically connected to propagate an output signal to the pin D group.

Reference numeral 19a denotes an input wiring group to the logic circuit 2, which electrically connects the switching circuit 6e to the logic circuit 2 and propagates an input signal from the switching circuit 6e to the logic circuit 2. Reference numeral 19b denotes an output wiring group from the logic circuit 2, which electrically connects the switching circuit 6e to the logic circuit 2 and propagates an output signal from the logic circuit 2 to the switching circuit 6e. Reference numeral 20a denotes an input wiring group to the logic circuit 3, which electrically connects the switching circuit 6f and the logic circuit 3 to propagate an input signal from the switching circuit 6f to the logic circuit 3. Reference numeral 20b denotes an output wiring group from the logic circuit 3, which electrically connects the switching circuit 6f and the logic circuit 3 to propagate an output signal from the logic circuit 3 to the switching circuit 6f. Reference numeral 21a denotes an input wiring group to the logic circuit 4, which electrically connects the switching circuit 6e to the logic circuit 4 and propagates an input signal from the switching circuit 6e to the logic circuit 4.
Reference numeral 21b denotes an output wiring group from the logic circuit 4, which electrically connects the switching circuit 6e to the logic circuit 4 and propagates an output signal from the logic circuit 4 to the switching circuit 6e.
Reference numeral 22a denotes an input wiring group to the logic circuit 5, and the switching circuit 6
f and the logic circuit 5 are electrically connected to each other and a switching circuit 6f
From the input to the logic circuit 5. 22b
Is an output wiring group from the logic circuit 5, and electrically connects the switching circuit 6f and the logic circuit 5 to propagate an output signal from the logic circuit 5 to the switching circuit 6f. In addition,
The same components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the outline will be described. In FIG. 2B, in the state where MIRROR is off, that is, in the normal bend mode, data input / output to / from each pin group is as follows, for example. The pin A group and the logic circuit 2 are electrically connected via the switching circuit 6e and the input / output wiring groups 15a, 15b, 19a, 19b. The input / output data in this connection state is indicated by A in FIG. Further, the switching circuit 6f, the input / output wiring groups 16a, 16b, 20
The pin B group and the logic circuit 3 are electrically connected via a and 20b. The input / output data in this connection state is indicated by B in FIG. Further, the pin C group and the logic circuit 4 are electrically connected via the switching circuit 6e and the input / output wiring groups 17a, 17b, 21a, 21b. The input / output data in this connection state is indicated by C in FIG. Further, the switching circuit 6f, the input / output wiring groups 18a, 1
The group of pins D and the logic circuit 5 are electrically connected via 8b, 22a and 22b. The input / output data in this connection state is indicated by D in FIG.

At this time, in the state where MIRROR is turned on in FIG. 2B, that is, in the reverse bend mode, the data input / output to / from each pin group is as follows. By switching the connection relationship by the switching circuit 6e,
The pin A group and the logic circuit 4 are electrically connected via the input / output wiring groups 15a, 15b, 21a, 21b. That is, it is switched to the connection target in the pin C group in the normal bend mode. In addition, the switching circuit 6d inputs the signal input from the pin A group instead of the pin C group to all the logic circuits 2, 3, 4, and 5. For this reason, in FIG. 2B, the connection state of the pin A group becomes C by turning on MIRROR.

Further, by switching the connection relationship by the switching circuit 6f, the input / output wiring groups 16a, 16b, 22a,
The pin B group and the logic circuit 5 are electrically connected via 22b. That is, it is switched to the connection target in the pin D group in the normal bend mode. In addition, the switching circuit 6d inputs the signal input from the pin B group to all the logic circuits 2, 3, 4, and 5 instead of the pin D group. For this reason, in FIG. 2B, the connection state of the pin B group becomes D by turning on MIRROR.

Further, by switching the connection relation by the switching circuit 6e, the input / output wiring groups 17a, 17b, 19
The group of pins C and the logic circuit 2 are electrically connected via a and 19b. That is, it is switched to the connection target in the pin A group in the normal bend mode. In addition to this, the switching circuit 6d
Input the signal input from the pin C group in place of the pin A group to all the logic circuits 2, 3, 4, and 5. For this reason, in FIG. 2B, the connection state of the pin C group becomes A by turning on MIRROR.

Further, by switching the connection relationship by the switching circuit 6f, the input / output wiring groups 18a, 18b, 20
The group of pins D and the logic circuit 3 are electrically connected via a and 20b. That is, it is switched to the connection target in the pin B group in the normal bend mode. In addition to this, the switching circuit 6d
Inputs the signal input from the pin D group to all the logic circuits 2, 3, 4, and 5 in place of the pin B group. For this reason, in FIG. 2B, the connection state of the pin D group becomes B by turning on MIRROR.

In summary, in the semiconductor chip 1A, the switching circuits 6d and 6d are controlled according to an external control signal.
e, 6f indicate the connection relationship between each group of pins and the logic circuits 2, 3, 4, 5 with a so-called mirror inversion (FIG. 2B) which is symmetrical with respect to a symmetrical line shown by a broken line in FIG. MI inside
RROR).

Here, features of the semiconductor device according to the second embodiment will be described. First, similarly to the first embodiment, the switching between the normal / reverse bend mode is performed symmetrically with respect to the symmetry line at the time of mirror inversion in FIG. Thereby, all the output wiring groups 15b, 16b, 17b, 1
8b, 19b, 20b, 21b and 22b are switched to a switching circuit 6d
Is not necessary, and it is possible to suppress the concentration of the wiring group around the switching circuit 6d.

In addition, control signals for controlling mainly the logic circuits 2, 3, 4, 5 (all the logic circuits 2, 3, 4, 5)
The switching circuit 6d for switching the group of pins for inputting the signals used in the first embodiment is connected to the center of the semiconductor chip 1A (that is, the wiring lengths of the input wiring groups of the logic circuits 2, 3, 4, and 5 via the switching circuit 6d are biased). At a position where they are not placed. In addition, the switching circuits 6e and 6f for switching the connection destinations of the wiring groups that mainly transmit and receive the signals that input and output the individual logic circuits 2, 3, 4, and 5 are connected to each other (the pin A group and the pin A). The group C, the group of the pins B, and the group of the pins D) are grouped and arranged near the corresponding pins. That is, the pin A group and the pin C
The switching circuit 6e for switching the connection destination of the input / output wiring groups 15a, 15b, 17a, 17b with the group is connected to the pin A group and the pin C
A switching circuit 6f for switching the connection destination of the input / output wiring groups 16a, 16b, 18a, 18b between the pin B group and the pin D group is disposed near the pin B group and the pin D group.

In the above-described configuration, the signals used only in the individual logic circuits input from the respective pin groups via the switching circuits 6e and 6f are input to the logic circuits 2, 3, 4, and 5 for processing. As a result, the output signal returns to the direction of each pin group again, and all the logic circuits 2, 3, 4, 5
The switching circuit 6d performs switching of the pin group for inputting the signal used in the above. That is, the conventional semiconductor chip 1
00, the signal input to the switching circuit 105 provided near the center of the semiconductor chip 100 is the logic circuit 101,
There is no such a case that the input signals are input to 102, 103, and 104 to be processed, and the output signals are output from the respective pin groups after returning to the switching circuit 105 again.

Thus, by providing the forward / reverse bend mode switching function, the wiring does not concentrate around the switching circuit. In the example of FIG. 2, in the peripheral areas of the switching circuits 6e and 6f surrounded by broken lines in FIG. 2A, wiring groups 19a, 19b and 21a as horizontal wirings connecting the logic circuits 2 and 4 and the switching circuit 6e. , 21b, and four bundles of wiring groups 20a, 20b, 22a, 22b, which are horizontal wirings connecting the logic circuits 3, 5 and the switching circuit 6f. That is, half the number of wiring groups of the conventional semiconductor chip 100 shown in FIG.

As described above, according to the second embodiment, all the logic circuits 2, 3, and 3 in the semiconductor chip 1A are provided.
A switching circuit 6d for relaying connection of wiring for inputting / outputting signals used for signals 4 and 5; Since the switching circuits 6e and 6f for relaying the connection between the switching circuits 6b and 6f are provided, it is possible to suppress the concentration of the wiring around the switching circuit without impairing the switching function of the forward / reverse bend mode. The area can be reduced. Thus, the size of the semiconductor chip 1A can be reduced.

According to the second embodiment, the switching circuits 6e and 6f are arranged near the pin group of the semiconductor chip 1A for switching the output destination.
Since the output wiring lengths e and 6f can be shortened, the output response from the semiconductor chip 1A can be made faster.

In the second embodiment, the case where the switching circuit 6d is provided near the center of the semiconductor chip 1A has been described. A switching circuit for switching a connection destination of a wiring for transmitting a signal to be transmitted or a switching circuit for switching a connection destination of a wiring for transmitting a control signal related to control between logic circuits may be provided near the center of the semiconductor chip 1A.

Embodiment 3 Third Embodiment A third embodiment relates to a semiconductor device having a specification in which signals used in all logic circuits are hardly handled or a specification that does not require a common wiring for inputting and outputting signals to and from all logic circuits. is there.

FIGS. 3A and 3B are views showing a semiconductor device according to a third embodiment of the present invention. FIG. 3A is a schematic view showing the configuration of the semiconductor device, and FIG. FIG. 3 is a table showing input / output data. In the figure,
1B is a semiconductor chip constituting the semiconductor device according to the third embodiment, and has switching circuits 6g and 6h for switching between forward / reverse bend specifications. Reference numeral 6g denotes a switching circuit provided in the vicinity of the pin A group and the pin C group, and a wiring group 23a mainly for transmitting a signal input / output to each of the pin A group and the pin C group according to an external control signal. , 23b, 25a, 25b
And the wiring groups 27a, 27b, 29a, and 29b for transmitting signals input to and output from the logic circuits 2 and 4, respectively. Reference numeral 6h denotes a switching circuit provided in the vicinity of the pin B group and the pin D group, and a wiring group 24a mainly transmitting signals input to and output from each of the pin B group and the pin D group according to an external control signal. , 24b, 26a, 26b and wiring groups 28a, 28b, 30a, 30b for transmitting signals input to and output from the logic circuits 3, 5, respectively.

Reference numeral 23a denotes an input wiring group from the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6g to transmit an input signal from the pin A group. Reference numeral 23b denotes an output wiring group to the pin A group, which electrically connects the pins constituting the pin A group and the switching circuit 6g to propagate an output signal to the pin A group. Reference numeral 24a denotes an input wiring group from the pin B group, which electrically connects the pins constituting the pin B group and the switching circuit 6h to propagate an input signal from the pin B group. 24b is pin B
In the output wiring group to the group, the pins constituting the group of pins B are electrically connected to the switching circuit 6h to propagate the output signal to the group of pins B. 25a is an input wiring group from the pin C group.
The input signal from the pin C group is propagated by electrically connecting the pins constituting the group and the switching circuit 6g. Reference numeral 25b denotes an output wiring group to the pin C group, which electrically connects the pins constituting the pin C group and the switching circuit 6g to propagate an output signal to the pin C group. Reference numeral 26a denotes an input wiring group from the pin D group, which electrically connects the pins constituting the pin D group and the switching circuit 6h to propagate an input signal from the pin D group. Reference numeral 26b denotes an output wiring group to the pin D group.
h is electrically connected to propagate the output signal to the pin D group.

Reference numeral 27a denotes a group of input wirings to the logic circuit 2, which electrically connects the switching circuit 6g and the logic circuit 2 and propagates an input signal from the switching circuit 6g to the logic circuit 2. Reference numeral 27b denotes an output wiring group from the logic circuit 2, which electrically connects the switching circuit 6g and the logic circuit 2 and propagates an output signal from the logic circuit 2 to the switching circuit 6g. Reference numeral 28a denotes an input wiring group to the logic circuit 3, which electrically connects the switching circuit 6h and the logic circuit 3 and propagates an input signal from the switching circuit 6h to the logic circuit 3. Reference numeral 28b denotes an output wiring group from the logic circuit 3, which electrically connects the switching circuit 6h and the logic circuit 3 to transmit an output signal from the logic circuit 3 to the switching circuit 6h. Reference numeral 29a denotes an input wiring group to the logic circuit 4, which electrically connects the switching circuit 6g and the logic circuit 4 to propagate an input signal from the switching circuit 6g to the logic circuit 4.
Reference numeral 29b denotes an output wiring group from the logic circuit 4, which electrically connects the switching circuit 6g and the logic circuit 4 and propagates an output signal from the logic circuit 4 to the switching circuit 6g.
30a is a group of input wires to the logic circuit 5, and a switching circuit 6a.
switching circuit 6h by electrically connecting the logic circuit 5 to the logic circuit 5
From the input to the logic circuit 5. 30b
Is an output wiring group from the logic circuit 5, and electrically connects the switching circuit 6h and the logic circuit 5 to propagate an output signal from the logic circuit 5 to the switching circuit 6h. In addition,
The same components as those in FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

Next, the outline will be described. In the state where MIRROR is off in FIG. 3B, that is, in the normal bend mode, data input / output to / from each pin group is as follows, for example. The pin A group and the logic circuit 2 are electrically connected via the switching circuit 6g and the input / output wiring groups 23a, 23b, 27a, 27b. The input / output data in this connection state is indicated by A in FIG. Further, the switching circuit 6h, the input / output wiring groups 24a, 24b, 28
The pin B group and the logic circuit 3 are electrically connected via a and 28b. The input / output data in this connection state is indicated by B in FIG. Further, the pin C group and the logic circuit 4 are electrically connected via the switching circuit 6g and the input / output wiring groups 25a, 25b, 29a, 29b. The input / output data in this connection state is indicated by C in FIG. Further, the switching circuit 6h, the input / output wiring groups 26a, 26
The group of pins D and the logic circuit 5 are electrically connected via 6b, 30a, 30b. The input / output data in this connection state is indicated by D in FIG.

At this time, in the state where MIRROR is turned on in FIG. 3B, that is, in the reverse bend mode, the data input / output to / from each pin group is as follows. By switching the connection relationship by the switching circuit 6g,
The pin A group and the logic circuit 4 are electrically connected via the input / output wiring groups 23a, 23b, 29a, 29b. That is, it is switched to the connection target in the pin C group in the normal bend mode. For this reason, in FIG. 3B, the connection state of the pin A group becomes C by turning on MIRROR.

Further, by switching the connection relation by the switching circuit 6h, the input / output wiring groups 24a, 24b, 30a,
The group of pins B and the logic circuit 5 are electrically connected via 30b. That is, it is switched to the connection target in the pin D group in the normal bend mode. For this reason, in FIG.
When the ROR is turned on, the connection state of the pin B group becomes D.

Further, by switching the connection relationship by the switching circuit 6g, the input / output wiring groups 25a, 25b, 27
The group of pins C and the logic circuit 2 are electrically connected via a and 27b. That is, it is switched to the connection target in the pin A group in the normal bend mode. For this reason, in FIG.
When the IRROR is turned on, the connection state of the pin C group becomes A.
Becomes

Further, by switching the connection relationship by the switching circuit 6h, the input / output wiring groups 26a, 26b, 28
The group of pins D and the logic circuit 3 are electrically connected via a and 28b. That is, it is switched to the connection target in the pin B group in the normal bend mode. For this reason, in FIG.
When the IRROR is turned on, the connection state of the pin D group becomes B
Becomes

In summary, in the semiconductor chip 1B, the switching circuits 6g and 6h are switched according to an external control signal.
Describes the connection relationship between each group of pins and the logic circuits 2, 3, 4, and 5 with a so-called mirror inversion (MIRRO in FIG. 3B) symmetrical with respect to a symmetrical line indicated by a broken line in FIG.
R).

Here, features of the semiconductor device according to the third embodiment will be described. First, as in the first embodiment, the switching between the forward / reverse bend mode is performed symmetrically with respect to the symmetry line at the time of mirror inversion in FIG. Thereby, all the output wiring groups 23b, 24b, 25b, 2
6b, 27b, 28b, 29b, and 30b are not wired near the center of the semiconductor chip 1B, and the concentration of the wiring groups can be suppressed.

Further, no switching circuit is provided near the center of the semiconductor chip 1B. In addition, the switching circuits 6g and 6h that mainly switch the connection destinations of the wiring groups that propagate signals that input and output the individual logic circuits 2, 3, 4, and 5 are connected to each other (pin A group and pin A). Group C, Pin B and Pin D
) As a set and arranged near the corresponding pin. That is, the input / output wiring group 23 between the pin A group and the pin C group
A switching circuit 6g for switching the connection destinations of the pins a, 23b, 25a, and 25b is arranged near the pin A group and the pin C group, and the input / output wiring groups 24a, 24b, and 26 for the pin B group and the pin D group.
The switching circuit 6h for switching the connection destination of the a and 26b is connected to the pin B
It is arranged near the group and the pin D group.

In the above-described configuration, signals used only in the individual logic circuits input from the respective pin groups via the switching circuits 6g and 6h are input to the logic circuits 2, 3, 4, and 5 for processing. As a result, the output signal returns to the direction of each pin group. That is, like the conventional semiconductor chip 100, the switching circuit 1 provided near the center of the semiconductor chip 100
05 are the logic circuits 101, 102, 1
There is no such a case that an input signal is input to the pins 03 and 104 to be processed, and an output signal due to this is output from each pin group after returning to the switching circuit 105 again.

Thus, by providing the forward / reverse bend mode switching function, the wiring does not concentrate around the switching circuit. In the example of FIG. 3, in the peripheral areas of the switching circuits 6g and 6h surrounded by broken lines in FIG. 3A, wiring groups 27a, 27b and 29a, which are horizontal wirings connecting the logic circuits 2 and 4 and the switching circuit 6g. , 29b, and four bundles of wiring groups 28a, 28b, 30a, 30b, which are horizontal wirings connecting the logic circuits 3, 5 and the switching circuit 6h. That is, half the number of wiring groups of the conventional semiconductor chip 100 shown in FIG.

As described above, according to the third embodiment, the individual logic circuits 2, 3, 3 in the semiconductor chip 1B
Switching circuits 6g and 6h are provided for relaying connections of wirings for inputting and outputting signals used only for signals 4 and 5, respectively. These switching circuits 6g and 6h are arranged in the vicinity of pins for switching output destinations. Since it is possible to suppress the concentration of wiring in the peripheral portion of the switching circuit without impairing the function, the peripheral portion can be reduced in area.
Thereby, the semiconductor chip 1B can be downsized. In addition, since the output wiring length from each pin group to the switching circuits 6g and 6h can be shortened, the output response from the semiconductor chip 1B can be made faster.

[0065]

As described above, according to the present invention, the connection between the pair of pins of the semiconductor chip and the pair of terminals in the semiconductor chip is provided by being dispersed in the semiconductor chip. Since a plurality of switching circuits for switching the connection are provided, it is possible to suppress the concentration of the wiring in the peripheral portion of the switching circuit, so that the peripheral portion can be reduced in area. Thus, there is an effect that the size of the semiconductor device can be reduced.

According to the present invention, the switching circuit includes an input-only switching circuit that relays a connection of a wiring for transmitting an input signal from a pin of the semiconductor chip to a terminal in the semiconductor chip, and an output signal from the terminal to the pin. Since it is composed of the output-only switching circuit that relays the connection of the wiring that propagates, it is possible to suppress the concentration of the wiring in the peripheral portion of the switching circuit, and thus it is possible to reduce the area of the peripheral portion. .

According to the present invention, since the output-only switching circuit is arranged near the pin of the semiconductor chip for switching the output destination, the length of the output wiring from the pin to the switching circuit can be shortened. The effect is that the response can be made faster.

According to the present invention, the switching circuit includes a main switching circuit for relaying connection of wiring for inputting and outputting signals used for all internal circuits in the semiconductor chip, and a switching circuit for each internal circuit in the semiconductor chip. Since it is composed of a sub-switching circuit that relays the connection of the wiring that inputs and outputs only the signals that are used, it is possible to suppress the concentration of the wiring in the peripheral portion of the switching circuit. There is an effect that can be.

According to the present invention, since the sub-switching circuit is arranged near the pin of the semiconductor chip for switching the output destination,
Since the output wiring length from the pin to the switching circuit can be shortened, the output response of the semiconductor device can be made faster.

According to the present invention, the switching circuit relays the connection of the wiring for inputting / outputting a signal used only for each internal circuit in the semiconductor chip, and is arranged near the pin for switching the output destination. Therefore, it is possible to suppress the concentration of wiring in the peripheral portion of the switching circuit, and to increase the output response of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a third embodiment of the present invention;

FIG. 4 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

1, 1A, 1B semiconductor chip, 2, 3, 4, 5 logic circuit (internal circuit), 6a switching circuit (input-only switching circuit, switching circuit), 6b switching circuit (output-only switching circuit, switching circuit), 6c switching Circuit (output-only switching circuit,
Switching circuit), 6d switching circuit (main switching circuit, switching circuit),
6e switching circuit (sub-switching circuit, switching circuit), 6f switching circuit (sub-switching circuit, switching circuit), 6g, 6h switching circuit, 7a, 15a, 23a input wiring group from pin A group, 7b, 15b, 23b pin Output wiring group to group A,
8a, 16a, 24a Input wiring group from pin B group, 8
b, 16b, 24b Output wiring group to pin B group, 9a,
17a, 25a Input wiring group from pin C group, 9b, 1
7b, 25b Output wiring group to pin C group, 10a, 18
a, 26a Input wiring group from pin D group, 10b, 18
b, 26b Output wiring group to pin D group, 11a, 19
a, 27a Input wiring group to the logic circuit 2, 11b,
19b, 27b Output wiring group from logic circuit 2, 1
2a, 20a, 28a Input wiring group to logic circuit 3, 12b, 20b, 28b Output wiring group from logic circuit 3, 13a, 21a, 29a Input wiring group to logic circuit 4, 13b, 21b, 29b Logic circuit 4 , Output wiring groups from the logic circuit 5, 14b, 22b, 30b output wiring groups from the logic circuit 5, 100 semiconductor chips, 101, 102, 103, 104 logic circuits,
105 switching circuit, 106a input wiring group from pin A group, 106b output wiring group to pin A group, 107a input wiring group from pin B group, 107b output wiring group to pin B group, 108a Input wiring group, 108
b output wiring group to pin C group, 109a input wiring group from pin D group, 109b output wiring group to pin D group, 1
10a Input wiring group to logic circuit 101, 110b
Output wiring group from logic circuit 101, 111a Input wiring group to logic circuit 102, 111b Output wiring group from logic circuit 102, 112a logic circuit 1
03, an output wiring group from the logic circuit 103, an input wiring group to the logic circuit 104, and an output wiring group from the logic circuit 104.

Claims (6)

[Claims] A plurality of switching circuits provided separately in a semiconductor chip, each of which relays a connection between a pair of pins of the semiconductor chip and a pair of terminals in the semiconductor chip, and switches these connections. Semiconductor device. 2. A switching circuit, comprising: an input-only switching circuit for relaying a connection of a wiring for transmitting an input signal from a pin of a semiconductor chip to a terminal in the semiconductor chip; and an output signal from the terminal to the pin. 2. The semiconductor device according to claim 1, further comprising an output-only switching circuit that relays connection of wirings to be connected. 3. The semiconductor device according to claim 2, wherein the output-only switching circuit is arranged near a pin of the semiconductor chip for switching an output destination. 4. The switching circuit is used only for a main switching circuit that relays connection of wiring for inputting and outputting signals used for all internal circuits in the semiconductor chip, and for each internal circuit in the semiconductor chip. 2. The semiconductor device according to claim 1, further comprising: a sub-switching circuit that relays connection of a wiring for inputting / outputting a signal. 5. The semiconductor device according to claim 4, wherein the sub-switching circuit is arranged near a pin of the semiconductor chip for switching an output destination. 6. The switching circuit is characterized in that the switching circuit relays a connection of a wiring for inputting and outputting a signal used only for each internal circuit in the semiconductor chip, and is arranged near a pin for switching an output destination. 2. The semiconductor device according to claim 1, wherein