KR19990002305A - Multiport Circuit in the Central Processing Unit (CPU) - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Central Processing Unit

2. The technical problem to be solved by the invention

In the conventional central processing unit, the port is installed to be used only for a specific purpose, and is intended to solve the disadvantage that the designed use cannot be changed.

3. Summary of Solution to Invention

It is placed between the main central processing unit 10 and the plurality of sub central processing units 20 and 30, and transmits signals generated by the main central processing unit 10, signals transmitted by the external port 40, and a plurality of sub signals. Selectively and logically combine the signals transmitted from the sub CPUs 20 and 30 to make a transmission and reception signal, and generate the plurality of path control signals generated by the main CPU 10. It characterized in that it comprises a data interface unit 50 to interface with each other according to Controol-Control3).

4. Important uses of the invention

The port is applied to the port utilization in the central processing unit designed for a specific purpose.

Description

Multiport Circuit in the Central Processing Unit (CPU)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a central processing unit (CPU), and more particularly to an input / output port for performing data input / output with another central processing unit.

In general, the port of the central processing unit is designed to be used for a specific purpose, and the intended use is not changed. 1 schematically shows a main central processing unit that performs data communication with another central processing unit by using a port designed for a specific purpose as described above.

Here, the main CPU 1 performs a data interface with the sub CPU 2 only through the first port SIO0, and the data with the sub CPU 3 only through the second port SID1. It will do the interface.

Therefore, in the conventional system having such a configuration, data interfaces are possible with the two sub-processors 2 and 3 through the first and second ports SID0 and SID1 in the main CPU 1, respectively. You cannot use that port to do anything else (e.g. debug, message output, etc.).

In order to perform other tasks in the above configuration, an expensive device must be used separately, and in this case, the main CPU should also process an interrupt signal.

Therefore, the present invention has been proposed to solve various problems occurring when the port of the conventional central processing unit is used as described above. The present invention is versatile depending on the use of a single port of a central processing unit (CPU). It is to provide a multi-port circuit of a central processing unit that can be used as a multi port so that the central processing unit can control the system normally even under special circumstances.

Technical means for achieving this object of the present invention;

A connection system between a main central processing unit and a plurality of sub central processing units;

A logical combination is provided between the main central processing unit and two sub central processing units to selectively transmit signals generated from the main central processing unit, signals transmitted from an external port, and signals transmitted from the plurality of sub central processing units, respectively. And a data interface unit for making a transmission and reception signal and interfacing the generated transmission signal according to a plurality of path control signals generated by the main CPU.

Hereinafter, described in detail with reference to the accompanying drawings the operation of the preferred embodiment of the present invention.

1 is a state diagram of a connection between a conventional central processing unit and another central processing unit;

Figure 2 is a block diagram of a multi-port circuit of the central processing unit according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: main central processing unit 20, 30: sub central processing unit

40: external port 50: data interface

2 is a block diagram of a multi-port circuit in the central processing unit according to the present invention.

As shown therein, reference numeral 10 denotes a main central processing unit for interfacing data with other sub- central processing units 20 and 30 while controlling the data interface path, and 20 and 30 refer to the main central processing unit and data. 40 is an external port for transmitting and receiving data to and from the main CPU 10 and the sub CPU 20 and 30.

In addition, the reference numeral 50 is placed between the main CPU 10 and the plurality of sub CPUs 20, 30, the transmission signal generated from the main CPU 10 and the external port 40 Selectively transmit and receive a signal transmitted from each of the plurality of sub-central processing units 20 and 30 to generate a transmission / reception signal, and transmit the received transmission / reception signal to the main central processing unit 10. It shows a data interface unit which interfaces with each other according to a plurality of path control signals generated from the.

The multi-port circuit of the central processing unit according to the present invention having the above-described configuration may be a first device in order to first interface data with a desired sub central processing unit 20 or 30 or an external port 40 in the main central processing unit 10. To third control signal (Controll-Control3) is set as shown in the following table (1-1) to control the transmission and reception path of data, and to transmit and receive data using a desired port corresponding to the path control signal. .

Table (1-1) Control signal relation diagram for data transmission and reception path

In the above, X is Don't Care.

As an example, when the main CPU 10 exchanges data with the sub CPU 20 using the port SIO0, the main CPU 10 is shown in Table 1-1. When the first and third control signals Control1 and Control3 output a high signal and output the transmission data TxD0 through the port SIO0, the transmission data is logically multiplied with the first control signal by the AND gate 51. The first control signal phase-inverted by the inverter 52 becomes low at the AND gate 53, and is output as a low signal at the AND gate 53. Therefore, the output of the AND gate 53 is transmitted to the transmitting end of the external port 40, but since the transmission signal is a low signal, data is not actually transmitted to the external port 40, and the output of the AND gate 51 is output. The high signal, which is a signal, is logically multiplied by the high signal, which is the third control signal Control3, in the AND gate 57 and transmitted to the receiving end of the sub CPU 20 as a high signal.

Similarly, when the first and third control signals are respectively in the high state as described above, the signal transmitted from the sub CPU 20 is logically ANDed with the third control signal at the AND gate 62, where the AND gate ( Since both input stage signals of 62 are high, the output becomes a high signal and is transmitted to the receiving end of port SIO0 of the main central processing unit 10 connected to the output stage so that the main central processing unit 10 and the sub central processing unit 20 ) Will interface with each other.

Similarly, if the path is controlled by the first to third control signals according to the following table (1-1), and the data is selectively transmitted and received through the ports SIO0 and SIO1, the sub-central processing unit 20 and 30 may, of course, be used. The data interface with the external port 40 is also possible, so that it can be operated as a multi-port without changing the single port designed of the main CPU 10.

As described above, the present invention has the effect that a single port of the main CPU can be used as a multi-port using a simple logic gate without using other expensive devices.

The present invention utilizes a single port of a central processing unit (CPU) as a multi-port that is versatile, depending on the purpose, so that the central processing unit can operate as a multi-system even under special circumstances. It is to provide a multi-port circuit of the processing unit.

Claims (1)

In the connection system between the main central processing unit 10 and the plurality of sub central processing units 20, 30, It is placed between the main central processing unit 10 and the plurality of sub central processing units 20 and 30, and transmits a signal generated by the main central processing unit 10 and a transmission signal of the external port 40, and a plurality of sub signals. A plurality of path control signals generated by the main CPU 10 are generated by generating a transmission / reception signal by selectively logically combining the signals transmitted from the sub CPUs 20 and 30 respectively. A multi-port circuit of a central processing unit, comprising a data interface unit 50 which interfaces with each other according to (Controll-Control3).