JP2002343614A - Multi-electrode type resistor for surface mounting - Google Patents

Multi-electrode type resistor for surface mounting

Info

Publication number
JP2002343614A
JP2002343614A JP2001146884A JP2001146884A JP2002343614A JP 2002343614 A JP2002343614 A JP 2002343614A JP 2001146884 A JP2001146884 A JP 2001146884A JP 2001146884 A JP2001146884 A JP 2001146884A JP 2002343614 A JP2002343614 A JP 2002343614A
Authority
JP
Japan
Prior art keywords
resistor
electrodes
electrode
resistors
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001146884A
Other languages
Japanese (ja)
Inventor
Akihiko Yamaki
昭彦 八巻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Miyagi Ltd
Original Assignee
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Miyagi Ltd filed Critical NEC Miyagi Ltd
Priority to JP2001146884A priority Critical patent/JP2002343614A/en
Publication of JP2002343614A publication Critical patent/JP2002343614A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To improve the flexibility of pattern design by using resistors with the same resistance value between any electrodes, in a multi-electrode type resistor for surface mounting. SOLUTION: This resistor comprises a ceramic board 2, four electrodes 1a to 1d arranged respectively on four sides of the ceramic board 2, two resistors 3a and 3b with the same resistance value that are formed crossing each other at an intermediate point between facing two electrodes on the opposite two sides, the electrodes 1a and 1c and the electrodes 1b and 1c, and a protective coat 4 made of insulator for protecting the resistors 3a and 3b. As shown in Fig. 1, the resistance valve of resistor 3a or of 3b will be shown between any electrodes. The ceramic board 2 may be of a small shape or polygonal in shape. In addition, by subjecting a crossed part of resistors to electrode formation, the current concentration is averaged out, and a sub-electrode is provided to improve the flexibility of pattern design and can also be used as a set resistor.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は表面実装用多極型抵
抗器に関し、特に回路基板などに搭載した時に回路基板
側のパターン設計に自由度を与えるために、4電極以上
の多電極を有し何れの2電極間でも同じ抵抗値が得られ
る表面実装用の多極型抵抗器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-pole resistor for surface mounting, and more particularly to a multi-pole resistor having four or more electrodes in order to give a degree of freedom in pattern design on a circuit board when mounted on a circuit board or the like. The present invention also relates to a multi-pole type surface mount resistor capable of obtaining the same resistance value between any two electrodes.

【0002】[0002]

【従来の技術】この種の表面実装用多極型抵抗器が搭載
される回路基板は、通常高密度実装が要求され、配線パ
ターンは輻輳して密度の高い配線パターンとなる。従っ
てこの種の表面実装用多極型抵抗器は、小型化と同時に
配線位置が選択できる多極型の抵抗器が望まれている。
即ち、何れの方向からもパターンが接続できる多電極を
備え、回路基板側のパターン設計に自由度を与える抵抗
器である。
2. Description of the Related Art A circuit board on which this type of multi-pole resistor for surface mounting is mounted usually requires high-density mounting, and the wiring pattern becomes congested and becomes a high-density wiring pattern. Therefore, for this type of multi-pole resistor for surface mounting, a multi-pole resistor capable of selecting a wiring position at the same time as miniaturization is desired.
In other words, it is a resistor that has multiple electrodes to which patterns can be connected from any direction and that gives a degree of freedom to the pattern design on the circuit board side.

【0003】従来、この種の表面実装用多極型抵抗器と
しては、例えば実開平01−115206号公報に記載
された角板形チップ複合抵抗器がある。
Conventionally, as this type of multi-pole type surface mount resistor, there is, for example, a square plate type chip composite resistor described in Japanese Utility Model Laid-Open Publication No. H01-115206.

【0004】図5はこの従来例を示す(a)平面図、
(b)等価結線図である。短形セラミック基板51と、
相対する2辺のそれぞれに形成した主電極52、52’
と、この主電極間に形成した抵抗体53と、残りの相対
する2辺の間に抵抗体53の中間点を通過し、形成され
た中間電極54とから構成される4電極型の抵抗器があ
る。
FIG. 5A is a plan view showing this conventional example.
(B) It is an equivalent connection diagram. A short ceramic substrate 51;
Main electrodes 52, 52 'formed on each of two opposing sides
And a resistor 53 formed between the main electrodes, and an intermediate electrode 54 formed between the two opposing sides of the resistor 53 and passing through an intermediate point of the resistor 53. There is.

【0005】この抵抗器は抵抗体53に中間電極54を
有する複合抵抗器として使用されるが、主電極52、5
2’と中間電極54との間で抵抗体53の1/2の抵抗
値を有する抵抗器として電極位置が4通りの選択が可能
であり、パターン設計の自由度が得られる。
This resistor is used as a composite resistor having a resistor 53 and an intermediate electrode 54.
A resistor having half the resistance of the resistor 53 between 2 'and the intermediate electrode 54 can be selected from four electrode positions, and the degree of freedom in pattern design can be obtained.

【0006】また、他の従来例として特開平03−18
0004号公報に記載された表面実装用調整抵抗器があ
る。図6はこの他の従来例を示す(a)外観斜視図、
(b)展開平面図である。
Another conventional example is disclosed in Japanese Patent Laid-Open Publication No.
There is a surface mount adjustment resistor described in Japanese Patent Publication No. 0004. FIG. 6A is a perspective view showing another conventional example.
(B) It is an expanded top view.

【0007】図6において、61は表面実装用調整抵抗
器であり、正多角形の端面を有する角柱体、例えば立方
体に成形されたセラミックなどからなる絶縁体本体62
と、この絶縁体本体62の側面62a〜62dに形成さ
れた抵抗63a〜63dと、上記絶縁体本体62の一面
62eに形成され上記各抵抗63a〜63dすべての一
端側が接触された共通電極64と、上記共通電極64の
反対向きの面62fに形成され各抵抗63a〜63dそ
れぞれの他端側が接続された第1〜第4電極65a〜6
5dとから構成されている。上記各抵抗63a〜63d
は、それぞれ異なる抵抗値からなり、使用目的に応じて
設定される。
In FIG. 6, reference numeral 61 denotes a surface-mounting adjustment resistor, which is an insulator main body 62 made of ceramic or the like formed into a prism having a regular polygonal end face, for example, a cube.
And resistors 63a to 63d formed on side surfaces 62a to 62d of the insulator main body 62, and a common electrode 64 formed on one surface 62e of the insulator main body 62 and having one end of each of the resistors 63a to 63d contacted. The first to fourth electrodes 65a to 65d formed on the opposite surface 62f of the common electrode 64 and connected to the other ends of the resistors 63a to 63d, respectively.
5d. Each of the above resistors 63a to 63d
Have different resistance values and are set according to the purpose of use.

【0008】上記表面実装用調整抵抗器61は、回路基
板66に形成された第1、第2リード67a、67d間
に位置し、はんだ付けで固定される。この表面実装用調
整抵抗体61は、立方体であるため回路基板66上に任
意の状態で設置でき、組合せによっては一面62eの共
通電極64の0Ωを含め7通りの抵抗値を得ることがで
きる。
The surface mount adjustment resistor 61 is located between the first and second leads 67a and 67d formed on the circuit board 66, and is fixed by soldering. Since the surface-mount adjustment resistor 61 is a cube, it can be installed in any state on the circuit board 66, and depending on the combination, seven resistance values including 0Ω of the common electrode 64 on one surface 62e can be obtained.

【0009】このように本抵抗器61は、回路基板66
に対し搭載面を選ぶことにより抵抗値が変化する可変抵
抗器として使用するが、しかし抵抗63a〜63dを同
一抵抗値に選べば図6(a)に示した搭載状態で、電極
65a〜65dの何れの2電極間で同一抵抗値の抵抗と
して使用することができる。即ち、6通りの電極位置を
選択できるので回路基板66のパターン設計において配
線の自由度が得られる。
As described above, the resistor 61 is connected to the circuit board 66.
However, if the resistors 63a to 63d are selected to have the same resistance value, the resistance of the electrodes 65a to 65d is changed in the mounting state shown in FIG. Any two electrodes can be used as resistors having the same resistance value. That is, since six electrode positions can be selected, a degree of freedom in wiring can be obtained in the pattern design of the circuit board 66.

【0010】[0010]

【発明が解決しようとする課題】図5に示した従来例に
おいては、2つの主電極と2つの中間電極との間で4通
りの2電極組合せが選択できるが2つの主電極間と2つ
の中間電極間では同一抵抗値の抵抗体として使用するこ
とができないので、この分回路基板のパターン設計の自
由度がせまくなるという問題がある。
In the conventional example shown in FIG. 5, four combinations of two electrodes can be selected between two main electrodes and two intermediate electrodes. Since it cannot be used as a resistor having the same resistance value between the intermediate electrodes, there is a problem that the degree of freedom in the pattern design of the circuit board is reduced accordingly.

【0011】また、図6で示した従来例においては、6
つの電極の何れの2電極間でも同一抵抗値の抵抗器とし
て使用できるので、6通りの電極内組合せが可能であ
り、パターン設計の自由度が拡大するのでこの点では問
題ないが、しかし立方体の構造であるので回路基板に搭
載する時に高さ方向の実装制約が発生し、また、コスト
も高くなるという問題がある。
In the conventional example shown in FIG.
Although any two of the two electrodes can be used as a resistor having the same resistance value, six combinations within the electrode are possible, and the degree of freedom in pattern design is increased, so there is no problem in this respect. Due to the structure, there is a problem that mounting restrictions in the height direction occur when mounting on a circuit board, and the cost also increases.

【0012】尚ここでいうパターン設計の自由度につい
て、図5の従来例を参照して説明を加える。主電極52
−中間電極54(上)、主電極52−中間電極54
(下)、主電極52’−中間電極54(上)、主電極5
2’−中間電極54(下)の4通りの各電極間でそれぞ
れ同一抵抗値の抵抗体が構成されるので、この抵抗器を
搭載する回路基板側は高密度実装でパターンが輻輳して
いる場合、この輻輳状況から最もパターンを接続し易い
位置にある電極組みを4通りの中から選び使用すること
ができるので自由度があるという。本従来例では主電極
52−主電極52’間を使用した方が好都合である場合
に使用できないので、この分自由度が低下するという。
The degree of freedom in pattern design will be described with reference to the conventional example shown in FIG. Main electrode 52
-Intermediate electrode 54 (upper), main electrode 52-intermediate electrode 54
(Bottom), main electrode 52'-intermediate electrode 54 (top), main electrode 5
Since a resistor having the same resistance value is formed between each of the four electrodes of the 2′-intermediate electrode 54 (lower), the circuit board side on which the resistor is mounted is densely packed and the pattern is congested. In this case, it is said that there is a degree of freedom because an electrode set located at a position where a pattern can be most easily connected can be selected from four types and used based on the congestion situation. In this conventional example, since it is not possible to use the space between the main electrode 52 and the main electrode 52 'when it is more convenient, the degree of freedom is reduced accordingly.

【0013】[0013]

【課題を解決するための手段】本発明の表面実装用多極
型抵抗器は、正n(偶数)辺形のセラミック基板と、前
記セラミック基板の各辺に1個づつ配設された複数の電
極と、相対する各2辺の前記電極間に互に中間点を交差
するように形成された複数の抵抗体とを備得て構成す
る。
A multi-pole resistor for surface mounting according to the present invention comprises a ceramic substrate having a positive n (even number) side shape, and a plurality of ceramic substrates arranged on each side of the ceramic substrate. An electrode and a plurality of resistors formed so as to intersect an intermediate point between the electrodes on each of two opposing sides are provided.

【0014】あるいは、短形のセラミック基板と、前記
セラミック基板の各辺に1個づつ配設された4個の電極
と、相対する短辺の前記電極間に形成された第1の抵抗
体と、相対する長辺の前記電極間に形成された前記第1
の抵抗体の中間点と傾斜して交差しかつ前記第1の抵抗
体と同じ長さを有する第2の抵抗体とを備えて構成す
る。
[0014] Alternatively, a short ceramic substrate, four electrodes disposed one on each side of the ceramic substrate, and a first resistor formed between the electrodes on the opposite short sides. The first electrode formed between the electrodes on opposite long sides.
And a second resistor having the same length as the first resistor and intersecting at an intermediate point of the resistor.

【0015】あるいは、短形のセラミック基板と、前記
セラミック基板の短辺に1個づつまた長辺に2個づつ配
設された6個の電極と、相対する短辺の前記電極間に形
成された第1の抵抗体と、それぞれ斜め方向に相対する
長辺の2組みの前記電極間にそれぞれ形成された前記第
1の抵抗体の中間点と傾斜して交差しかつ前記第1の抵
抗体と同じ長さを有する第2および第3の抵抗体とを備
えて構成する。
Alternatively, a short ceramic substrate, six electrodes disposed one by one on the short side and two electrodes on the long side of the ceramic substrate, and the electrodes formed between the opposite short side electrodes are formed. The first resistor and an intermediate point of the first resistor formed between the two pairs of electrodes having long sides opposed to each other in an oblique direction at an angle and intersecting the first resistor. And a second resistor and a third resistor having the same length.

【0016】また、各前記抵抗体が交差する部分に前記
電極と同材質を用いて形成された中間電極を備えるよう
にしても良い。
Further, an intermediate electrode formed by using the same material as the electrode may be provided at a portion where each of the resistors intersects.

【0017】また、前記第1の抵抗体と前記第2の抵抗
体とが交差する部分に前記電極と同材質を用いて形成さ
れた中間電極を備えるようにしても良い。
Further, an intermediate electrode formed of the same material as the electrode may be provided at a portion where the first resistor and the second resistor intersect.

【0018】また、前記第1の抵抗体と前記第2および
第3の抵抗とが交差する部分に前記電極と同材質を用い
て形成された中間電極を備えるようにしても良い。
Further, an intermediate electrode formed of the same material as the electrode may be provided at a portion where the first resistor intersects with the second and third resistors.

【0019】更に、各前記電極に隣接して配設された複
数の副電極と、前記中間電極と各前記副電極とをそれぞ
れ接続する複数のパターンとを備えるようにしても良
い。
[0019] Further, a plurality of sub-electrodes arranged adjacent to each of the electrodes and a plurality of patterns for connecting the intermediate electrode and each of the sub-electrodes may be provided.

【0020】[0020]

【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。図1は本発明の第1の実施例
を示す(a)平面図、(b)断面図、(c)等価結線
図、図2は第2の実施の形態例を示す平面図、図3は第
3の実施の形態例を示す平面図、図4は第4の実施の形
態例を示す(a)平面図、(b)等価結線図である。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of the present invention, (a) a plan view, (b) a sectional view, (c) an equivalent connection diagram, FIG. 2 is a plan view showing a second embodiment, and FIG. FIG. 4 is a plan view showing the third embodiment, and FIG. 4 (a) is a plan view showing the fourth embodiment, and FIG. 4 (b) is an equivalent connection diagram.

【0021】先ず図1について第1の実施の形態例を説
明する。図1(a)、(b)に示すように本抵抗器は、
正4辺形のセラミック基板2と、セラミック基板2の各
辺に配設された4個の電極1a〜1dと、相対する各2
辺の電極、即ち電極1a、1cおよび電極1b、1c間
に互に中間点を交差するように形成された同一抵抗値の
2つの抵抗体3a、3bと、抵抗体3a、3bを保護す
る絶縁体で形成された保護コート4とで構成されてい
る。
First, a first embodiment will be described with reference to FIG. As shown in FIGS. 1A and 1B, this resistor is
A regular quadrilateral ceramic substrate 2 and four electrodes 1 a to 1 d disposed on each side of the ceramic
Two resistors 3a, 3b having the same resistance value formed so as to intersect the middle point between the electrodes on the sides, that is, the electrodes 1a, 1c and the electrodes 1b, 1c, and insulation for protecting the resistors 3a, 3b And a protective coat 4 formed of a body.

【0022】図1(c)に示すように本抵抗器は、電極
1a−1b,電極1a−1d,電極1c−1dの何れの
電極内でも抵抗体3aあるいは3bの示す抵抗値とな
る。即ち、抵抗体3a、3bは同一抵抗値があり、その
中間点で交差しているので何れの電極間でも同じ抵抗値
を示す抵抗器となる。従ってこの抵抗器を回路基板に搭
載して使用する時に、回路基板側のパターンの輻輳状況
を見てもっとも配線し易い位置にある電極間を6通りの
中から選んで配線することができる。
As shown in FIG. 1 (c), the resistance value of the resistor 3a or 3b is shown in any one of the electrodes 1a-1b, 1a-1d and 1c-1d. That is, since the resistors 3a and 3b have the same resistance value and intersect at the intermediate point, the resistors 3a and 3b exhibit the same resistance value between any two electrodes. Therefore, when the resistor is mounted on a circuit board and used, the congestion of the pattern on the circuit board side can be checked and the wiring at the position where the wiring is most easily selected can be selected from among six types.

【0023】尚、本実施例は正4辺形のセラミック基板
を用いたが正6辺形などの多辺形セラミック基板を用い
て電極数を更に増加させるようにしても良く、このよう
にすればパターン設計の自由度が更に拡大する。
In this embodiment, a regular quadrilateral ceramic substrate is used. However, a polygonal ceramic substrate such as a regular hexagon may be used to further increase the number of electrodes. If this is the case, the degree of freedom in pattern design is further expanded.

【0024】次に図2を参照して第2の実施の形態例を
説明する。図1の実施例との相違はセラミック基板に短
形のセラミック基板を用いた点にある。即ち短形のセラ
ミック基板22と、セラミック基板22の各辺に配設さ
れた4個の電極21a〜21dと、相対的短辺の電極2
1b−21d間に形成された抵抗体23aと、相対する
長辺の電極21a−21c間に形成された抵抗体23a
の中間点と傾斜して交差し、かつ抵抗体23aと同じ長
さの抵抗体23bとで構成される。尚、抵抗体23aと
抵抗体23bとが交差する部分は、それぞれの図中鎖線
で示した中心線がその中心点で傾斜して交差し、かつ中
心線の長さが同じ長さであるという意味である。この第
2の実施例は図1の実施例と同様に任意の電極間の抵抗
体を選んで使用することができるが、更に図1のものよ
りセラミック基板の面積を小さくできる特徴がある。
Next, a second embodiment will be described with reference to FIG. The difference from the embodiment of FIG. 1 is that a short ceramic substrate is used as the ceramic substrate. That is, the short ceramic substrate 22, the four electrodes 21 a to 21 d disposed on each side of the ceramic substrate 22, and the electrodes 2 on the relatively short side
1b-21d and a resistor 23a formed between opposing long-side electrodes 21a-21c.
And a resistor 23b having the same length as the resistor 23a. It is to be noted that the portion where the resistor 23a and the resistor 23b intersect is such that the center line indicated by the chain line in each figure intersects at a slant at the center point, and the length of the center line is the same length. Meaning. The second embodiment can select and use an arbitrary resistor between the electrodes as in the embodiment of FIG. 1, but has a feature that the area of the ceramic substrate can be made smaller than that of FIG.

【0025】次に図3を参照して第3の実施の形態例を
説明する。図2の実施例との相違は短形のセラミック基
板の長辺に1個づつの電極を追加し、抵抗体を更に1本
追加した点にある。即ち、短形セラミック基板32と、
短形セラミック基板32の短辺に1個づつ、また長辺に
2個づつ配設された6個の電極31a〜31bと、相対
する短辺の電極31b−31c間に形成された抵抗体3
3aと、それぞれ斜め方向に相対する2組みの電極31
a−31d,31b−31e間にそれぞれ形成された抵
抗体33aの中間点と傾斜して交差し、かつ抵抗体33
aと長さが同じの抵抗体33b、33cとで構成されて
いる。尚、抵抗体33aと抵抗体33b、33cとの交
差は、図中鎖線で示した中心線がそれぞれの中間点で傾
斜して交差し、かつ中心線の長さが同じであるという意
味である。この第3の実施例は図3の実施例と同様な特
徴を有するが、更に電極数が増加しているのでこの分パ
ターン設計の自由度が拡大する特徴がある。
Next, a third embodiment will be described with reference to FIG. The difference from the embodiment of FIG. 2 is that one electrode is added to the long side of the short ceramic substrate and one resistor is further added. That is, the short ceramic substrate 32,
Six electrodes 31a-31b, one on the short side and two on the long side of the short ceramic substrate 32, and the resistor 3 formed between the electrodes 31b-31c on the opposite short side.
3a and two sets of electrodes 31 which are respectively obliquely opposed to each other
a-31d, 31b-31e, each of which intersects at an angle with an intermediate point of a resistor 33a formed between the resistors 33a and 31b.
It is composed of resistors 33b and 33c having the same length as a. The intersection of the resistor 33a and the resistors 33b and 33c means that the center lines indicated by chain lines in the figure intersect at an inclination at their respective intermediate points, and the lengths of the center lines are the same. . The third embodiment has the same features as the embodiment of FIG. 3, but has a feature that the degree of freedom in pattern design is increased by the increased number of electrodes.

【0026】尚、図1〜図3で示した各実施例におい
て、抵抗体が交差する部分を各辺に形成して電極を同じ
材質を用いて電極化しても良い。例えば図1で示せば抵
抗体3aと3bとが交差する点線で囲んだ部分を電極化
する。このようにすれば電極1a−1b間で使用した時
の抵抗体3a、3bの面積に流れる電流の電流密度を平
均化できるので使用電力を大きくすることができる。
In each of the embodiments shown in FIGS. 1 to 3, a portion where the resistor intersects may be formed on each side, and the electrode may be formed of the same material. For example, in FIG. 1, a portion surrounded by a dotted line where the resistors 3a and 3b intersect is converted into an electrode. By doing so, the current density of the current flowing through the area of the resistors 3a and 3b when used between the electrodes 1a and 1b can be averaged, so that the power consumption can be increased.

【0027】次に図4を参照して第4の実施の形態例を
説明する。本実施例は図1の実施例に比べて抵抗体の交
差部分を電極化し、この中間電極と各辺に追加配設され
た副電極とをパターンで接続した点にある。即ち、図4
(a)に示すように正4辺形のセラミック基板42と、
各辺に配設された4個の主電極41a〜41dおよび4
個の副電極41a’〜41d’と、相対する2辺の電極
41a−41c間、および電極41b−41d間にそれ
ぞれ形成される抵抗体が交差する部分に配設された中間
電極41eと、この中間電極41eと各主電極41a〜
41dとの間に形成された抵抗体43a〜43dと、中
間電極41eと各副電極41a’〜41d’とをそれぞ
れ接続するパターンとで構成される。この抵抗器は図2
(b)に示す回路構成となるので、図1の実施例と比べ
て次のような特徴がある。主電極41a〜41dの任意
の2電極間で同一抵抗値の抵抗器として使用できる同時
に、各種電極41a〜41dと対応する副電極41a’
〜41d’との2電極間でも同様に同一抵抗値の抵抗体
として使用することができる。但し、この場合は主電極
間で使用する場合の1/2の抵抗値となる。また組み抵
抗器として2回路以上でも使用することができ、パター
ン設計上の自由度の拡大と同時に汎用性も拡大できると
いう特徴がある。尚、本実施例は正4辺形のセラミック
基板について説明したが、図2、図3で説明した短形セ
ラミック基板のものについても同様に適用することがで
きる。
Next, a fourth embodiment will be described with reference to FIG. This embodiment is different from the embodiment shown in FIG. 1 in that the intersection of the resistors is formed into an electrode, and the intermediate electrode and the sub-electrode additionally provided on each side are connected in a pattern. That is, FIG.
(A) As shown in FIG.
Four main electrodes 41a to 41d and 4 arranged on each side
A plurality of sub-electrodes 41a ′ to 41d ′, an intermediate electrode 41e disposed at a portion where resistors formed between two opposing electrodes 41a-41c, and between the electrodes 41b-41d intersect, respectively. The intermediate electrode 41e and each main electrode 41a-
The resistors 43a to 43d formed between the sub-electrodes 41a and 41d are connected to the intermediate electrodes 41e and the sub-electrodes 41a 'to 41d'. This resistor is shown in FIG.
The circuit configuration shown in FIG. 1B has the following characteristics as compared with the embodiment of FIG. Any two of the main electrodes 41a to 41d can be used as a resistor having the same resistance value, and at the same time, the sub-electrodes 41a 'corresponding to the various electrodes 41a to 41d.
Similarly, a resistor having the same resistance value can be used between the two electrodes 41d to 41d '. However, in this case, the resistance value is の of that when used between the main electrodes. Also, two or more circuits can be used as the assembled resistor, and the feature is that the versatility can be expanded at the same time as the degree of freedom in pattern design is expanded. Although the present embodiment has been described with reference to a regular quadrilateral ceramic substrate, the present invention can be similarly applied to the rectangular ceramic substrate described with reference to FIGS.

【0028】[0028]

【発明の効果】以上説明したように本発明の表面実装用
多極型抵抗器は、多辺形のセラミック基板の各辺に配設
した多電極の何れの2電極間でも同一抵抗値の抵抗器と
して使用できるので、回路基板側のパターン設計におい
て、位置的に配線に都合の良い2電極を選択して使用で
きるのでパターン設計の自由度が拡大するという効果が
ある。また、抵抗体が交差する部分に中間電極を設け、
これに接続される副電極を設けることにより、更に組み
抵抗器とを使用することができるので汎用性が拡大する
という効果がある。
As described above, the multi-pole type surface mount resistor of the present invention has the same resistance value between any two of the multi-electrodes arranged on each side of the multi-sided ceramic substrate. Since it can be used as a device, in the pattern design on the circuit board side, it is possible to select and use two electrodes that are convenient for wiring in terms of position, and thus there is an effect that the degree of freedom in pattern design is expanded. Also, an intermediate electrode is provided at a portion where the resistor intersects,
By providing the sub-electrode connected to this, it is possible to further use the assembled resistor, so that the versatility is expanded.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態例を示す(a)平面
図、(b)断面図、(c)等価結線図である。
FIG. 1A is a plan view, FIG. 1B is a cross-sectional view, and FIG. 1C is an equivalent connection diagram showing a first embodiment of the present invention.

【図2】本発明の第2の実施の形態例を示す平面図であ
る。
FIG. 2 is a plan view showing a second embodiment of the present invention.

【図3】本発明の第3の実施の形態例を示す平面図であ
る。
FIG. 3 is a plan view showing a third embodiment of the present invention.

【図4】本発明の第4の実施の形態例を示す(a)平面
図、(b)等価結線図である。
4A is a plan view and FIG. 4B is an equivalent connection diagram showing a fourth embodiment of the present invention.

【図5】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.

【図6】他の従来例を示す(a)外観斜視図、(b)展
開平面図である。
6A is an external perspective view showing another conventional example, and FIG. 6B is a developed plan view.

【符号の説明】[Explanation of symbols]

1a〜1d 電極 21a〜21d 電極 31a〜31b 電極 2、22、32 セラミック基板 3a、3b 抵抗体 23a、23b 抵抗体 33a、33c 抵抗体 41a〜41d 主電極 41a’〜41d’ 副電極 42 セラミック基板 43a〜43d 抵抗体 1a to 1d electrode 21a to 21d electrode 31a to 31b electrode 2, 22, 32 ceramic substrate 3a, 3b resistor 23a, 23b resistor 33a, 33c resistor 41a to 41d main electrode 41a 'to 41d' sub electrode 42 ceramic substrate 43a ~ 43d resistor

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 正n(偶数)辺形のセラミック基板と、
前記セラミック基板の各辺に1個づつ配設された複数の
電極と、相対する各2辺の前記電極間に互に中間点を交
差するように形成された複数の抵抗体とを備えることを
特徴とする表面実装用多極型抵抗器。
1. A positive n (even) side ceramic substrate,
A plurality of electrodes disposed one on each side of the ceramic substrate, and a plurality of resistors formed so as to intersect each other at an intermediate point between the electrodes on the opposite two sides. Characteristic multi-pole type resistors for surface mounting.
【請求項2】 短形のセラミック基板と、前記セラミッ
ク基板の各辺に1個づつ配設された4個の電極と、相対
する短辺の前記電極間に形成された第1の抵抗体と、相
対する長辺の前記電極間に形成された前記第1の抵抗体
の中間点と傾斜して交差しかつ前記第1の抵抗体と同じ
長さを有する第2の抵抗体とを備えることを特徴とする
表面実装用多極型抵抗器。
2. A short ceramic substrate, four electrodes disposed one on each side of the ceramic substrate, and a first resistor formed between the electrodes on opposite short sides. A second resistor having a length that is the same as the length of the first resistor, the second resistor intersects obliquely with an intermediate point of the first resistor formed between the electrodes on opposite long sides. A multi-pole type resistor for surface mounting, characterized by the following.
【請求項3】 短形のセラミック基板と、前記セラミッ
ク基板の短辺に1個づつまた長辺に2個づつ配設された
6個の電極と、相対する短辺の前記電極間に形成された
第1の抵抗体と、それぞれ斜め方向に相対する長辺の2
組みの前記電極間にそれぞれ形成された前記第1の抵抗
体の中間点と傾斜して交差しかつ前記第1の抵抗体と同
じ長さを有する第2および第3の抵抗体とを備えること
を特徴とする表面実装用多極型抵抗器。
3. A short ceramic substrate, six electrodes disposed one by one on a short side and two on a long side of the ceramic substrate, and are formed between the opposite short side electrodes. The first resistor and the two long sides opposed to each other in the oblique direction
A second resistor and a second resistor having the same length as the first resistor, which obliquely intersect with an intermediate point of the first resistor formed between the pair of electrodes; A multi-pole type resistor for surface mounting, characterized by the following.
【請求項4】 各前記抵抗体が交差する部分に前記電極
と同材質を用いて形成された中間電極を備えることを特
徴とする請求項1記載の表面実装用多極型抵抗器。
4. The multi-pole surface mount resistor according to claim 1, further comprising an intermediate electrode formed of the same material as the electrode at a portion where each of the resistors intersects.
【請求項5】 前記第1の抵抗体と前記第2の抵抗体と
が交差する部分に前記電極と同材質を用いて形成された
中間電極を備えることを特徴とする請求項2記載の表面
実装用多極型抵抗器。
5. The surface according to claim 2, wherein an intermediate electrode formed of the same material as the electrode is provided at a portion where the first resistor and the second resistor intersect. Multi-pole type resistors for mounting.
【請求項6】 前記第1の抵抗体と前記第2および第3
の抵抗とが交差する部分に前記電極と同材質を用いて形
成された中間電極を備えることを特徴とする請求項4記
載の表面実装用多極型抵抗器。
6. The first resistor and the second and third resistors.
The multi-pole resistor for surface mounting according to claim 4, further comprising an intermediate electrode formed by using the same material as the electrode at a portion where the resistance intersects.
【請求項7】 各前記電極に隣接して配設された複数の
副電極と、前記中間電極と各前記副電極とをそれぞれ接
続する複数のパターンとを備えることを特徴とする請求
項4、5あるいは6記載の表面実装用多極型抵抗器。
7. The semiconductor device according to claim 4, further comprising: a plurality of sub-electrodes disposed adjacent to each of said electrodes; and a plurality of patterns for respectively connecting said intermediate electrode and each of said sub-electrodes. 7. A multi-pole resistor for surface mounting according to 5 or 6.
JP2001146884A 2001-05-16 2001-05-16 Multi-electrode type resistor for surface mounting Pending JP2002343614A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001146884A JP2002343614A (en) 2001-05-16 2001-05-16 Multi-electrode type resistor for surface mounting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001146884A JP2002343614A (en) 2001-05-16 2001-05-16 Multi-electrode type resistor for surface mounting

Publications (1)

Publication Number Publication Date
JP2002343614A true JP2002343614A (en) 2002-11-29

Family

ID=18992455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001146884A Pending JP2002343614A (en) 2001-05-16 2001-05-16 Multi-electrode type resistor for surface mounting

Country Status (1)

Country Link
JP (1) JP2002343614A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7277006B2 (en) 2005-11-30 2007-10-02 Kabushiki Kaisha Toshiba Chip resistor
CN108806902A (en) * 2017-04-27 2018-11-13 三星电机株式会社 Chip resistor and plate resistor device assembly
US10170223B2 (en) 2016-11-15 2019-01-01 Samsung Electro-Mechanics Co., Ltd. Chip resistor and chip resistor assembly

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7277006B2 (en) 2005-11-30 2007-10-02 Kabushiki Kaisha Toshiba Chip resistor
US10170223B2 (en) 2016-11-15 2019-01-01 Samsung Electro-Mechanics Co., Ltd. Chip resistor and chip resistor assembly
CN108806902A (en) * 2017-04-27 2018-11-13 三星电机株式会社 Chip resistor and plate resistor device assembly
US10559648B2 (en) 2017-04-27 2020-02-11 Samsung Electro-Mechanics Co., Ltd. Chip resistor and chip resistor assembly
CN108806902B (en) * 2017-04-27 2021-01-12 三星电机株式会社 Chip resistor and chip resistor assembly

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