JP2002324853A - Method for forming capacitor of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for forming a capacitor of a semiconductor device capable of suppressing deterioration of device characteristics due to a residue produced in a process for forming a storage node. SOLUTION: The capacitor forming method is provided with a stage for forming an insulation layer having a contact hole on a substrate and forming a conductive layer in the contact hole, a stage for forming a first metal layer on the whole face including the conductive layer, a stage for selectively etching a dummy pattern layer and an etching barrier layer after they are formed on a first metal layer and forming a lower electrode forming area, a stage for forming a second metal layer by regarding the first metal layer as a seed on the lower electrode forming area, a stage for performing a wet type cleaning process for removing the residue produced in a removing process after removing the etching barrier layer and the dummy pattern layer, and a stage for removing the exposed first metal layer to form a lower electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of a semiconductor device, and more particularly to a semiconductor device capable of suppressing a decrease in device characteristics due to a residue generated in a step of forming a storage node of a capacitor. The present invention relates to a method for forming a capacitor.

[0002]

2. Description of the Related Art Generally, in order to form a DRAM, a cell transistor is formed on a substrate, the surface thereof is covered with an insulating layer, and a capacitor is formed on the insulating layer. At this time, in order to electrically connect the capacitor and the transistor, a contact hole is formed in the insulating layer, a conductive plug is filled therein, and the plug is connected to the lower electrode of the capacitor. In forming the capacitor, an ECD (Electro-Chemical Deposition) Pt process is often used, but in the process of manufacturing the DRAM capacitor, the profile at the time of etching the dummy pattern layer for forming the storage node of the capacitor is improved. Next, an SiON film is deposited on the dummy pattern layer. The SiON film functions as an etching barrier layer and improves the vertical profile of the dummy pattern layer. Then, the SiON film is removed by a dry etching process in order to remove the dummy pattern layer performed after the ECD Pt deposition.

Hereinafter, a conventional process for forming a capacitor of a semiconductor device will be described with reference to the accompanying drawings.

FIGS. 1A to 1E are sectional views illustrating a process for forming a capacitor of a conventional semiconductor device. And
FIG. 2A is a photograph showing the form of the storage node after etching back the etching barrier layer, and FIG. 2B is a photograph showing the form of the storage node after wet deep-out of the dummy pattern layer.

First, as shown in FIG. 1A, an insulating layer 11 and a surface antireflection film 12 are sequentially formed on a semiconductor substrate (not shown) on which a cell transistor (not shown) is formed. A capacitor is formed on the insulating layer 11. A contact hole for electrically connecting a lower electrode of the capacitor and one electrode of the cell transistor is formed. In the contact hole, a doped polysilicon layer is
The plug layer 13 is formed by depositing and etching back in a VD process, and at this time, the plug layer 13 is deeply etched back so as to form a recess at the upper end.

Next, a low-resistance contact layer 14 for reducing the contact resistance between the plug layer 13 and a barrier layer formed in a subsequent step is formed on the plug layer 13 in the recess portion, and a barrier layer 15 is formed thereon. Form. Here, the low resistance contact layer 14 is formed by depositing a material such as Ti on silicon, converting the material to silicide (TiSix) in a heat treatment process, and removing unreacted Ti. And the barrier layer 1
5 is formed so as to be formed on the entire surface including the portion where the low-resistance contact layer 14 is formed, and then flattened to remain only on the low-resistance contact layer 14. At this time, it is desirable that the surface of the barrier layer 15 be flush with the surface of the reflective hat film 2.

After the barrier layer is formed as described above, a first metal layer 16 as a seed layer is formed on the entire surface using Pt. Then, as shown in FIG. 1B, a dummy pattern layer 17 for patterning the storage node is formed on the entire surface.
Then, an etching barrier layer 18 is formed. Here, the etching barrier layer 18 uses SiON. Then, as shown in FIG. 1C, the dummy pattern layer 17 and the etching barrier layer 18 are selectively etched by a photolithography process to form a lower electrode formation region 19 of the capacitor. The etching barrier layer 18 is provided to improve the etching profile of the dummy pattern layer 17 during the etching. The etched portion of the dummy pattern layer 17 is a storage node formation region.

Next, as shown in FIG. 1D, a second metal layer 20 is formed using the first metal layer 16 exposed in the storage node formation region, that is, the portion where the dummy pattern layer 17 has been removed, as a seed layer. The step of forming the second metal layer 20 is performed by an ECD step.

As shown in FIG. 1E, the etching barrier layer 18 is removed by a wet etching process, and the dummy pattern layer 17 is removed by a wet deep-out method. Thus, a lower electrode is formed by the second metal layer 20. Accordingly, the second metal layer 20 as the lower electrode is, of course, the plug 1
It overlaps with 3.

In the prior art performed in such an order,
At the time of the dry etching step for removing the SiON used as the etching barrier layer 18, blanket etching is performed without using a photomask. At this time, since the dry etching gas also affects the upper surface of the Pt lower electrode, a residue containing Pt is generated. Such a residue remains even after the wet-deep-out of the dummy pattern layer, and if the subsequent process is performed as it is, it may cause the electrical characteristics of the device to deteriorate.

FIGS. 2A and 2B show photographs showing the residual residue. FIG. 2A is a photograph showing a state of a storage node portion after etch back of an etching barrier layer, and FIG. 2B is a photograph showing a state where a residue remains after a wet deep out of a dummy pattern layer.
As can be seen from FIG. 2B, a large amount of residue generated in the etch back process of the etching barrier layer remains.

[0012]

However, there are the following problems in the formation of the capacitor of the above-mentioned prior art semiconductor device. Residue generated at the time of removing the etching barrier layer used to secure the vertical profile of the dummy pattern layer for forming the storage node remains even after the removal of the dummy pattern layer, and deteriorates the electrical characteristics of the device. In particular, the subsequent deposition of the BST dielectric layer becomes non-uniform, the capacitance between cells becomes non-uniform,
Partial loss of applied current occurs.

The present invention has been made in order to solve the problem of the conventional capacitor forming process, and a method of forming a capacitor of a semiconductor device which can suppress the deterioration of the device characteristics due to the residue generated in the process of forming a storage node. The purpose is to provide.

[0014]

According to the present invention, there is provided a method of forming a capacitor of a semiconductor device, comprising forming an insulating layer having a contact hole on a substrate, and forming a conductive layer in the contact hole. And forming a first metal layer on the entire surface of the substrate on which the conductive layer has been formed.
Forming a dummy pattern layer and an etching barrier layer on the first metal layer, and selectively exposing the lower electrode formation region to expose the first metal layer; and exposing the first metal layer to the lower electrode formation region. Forming a second metal layer in the lower electrode formation region using as a seed, an etching barrier layer,
After the dummy pattern layer is removed, a step of performing a wet cleaning step for removing residues generated in these removal steps, and a step of removing the exposed first metal layer to form a lower electrode are provided. It is characterized by.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for forming a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

FIGS. 3A to 3H are cross-sectional views illustrating a process for forming a capacitor of a semiconductor device according to the present invention. FIG. 4 is a photograph showing a form of a storage node after removing a residue using a wet cleaning process according to the present invention.

The present invention is characterized in that a residue generated during a process of forming a storage node is removed by a wet cleaning process, and then a subsequent process is performed. Here, the cleaning solution used in the wet cleaning process reacts with the residue containing the components of the lower electrode forming material layer and can remove the same.

Hereinafter, embodiments of the present invention will be described specifically. First, as shown in FIG. 3A, an insulating layer 31 and a surface anti-reflection film 32 are sequentially formed on a semiconductor substrate (not shown) on which a number of cell transistors (not shown) are formed. A contact hole for connecting to the electrode is formed. Here, the insulating layer 31 is formed of an oxide film, and the surface antireflection film 32 is formed of a material having a high etching selectivity with respect to the oxide film, for example, a nitride film.
It is formed to a thickness of 0 to 1000 mm.

A conductive layer is formed in the contact hole in the same manner as in the prior art. The formation process is as follows.

First, a polysilicon layer doped by a CVD process is deposited in a contact hole, and the polysilicon layer is etched back deeply so as to form a recess in the contact hole, thereby forming a plug layer 33. The recess is formed at a depth of 500 to 1500 °.

Next, the plug layer 3 formed in the recessed portion is formed.
A low-resistance contact layer 34 and a barrier layer 35 for reducing the contact resistance between the layer 3 and a barrier layer formed in a subsequent step are formed on the plug layer 33 in the recess. Here, the low-resistance contact layer 34 is formed by evaporating a material such as Ti to a thickness of 100 to 300 °, silicifying it by a heat treatment process such as RTP (Rapid Thermal Process), and then reacting without reacting.
i is formed by removing in a wet process.

The barrier layer 35 is made of TiN or a three-component diffusion prevention film of TiSiN, TiAlN, TaSiN.
After one of N and TaAlN is formed on the entire surface including the portion where the low resistance contact layer 34 is formed by a PVD or CVD process, it is planarized by a CMP process and formed so as to remain only on the low resistance contact layer 34. I do.

Next, Pt is deposited on the entire surface to a thickness of 50 to 1000 ° to form a first metal layer 36 as a seed layer. This first metal layer 36 is made of P having excellent etching characteristics.
t, Ru, Ir, Os, W, Mo, Co, Ni,
It can also be formed using either Au or Ag.

Then, as shown in FIG. 3B, a dummy pattern layer 37 and an etching barrier layer 38 for forming a storage node are formed on the entire surface. Here, the dummy pattern layer 37 and the etching barrier layer 38 are made of a material that increases the etching selectivity to each other. Preferably, the dummy pattern layer 37 is made of photoresist or CV.
A D oxide film is formed to a thickness of 5000-10000 °, and the etching barrier layer 38 is made of SiON of 100-1000 °.
Formed to a thickness of The dummy pattern layer 37 and the etching barrier layer 38 formed on the entire surface of the substrate in this manner are selectively etched to remove the dummy pattern layer 37 and the etching barrier layer 38 from the lower electrode formation region 39 as shown in FIG.
Is removed to expose the first metal layer 36 at the bottom thereof.

Next, after performing a pre-cleaning process for depositing the first metal layer by the ECD process, as shown in FIG. 3D, the lower electrode forming region 39, ie, the barrier layer 38 and the dummy insulating layer 37 are removed. Exposed first metal layer 36
Is used as a seed layer, a first metal layer is deposited by an ECD process to form a second metal layer 40. Here, the current density during the ECD process is in the range of 0.1 to 10 mA / cm ² , and the power used is a DC power or a pulse or reverse pulse method.

The second metal layer 40 is not formed in the lower electrode forming region 39 to the same height as the upper surface of the dummy insulating layer 37 but is formed lower than the same. As shown in FIG. 3e,
The etching barrier layer 38 above the dummy pattern layer 37 is removed by a dry etching step, and the dummy pattern layer 3 is removed.
7 is removed by a wet deep-out method. Here, the wet deep-out method uses HF or a mixed solution of HF / NH ₄ F.

In the step of removing the etching barrier layer 38, a residue is generated as in the conventional case, and the residue is removed in the next step. That is, a large amount of residue containing the components of the second metal layer 40 is generated in the step of removing the etching barrier layer 38, and a cleaning solution capable of reacting with the residue and removing the residue is used.
Perform a wet cleaning process.

Preferably, the mixture ratio of H ₂ SO ₄ : H ₂ O ₂ is 1: 0.1 to 1: 100, and the treatment temperature is 4 to 100.
C. and dipping time is 2-3600 seconds. More preferably, the mixing ratio is 4: 1, and the dipping is performed for 5 minutes. The cleaning solution is H ₂ SO ₄ : H ₂
In addition to O ₂ , diluted H ₂ SO ₄ , NH ₄ OH / H ₂ O ₂ /
H ₂ O mixed solution, HF / H ₂ O mixed solution, HF / HN ₄ F
It is also possible to use any of the mixed solutions alone or to use them in appropriate combinations. FIG. 4 shows the substrate from which the residue has been removed in the cleaning step.

Next, as shown in FIG. 3F, the lower electrode 41 is formed by removing the first metal layer 36 by a dry etch back process. Then, as shown in FIG. 3G, a dielectric layer 42 is formed by depositing a high dielectric material, for example, BST, on the entire surface at a temperature of 400 to 600 ° C. and a thickness of 150 to 500 ° in a CVD process. Next, the dielectric layer 42 is crystallized by a RTP process in a nitrogen atmosphere at 500 to 700 ° C. for 30 to 180 seconds to improve the dielectric characteristics.

Then, as shown in FIG. 3H, Pt is deposited on the dielectric layer 42 using a CVD process, and is selectively patterned to form a capacitor upper electrode 43.

In the capacitor forming process according to the present invention, the residue generated when the etching barrier layer is removed to secure the vertical profile of the dummy pattern layer for forming the storage node is completely removed as shown in FIG. After that, a subsequent process is performed, so that the characteristics of the element can be improved.

The present invention is not limited to the above embodiments, but can be modified by those skilled in the art according to the technical concept within the scope of the claims.

[0033]

The method for forming a capacitor of a semiconductor device according to the present invention has the following effects. Residue generated at the time of removing an etching barrier layer used for securing a vertical profile of a dummy pattern layer for forming a storage node can be completely removed. This makes the subsequent deposition of the BST dielectric layer uniform and makes the intercell capacitance uniform. In addition, by completely removing such a residue, the loss of the applied current that is partially generated is suppressed, and the electrical characteristics are improved. In particular, since a high-stack type Pt storage node can be formed even with a device of 0.1 μm or less, the BST
Can be improved as a dielectric film.

[Brief description of the drawings]

FIG. 1a is a process sectional view for forming a capacitor of a conventional semiconductor device.

FIG. 1b is a sectional view showing a process for forming a capacitor of a conventional semiconductor device.

FIG. 1c is a process sectional view for forming a capacitor of a conventional semiconductor device.

FIG. 1d is a process sectional view for forming a capacitor of a semiconductor device according to the related art.

FIG. 1e is a sectional view showing a process for forming a capacitor of a conventional semiconductor device.

FIGS. 2A and 2B are a photograph (a) showing a form of a storage node after etch back of an etching barrier layer and a photograph (b) showing a form of a storage node after wet deep-out of a dummy pattern layer.

FIG. 3a is a sectional view illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

FIG. 3b is a sectional view illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

FIG. 3c is a sectional view illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

3A to 3D are cross-sectional views illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

FIG. 3e is a sectional view illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

FIG. 3f is a sectional view illustrating a process for forming a capacitor of the semiconductor device according to the present invention;

FIG. 3g is a sectional view illustrating a process for forming a capacitor of the semiconductor device according to the present invention;

FIG. 3h is a sectional view illustrating a process for forming a capacitor of a semiconductor device according to the present invention;

FIG. 4 is a photograph showing a form of a storage node after a residue is removed using a wet cleaning process according to the present invention.

[Explanation of symbols]

31: insulating layer 32: surface antireflection film 33: plug layer 34: low-resistance contact layer 35: barrier layer 36: first
Metal layer 37: Dummy pattern layer 38: Etching barrier layer 39: Lower electrode formation region 40: Second
Metal layer 41: Lower electrode 42: Dielectric layer 43: Upper electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 BB40 CC01 DD16 DD17 DD43 DD52 DD84 FF22 GG16 5F083 AD56 JA14 JA38 JA39 JA40 PR34 PR39

Claims (7)

[Claims] An insulating layer having a contact hole is formed on a substrate, a conductive layer is formed in the contact hole, and a first metal layer is formed on the entire surface of the substrate having the conductive layer formed in the contact hole. Forming, after forming a dummy pattern layer and an etching barrier layer on the first metal layer, selectively etching them to remove the dummy pattern layer and the etching barrier layer in a lower electrode formation region; Forming a second metal layer using the first metal layer exposed in the lower electrode formation region from which the dummy pattern layer and the etching barrier layer have been removed; and forming an etching barrier remaining after forming the second metal layer. Performing a wet cleaning step of removing the layer and the dummy pattern layer and removing residues generated in these removing steps; A capacitor forming a semiconductor device characterized by comprising the steps of forming a lower electrode on a substrate by removing the first metal layer Chingubaria layer and the dummy pattern layer is exposed by removing the. 2. The method as claimed in claim 1, wherein the lower electrode formation region overlaps at least a part of the conductive layer formed in the contact hole. 3. The capacitor of claim 1, wherein the cleaning solution used in the wet cleaning process reacts with a residue containing the second metal layer component to remove the second metal layer component. Forming method. 4. H ₂ SO ₄ : H during a wet cleaning step.
4. A capacitor for a semiconductor device according to claim 3, wherein the mixing ratio of ₂ O ₂ is 1: 0.1 to 1: 100, the processing temperature is 4 to 100 ° C., and the dipping time is 2 to 3600 seconds. Method. 5. The wet cleaning step includes a step of diluting H ₂ S
O ₄ , NH ₄ OH / H ₂ O ₂ / H ₂ O mixed solution, HF / H ₂ O
_{4. The} method according to claim 3, wherein one of the mixed solution and the HF / HN4F mixed solution is used alone or in combination. 6. The method according to claim 1, wherein the etching barrier layer is removed by a dry etching process, and the dummy pattern layer is removed by a wet deep-out method. 7. A step of sequentially forming an insulating layer and a surface anti-reflection film on the entire surface including the cell transistor and selectively etching them to form a contact hole; Forming a resistive contact layer and a barrier layer in order; and depositing Pt on the entire surface to form a first layer used as a seed layer.
Forming a metal layer, forming a dummy pattern layer and an etching barrier layer on the entire surface of the substrate on which the first metal layer is formed, and selectively etching them to form a lower electrode formation region; The first metal layer exposed at the bottom of
Forming a second metal layer by depositing Pt in a CD process; removing the etching barrier layer and the dummy pattern layer; and reacting with a residue containing the second metal layer component to remove the second metal layer. Performing a wet cleaning process, removing the etching barrier layer and the dummy pattern layer and removing the exposed first metal layer to form a lower electrode, and depositing BST on the entire surface. A method for forming a capacitor of a semiconductor device, comprising: forming and crystallizing a dielectric film; and depositing and selectively patterning Pt on the dielectric film to form an upper electrode.