JP2002324843A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a capacitor for noise reduction measure superior in transition response at excellent yield. SOLUTION: A capacitor insulation film CZ is formed by accumulating a silicon nitride film on wiring Ma applying power source electric potential (VDD) and wiring Mb applying ground electric potential (GND), tungsten films are accumulated on the capacitor insulation film CZ, and a floating electrode FE is formed by etching. The floating electrode FE is extended on the wirings Ma, Mb in a divided state. Power source noise can be reduced with capacitors Ca1 , Ca2 comprising the wirings Ma, Mb, the capacitor insulation film CZ and the floating electrode FE. In addition, since the floating electrode FE is divided, the yield can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the same, and more particularly to a technique effective when applied to forming a capacitance for reducing noise on wiring.

[0002]

2. Description of the Related Art Semiconductor elements constituting a semiconductor integrated circuit are connected via wiring. Since various noises can be applied to this wiring, the influence of this noise is reduced,
It is necessary to ensure the operation accuracy of the integrated circuit, for example, the operation speed.

In particular, when an input / output circuit is switched, noise is likely to be generated in a wiring (power supply wiring or ground wiring) for supplying a power supply potential (VDD) or a ground potential (GND), which hinders a desired circuit operation. Was.

As a measure for reducing such noise, a MOS (Metal Oxide Semiconductor) is provided between a power supply wiring and a ground wiring.
A method of connecting a capacitor (decoupling capacitor) having an uctor structure, for example, a method of connecting a source / drain region of a MOS transistor to a ground wiring and connecting a power supply wiring to a gate electrode of the MOS transistor has been adopted. This MOS capacitor can be formed in the same manner as a MOS transistor forming a semiconductor integrated circuit.

[0005] For the MOS capacitor as described above, for example, IBM J. RES. DEVELOP. VOL. 41 NO.
ULY / SEPTEMBER 1977 P489-501, JP-A-7-13530
No. 1 and JP-A-10-12825. The MOS capacitors described in these publications are formed on the outer periphery of the chip, and are also disclosed in IBM J. RES.D.
EVELOP. VOL. 41 NO. 4/5 JULY / SEPTEMBER 1977 P489-5
The MOS capacitor described in 01 is connected with a fuse for a countermeasure when a defect occurs in the gate oxide film.

On the other hand, an SRAM (Static Random Access M)
emory) In a memory cell, a method of adding capacitance to the memory cell has been adopted to reduce soft errors due to α rays. Soft error due to α-rays means that α-rays contained in external cosmic rays and α-rays emitted from radioactive atoms contained in LSI package material enter a memory cell and are stored in the memory cell. It is a phenomenon that destroys information.

For example, an SRAM memory cell has a flip-flop circuit for storing 1-bit information and two information transfer MISFETs (Metal Insulator Semiconductor Fiscal).
eldEffect Transistor).

The capacity is added to the information storage section (input / output section of the flip-flop circuit) in the memory cell to reduce the soft error due to α rays.

[0009] The capacity of the information storage unit as described above is described in, for example, IEDM 1988 P205.

[0010]

However, when a capacitor having a MOS structure is used to reduce noise, a capacitor is formed by the gate electrode, the gate insulating film, and the inversion layer in the semiconductor substrate. This inversion layer has a large sheet resistance and a poor transient response.

Further, by forming such a MOS capacitor, a region where a MOS transistor constituting a semiconductor integrated circuit is formed is limited. Further, when a defect occurs in the gate insulating film (oxide film) constituting the MOS capacitor, the wiring is short-circuited. Therefore, it is necessary to prepare the above-described fuse for the measure against the defect.

On the other hand, even when a capacity is added to the information storage section in the SRAM memory cell, the above-mentioned IEDM 1
In the process flow as shown in FIG. 6 of 988, a lower electrode (LE), an upper electrode (UE), and a through hole for connecting each of these electrodes to a source / drain electrode must be formed ( The detailed steps will be described later. In these steps, a mask is used.
The number of processes is required, and the number of processes increases. In addition, since the through holes for connecting the lower electrode (LE) and the source and drain electrodes are provided by etching the capacitor insulating film, during this etching (including the photolithography step), The quality will be degraded. As a result, defects easily occur in the capacitance insulating film,
Yield decreases.

An object of the present invention is to provide a semiconductor integrated circuit device having a capacitor for noise reduction measures having a good transient response. Another object of the present invention is to provide a semiconductor integrated circuit device having a high yield and a high degree of integration.

Another object of the present invention is to reduce steps for forming a capacitor of a semiconductor integrated circuit device. Another object is to improve the reliability of the semiconductor integrated circuit device and improve the yield.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device of the present invention has a conductive film formed on a power supply wiring and a ground wiring of a semiconductor integrated circuit device so as to extend through an insulating film, and the conductive film Is formed of a floating conductive film that is not electrically connected to the power supply wiring and the ground wiring.

(2) The semiconductor integrated circuit device according to the present invention is a power supply wiring and a ground wiring of the semiconductor integrated circuit device,
A conductive film formed on these wirings extending in the first direction so as to extend through an insulating film, wherein the conductive film is moved in a second direction orthogonal to the first direction; , A floating conductive film divided into a plurality of parts and arranged.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a first conductive film is deposited on a semiconductor substrate;
Forming a power supply wiring and a ground wiring which run in parallel by patterning; forming an insulating film on the power supply wiring and the ground wiring;
Forming a floating electrode extending on the power supply wiring and the grounding wiring via the insulating film by depositing and patterning the conductive film. The floating electrode may be formed so as to be divided into a plurality of parts in a second direction orthogonal to the first direction in which the power supply wiring and the ground wiring extend.

(4) The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, The pair of n
An interlayer insulating film formed on the channel type MISFET;
A first and a second conductive layer for connecting a gate electrode and a drain of the pair of n-channel MISFETs; a capacitor insulating film formed on the first and second conductive layers; And a third formed on the first and second conductive layers via the capacitor insulating film.
And a conductive layer of

(5) The method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected. Forming a pair of n-channel MISFETs; and forming first and second conductive films extending from above a gate electrode to a drain of the pair of n-channel MISFETs. Forming a capacitive insulating film on the first and second conductive layers, forming a third conductive film on the capacitive insulating film, and forming a floating electrode by patterning; Having.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) Next, a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. 1 to 6 are cross-sectional views of a main part showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, as shown in FIG. 1, a semi-MISFE is formed on a main surface of a semiconductor substrate 1 made of, for example, single crystal silicon.
A semiconductor element (not shown) such as T is formed, and C
After depositing a silicon oxide film by VD (Chemical Vapor deposition) method, CMP (Chemical Mechanical Poli
The surface is flattened by polishing with a shing) method to form an interlayer insulating film TH.

Next, a contact hole (not shown) is formed by etching the interlayer insulating film TH. Next, a plug (not shown) is formed by embedding, for example, a tungsten film in the contact hole.

Next, a titanium nitride film (not shown), an aluminum film and a titanium nitride film (not shown) are sequentially deposited on the interlayer insulating film TH by, for example, a sputtering method, and are patterned into a desired shape. Wirings Ma and Mb made of a metal film that is a conductive film are formed. Here, for example, the wiring Ma is connected to the power supply potential (VDD) via a wiring or plug (not shown), and the wiring Mb is connected to the ground potential (GND) via a wiring or plug (not shown). Since these wirings (Ma, Mb) are so-called power supply wirings, the wiring widths are almost equal, and several tens μm,
Designed to be thicker than other wiring.

Next, as shown in FIG. 2, a silicon nitride film having a thickness of about 10 nm is deposited on the interlayer insulating film TH including the wirings Ma and Mb by, for example, a plasma CVD method to form a capacitor insulating film (dielectric material). Film) CZ is formed.
Here, the power supply voltage (VD
Since a voltage of 1/2 of D) is applied, the thickness of the insulating film forming the capacitor insulating film CZ is set so as to withstand this voltage. The capacitor insulating film CZ may be formed by depositing a material having a high dielectric constant such as a tantalum oxide film (Ta ₂ O ₅ ) in addition to the silicon nitride film. As described above, when a material having a high dielectric constant is used for the capacitor insulating film, the capacitance can be increased.

Next, as shown in FIG. 3, a tungsten film W having a thickness of about 100 nm is deposited on the capacitor insulating film CZ by, for example, a sputtering method.

Next, as shown in FIG. 4, the tungsten film W is etched using a resist film (not shown) on the tungsten film W, which is a conductive film or a metal film, as a mask to form a floating electrode (floating conductive film). Alternatively, a floating electrode FE is formed. This floating electrode FE
Are not electrically connected to the lower wiring Ma and the wiring Mb and the upper wiring.

FIG. 5 is a plan view of the semiconductor substrate 1 after the formation of the floating electrode FE. As shown in FIG. 5, the floating electrode FE extends on the wires Ma and Mb in a divided state. Here, the plurality of divided floating electrodes are referred to as a unit electrode UE, and the unit electrode UE, the capacitor insulating film CZ, and the wiring (M
The capacitor composed of a and Mb) is called a unit capacitor UC.

Thereafter, a semiconductor integrated circuit device having a plurality of wiring layers is formed by repeating the formation of the interlayer insulating film, wiring, capacitor insulating film and floating electrode FE. However, it is not necessary to form the capacitor insulating film and the floating electrode FE on all power supply lines and ground lines.

As described above, according to the present embodiment, the wiring Ma (VDD) is used as the lower electrode and the floating electrode F
E as an upper electrode, and a capacitor insulating film CZ between them.
(Capacitance element) Ca ₁ having
A capacitor (capacitance element) Ca ₂ having a capacitor insulating film CZ can be formed between (GND) as a lower electrode and the floating electrode FE as an upper electrode. These capacitors (capacitance elements) Ca ₁ , Ca
₂ is connected in series between the wiring Ma and the wiring Mb.

Therefore, these capacitors (capacitance elements)
Power noise can be reduced by Ca ₁ and Ca ₂ .

The floating electrode FE is connected to the wiring M
Since it extends on a and Mb in a divided state, a reduction in yield can be avoided. The reason will be described below.

Here, it is assumed that the area where the floating electrode FE faces the wirings Ma and Mb is A, and N unit electrodes UE obtained by equally dividing this A into N are formed. Note that if A is the same regardless of the division number N, the capacitor between the wires Ma and Mb is constant, and the effect of reducing power supply noise does not change.

The area where each unit capacitor UC faces the wiring Ma is A / 2N, and the area where each unit capacitor UC faces the wiring Mb is also:
A / 2N.

In this case, in order for each unit capacitor UC to be defective, for a certain unit capacitor UC, the breakdown voltage between the unit capacitor UC and the wiring Ma is poor, and the unit capacitor UC and the wiring Mb This is limited to the case where the breakdown voltage between the two is poor.

For example, the unit capacitor UC and the wiring M
The probability that the withstand voltage between a and a is not bad is expressed by Exp (−A * D
/ (2N)), the unit capacitor UC and the wiring M
b is not bad, Exp (−A * D
/ (2N)). Here, D indicates the defect density.

Therefore, the unit capacitor UC is a good product.
A certain probability (P_unit) Is P_unit= 1- (1-Exp (-
A * D / (2N))) * (1-Exp (-A * D / (2
N))), and N unit capacitors are non-defective.
Probability (P) is P = P_unit ^N(P_unitN)
You.

FIG. 6 shows the probability that all N unit capacitors are non-defective (P) as the capacitor yield.
(Number of divisions). Here, the defect density (D) is 5 / cm ² , and the facing area (A) is 1 cm ²
And As shown in FIG. 6, by dividing the floating electrode FE (N ≧ 2) as compared with the case where the floating electrode FE is not divided (N = 1), the capacitor yield is improved. The capacitor yield increases and approaches 1 as the number of divisions (N) increases.

As described above, by dividing the floating electrode FE, the yield (non-defective product rate) of the capacitors connected in series between the wirings Ma and Mb, and furthermore, the yield of the semiconductor integrated circuit device having these are obtained. Can be improved.

Further, unlike the above-mentioned capacitor having the MOS structure, a MIM (Metal Insulator Metal) structure can be adopted, so that the frequency characteristics can be improved.
In addition, it is possible to cope with steep pulse-like noise.

Further, a MOS transistor constituting a semiconductor integrated circuit can be formed below the floating electrode FE, and the area is not limited as in the case of the capacitor having the MOS structure described above. In addition, there is no need to prepare a fuse to cope with a defect in the MOS capacitor, and it is not necessary to judge the quality of the MOS capacitor and the step of cutting the fuse, which complicates the structure of the capacitor and the manufacturing process thereof. Can be solved.

Note that, as shown in FIG.
b may be divided into a plurality of lines in the direction in which these wirings extend. In this case, since the capacitor insulating film CZ is also formed on the side wall of the divided wiring, the capacitance can be increased.

(Embodiment 2) Next, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. 7 to 24 are sectional views or plan views of a main part of a semiconductor substrate, showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, as shown in FIG. 7, a semiconductor substrate 1 having a main surface on which a semiconductor element such as a MISFET is formed is prepared. As shown in FIG.
The T gate electrode 9 extends on the semiconductor substrate 1,
Source and drain regions are present on both sides of the gate electrode 9 (not exposed in the cross section shown in FIG. 1).

On the MISFET (gate electrode 9), a silicon oxide film 15 is formed. In the silicon oxide film 15, a local interconnect line L is formed.
I is formed. This local interconnect wiring LI is, for example, a gate electrode 9 of MISFET or MI
It is connected to the source and drain regions of the SFET. Note that, in the semiconductor substrate 1, an element isolation 2 made of a silicon oxide film embedded in an element isolation groove is formed.
The gate electrode 9 is made of, for example, a laminated film of a low-resistance polycrystalline silicon film doped with phosphorus, a tungsten nitride film, and a tungsten film. The local interconnect LI is formed by, for example, embedding a tungsten film in a groove formed in the silicon oxide film 15.

An interlayer insulating film such as a silicon oxide film and a conductive film such as an aluminum film are alternately deposited on the semiconductor substrate 1 to form a plurality of wirings. Hereinafter, the formation of the interlayer insulating film and the wirings will be described. This will be described in detail with reference to FIGS.

As shown in FIG. 8, a silicon oxide film is deposited on the silicon oxide film 15 including the local interconnect wiring LI by CVD, and then the silicon oxide film is
The interlayer insulating film TH1 is formed by polishing by the P method and flattening the surface.

Next, a photoresist film is formed on the interlayer insulating film TH1 (not shown), and the interlayer insulating film TH1 is etched using the photoresist film as a mask to form a contact hole C1 on the local interconnect wiring LI. Form.

Next, a tungsten film is deposited on the interlayer insulating film TH1 including the inside of the contact hole C1 by the CVD method, and the tungsten film is polished by the CMP method until the interlayer insulating film TH1 is exposed. To form a plug P1. Next, a titanium nitride film (not shown), an aluminum film, and a titanium nitride film (not shown) are sequentially deposited on the interlayer insulating film TH1 and the plug P1 by a sputtering method, and are patterned into a desired shape to form a first film. The layer wiring M1 is formed. Here, of the first layer wiring M1, the power supply potential (VDD) is applied to the wiring M1a, and the ground potential (GND) is applied to the wiring M1b.

Next, as shown in FIG. 9, a capacitor insulating film CZ1 is formed by depositing a silicon nitride film having a thickness of about 10 nm by a plasma CVD method on the interlayer insulating film TH1 including on the first layer wiring M1. . Here, the thickness of the capacitor insulating film CZ1 is set so as to withstand the power supply voltage (VDD). Note that, as shown in FIG. 2 described in the first embodiment, the capacitor insulating film CZ1 may be formed with a certain thickness over the wiring.
Here, for convenience, the surface of the capacitor insulating film is described as being flat (hereinafter, other capacitor insulating films CZ2 to CZ).
Same for 7 mag. 10 to 23 and FIG.
To FIG. 28).

Next, as shown in FIG. 10, a tungsten film is deposited on the capacitor insulating film CZ1 by sputtering, and the tungsten film is etched using a resist film (not shown) as a mask to form a floating electrode FE1.
To form The floating electrode FE1 is formed on the first layer wiring M1a to which the power supply potential (VDD) is applied and the first layer wiring M1b to which the ground potential (GND) is applied. The first layer wiring M1b is located next to the first layer wiring M1a and extends in parallel with the wiring M1a, and the floating electrode FE1 is also connected to these wirings M1a,
It extends in the same direction as M1b. Further, the floating electrode FE1 is connected to the wiring M as in the first embodiment.
It extends in a state of being divided into a plurality in a direction orthogonal to the direction in which 1a and M1b extend (see FIG. 5).

Next, as shown in FIG. 11, an interlayer insulating film TH2 is formed on the floating electrode FE1. The interlayer insulating film TH2 is formed in the same manner as the interlayer insulating film TH1.
Thereafter, a contact hole C2 is formed by removing the interlayer insulating film TH2 and the capacitor insulating film CZ1 on the first layer wiring M1, and a plug P2 is formed in the contact hole C2. This plug P2 is formed similarly to the plug P1. Next, a second layer wiring M2 is formed on the interlayer insulating film TH2 and the plug P2 in the same manner as the first layer wiring.

Next, as shown in FIG.
2, an interlayer insulating film TH3 is formed. Interlayer insulating film TH3
Is formed in the same manner as the interlayer insulating film TH1. afterwards,
Forming a contact hole C3 in the interlayer insulating film TH3,
A plug P3 is formed in the contact hole C3.
This plug P3 is formed similarly to the plug P1. Next, a third layer wiring M3 is formed on the interlayer insulating film TH3 and the plug P3 in the same manner as the first layer wiring.

Next, as shown in FIG.
3, an interlayer insulating film TH4 is formed. Interlayer insulating film TH4
Is formed in the same manner as the interlayer insulating film TH1. afterwards,
A contact hole (not shown) is formed in the interlayer insulating film TH4, and a plug (not shown) is formed in the contact hole. This plug is formed similarly to the plug P1. Next, a fourth-layer wiring M4 is formed on the interlayer insulating film TH4 and a plug (not shown) in the same manner as the first-layer wiring.

Next, as shown in FIG.
4, an interlayer insulating film TH5 is formed. Interlayer insulating film TH5
Is formed in the same manner as the interlayer insulating film TH1. afterwards,
Forming a contact hole C5 in the interlayer insulating film TH5,
A plug P5 is formed in the contact hole C5.
This plug P5 is formed similarly to the plug P1. Next, a fifth layer wiring M5 is formed on the interlayer insulating film TH5 and the plug P5 in the same manner as the first layer wiring. Here, of the fifth layer wiring M5, the power supply potential (VDD) is applied to the wiring M5a, and the ground potential (GND) is applied to the wiring M5b.

Next, as shown in FIG. 15, the fifth layer wiring M5
A capacitor insulating film CZ5 is formed by depositing a silicon nitride film having a thickness of about 10 nm on the interlayer insulating film TH5 including the upper portion by a plasma CVD method. Here, the thickness of the capacitor insulating film CZ5 is set so as to withstand the power supply voltage (VDD).

Next, as shown in FIG. 16, a tungsten film is deposited on the capacitor insulating film CZ5 by sputtering, and the tungsten film is etched using a resist film (not shown) as a mask to form a floating electrode FE5.
To form The floating electrode FE5 is formed on the fifth layer wiring M5a to which the power supply potential (VDD) is applied and the fifth layer wiring M5b to which the ground potential (GND) is applied. The fifth-layer wiring M5b is located next to the fifth-layer wiring M5a and extends in parallel with the wiring M5a, and the floating electrode FE5 is also connected to these wirings M5a,
It extends in the same direction as M5b. The floating electrode FE5 is connected to the wiring M as in the case of the first embodiment.
It extends in a direction orthogonal to the direction in which 5a and M5b extend, while being divided into a plurality of parts (see FIG. 5).

Next, as shown in FIG. 17, an interlayer insulating film TH6 is formed on the floating electrode FE5. The interlayer insulating film TH6 is formed in the same manner as the interlayer insulating film TH1.
Thereafter, a contact hole (not shown) is formed by removing the interlayer insulating film TH6 and the capacitor insulating film CZ5 on the fifth layer wiring M5, and a plug (not shown) is formed in the contact hole. This plug is formed similarly to the plug P1. Next, a sixth layer wiring is formed on the interlayer insulating film TH6 and the plug in the same manner as the first layer wiring. Here, M6a in FIG. 17 is the sixth layer wiring.
The wiring to which the power supply potential (VDD) is applied.
Next to the layer wiring (M6a), a first layer wiring M6 extending parallel to the wiring M6a and receiving a ground potential (GND).
b exists. However, the wiring M6b is not exposed in the sectional direction of FIG.

Next, as shown in FIG. 18, the sixth layer wiring M6
A capacitor insulating film CZ6 is formed by depositing a silicon nitride film having a thickness of about 10 nm by a plasma CVD method on the interlayer insulating film TH6 including the portion a. Here, the thickness of the capacitor insulating film CZ6 is set so as to withstand the power supply voltage (VDD).

Next, as shown in FIG. 19, a tungsten film is deposited on the capacitor insulating film CZ6 by a sputtering method, and the floating film FE6 is etched by etching the tungsten film using a resist film (not shown) as a mask.
To form The floating electrode FE6 is formed on the sixth layer wiring M6a to which the power supply potential (VDD) is applied and on the sixth layer wiring M6b to which the ground potential (GND) is applied. The floating electrode FE5 extends in the same direction as the wirings M6a and M6b. Also,
As shown in the drawing, the floating electrode FE6 extends in a state of being divided into a plurality of parts in a direction orthogonal to the direction in which the wirings M6a and M6b extend, as in the first embodiment.

Next, as shown in FIG. 20, an interlayer insulating film TH7 is formed on the floating electrode FE6. The interlayer insulating film TH7 is formed in the same manner as the interlayer insulating film TH1.
Thereafter, a contact hole C6 is formed by removing the interlayer insulating film TH7 and the capacitor insulating film CZ6 on the sixth layer wiring M6a, and a plug P6 is formed in the contact hole C6. This plug P6 is plug P1
It is formed in the same manner as described above. Next, a seventh layer wiring M7 is formed on the interlayer insulating film TH6 and the plug P6 in the same manner as the first layer wiring. Here, of the seventh layer wiring M7, the power supply potential (VDD) is applied to the wiring M7a and the wiring M7b is applied to the wiring M7b.
A ground potential (GND) is applied.

Next, as shown in FIG. 21, the seventh layer wiring M7
A capacitor insulating film CZ7 is formed by depositing a silicon nitride film having a thickness of about 10 nm on the interlayer insulating film TH7 including the upper portion by a plasma CVD method. The thickness of the capacitor insulating film CZ7 is set so as to withstand the power supply voltage (VDD).

Next, as shown in FIG. 22, a tungsten film is deposited on the capacitor insulating film CZ7 by a sputtering method, and the floating film FE7 is etched by etching the tungsten film using a resist film (not shown) as a mask.
To form The floating electrode FE7 is formed on the seventh layer wiring M7a to which the power supply potential (VDD) is applied and on the seventh layer wiring M7b to which the ground potential (GND) is applied. The seventh-layer wiring M7b is located next to the seventh-layer wiring M7a and extends in parallel with the wiring M7a, and the floating electrode FE7 is also connected to these wirings M7a,
It extends in the same direction as M7b. The floating electrode FE7 is connected to the wiring M as in the case of the first embodiment.
7a and M7b extend in a direction orthogonal to the direction in which they extend and are divided into a plurality of parts (see FIG. 5).

Next, as shown in FIG. 23, a silicon oxide film and a silicon nitride film are sequentially deposited on the floating electrode FE7 to form a passivation film PV composed of these films.

FIG. 24 is a plan view of a main part of the semiconductor integrated circuit device of the present embodiment. As shown in FIG. 24, the wirings M7a and M7b of the seventh-layer wiring M7 are
01 is formed in an annular shape around the periphery. Here, the inside of these wirings formed in an annular shape is called a core region 202. Further, a bonding pad BP is formed on the outer periphery of the element formation region 201. Bonding pad B
P is formed by a seventh layer wiring M7 which is the uppermost layer wiring.

As described above, according to the present embodiment, the power supply potential (VD) of the first, fifth, sixth, and seventh layer wirings is used.
Since the floating electrode (FE1 or the like) is formed via a capacitor insulating film (CZ1 or the like) on the wiring pair to which D) and the ground potential (GND) are applied, as described in the first embodiment, power supply noise is reduced. Can be reduced. In addition, since the floating electrode (FE1 or the like) is extended on these wirings in a divided state, it is possible to avoid a decrease in yield. Further, since the capacitor has the MIM structure, the frequency characteristics can be improved.
In addition, it is possible to cope with steep pulse-like noise.

Further, below the floating electrode, for example,
A MOS transistor forming a semiconductor integrated circuit can be formed below the annularly formed wirings M7a and M7b, and the formation region of the MOS transistor is not limited. Also, as described in Embodiment 1,
It is possible to solve problems when a capacitor having a MOS structure is used, such as a complicated configuration and a manufacturing process of the capacitor.

In this embodiment, the floating electrode (F) is formed on the four layers of wiring (first, fifth, sixth and seventh layer wiring) via a capacitor insulating film (CZ1 or the like).
E1), but these may be formed for four or more layers of wiring or four or less layers of wiring. In this embodiment, the floating electrodes (FE1 and the like) are formed on the first, fifth, sixth and seventh layer wirings via the capacitor insulating films (CZ1 and the like). The wiring (second to fourth layer wiring) may be formed on a pair of wirings to which a power supply potential (VDD) and a ground potential (GND) are applied.

However, for example, M7 (M7a, M7b, FE
7), the current from the capacitor flows through M6, M5... M1.
Is the cause of noise. Therefore, the effect of forming the capacitor in the lower layer (for example, M1) is large.

As in the first embodiment, the capacitor insulating film CZ may be formed using a material having a high dielectric constant, such as a tantalum oxide film, in addition to the silicon nitride film.

(Embodiment 3) In the second embodiment, the wirings M7a and M7b of the seventh layer wiring M7 are formed annularly outside the core region. However, these wirings are formed in the core region. Is also good.

Next, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. The steps up to the step of forming the interlayer insulating film TH7 and the plug P6 formed therein are the same as in the case of the second embodiment, and a description thereof will be omitted.

A titanium nitride film (not shown), an aluminum film and a titanium nitride film (not shown) are formed on interlayer insulating film TH7 and plug P6 shown in FIG. 25 by sputtering.
Are sequentially deposited and patterned into a desired shape to form a seventh-layer wiring M7. Here, the seventh layer wiring M
7, the power supply potential (VDD) is applied to the wiring M7a, and the ground potential (GND) is applied to the wiring M7b. These wirings M7a and M7b are also formed inside an element formation region 201 described later.

Next, as shown in FIG.
A capacitor insulating film CZ7 is formed by depositing a silicon nitride film having a thickness of about 10 nm on the interlayer insulating film TH7 including the upper portion by a plasma CVD method. Here, the thickness of the capacitor insulating film CZ7 is set so as to withstand the power supply voltage (VDD).

Next, a tungsten film is deposited on the capacitor insulating film CZ7 by a sputtering method, and the floating film FE7 is formed by etching the tungsten film using a resist film (not shown) as a mask. The floating electrode FE7 is formed on the seventh layer wiring M7a to which the power supply potential (VDD) is applied and on the seventh layer wiring M7b to which the ground potential (GND) is applied. The seventh-layer wiring M7b is located next to the seventh-layer wiring M7a and extends in parallel with the wiring M7a, and the floating electrode FE7 also extends in the same direction as these wirings M7a and M7b. I have. The floating electrode FE7 extends in a state of being divided into a plurality of parts in a direction orthogonal to the direction in which the wirings M7a and M7b extend, as in the first embodiment (see FIG. 5). Further, the floating electrode FE7 is formed so as to avoid a region where a plug P7 described later is formed.

Next, as shown in FIG. 27, a silicon oxide film and a silicon nitride film are sequentially deposited on the floating electrode FE7 to form a passivation film PV composed of these films.

Next, as shown in FIG.
A contact hole C7 is formed by etching the passivation film PV and the capacitor insulating film CZ7 on the seventh-layer wiring including M7b. Next, on the passivation film PV including the inside of the contact hole C7, C
A plug P7 is formed in the contact hole C7 by depositing a tungsten film by the VD method and polishing the tungsten film by the CMP method until the passivation film PV is exposed.

Next, a barrier metal film BM made of a titanium nitride film or the like is formed on the plug P7 by sputtering.
Further, a solder bump electrode BPn is formed thereon (see FIG. 29). Here, the power supply potential (VDD) is applied to the solder bump electrode BPa among the solder bump electrodes BPn.
Is applied, and a ground potential (GND) is applied to the solder bump electrode BPb. The solder bump electrode BPo is
Other bump electrodes.

FIG. 29 is a plan view of a main part of the semiconductor integrated circuit device of the present embodiment. As shown in FIG. 29, the seventh layer wiring M7 (including M7a and M7b) is
1 and the solder bump electrodes BPn (including BPo, BPa, BPb) formed thereon are exposed.

In the embodiment shown in FIG. 29, since M7a and M7b are scattered inside the element region, there is a problem that a known method of providing a MOS capacitor below M7a and M7b greatly reduces the degree of integration.

According to the present embodiment, however, the power supply potential (VD) of the first, fifth, sixth and seventh layer wirings
Since the floating electrode is formed on the wiring pair to which D) and the ground potential (GND) are applied via the capacitor insulating film, the effect described in the second embodiment can be obtained. Further, a MOS transistor forming a semiconductor integrated circuit can be formed below the wirings M7a and M7b of the seventh-layer wiring M7, and the formation region of the MOS transistor is not limited.

(Embodiment 4) In the first to third embodiments, each wiring is formed on an interlayer insulating film. However, each wiring is formed by embedding a metal film in a groove formed in the insulating film. May be.

Next, a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention will be described. 30 to 3
FIG. 5 is a sectional view of a principal part of a semiconductor substrate, showing an example of a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

First, as shown in FIG. 30, a semiconductor element (not shown) such as a MISFET is formed on the main surface of a semiconductor substrate 1 made of single crystal silicon, and a silicon oxide film is deposited on the semiconductor element. The interlayer insulating film TH is formed by polishing and flattening the surface.

Next, on the interlayer insulating film TH, a silicon nitride film Ha and a silicon oxide film Hb are sequentially deposited by the CVD method, and an insulating film H for wiring trench formed of these films is formed. Next, the wiring grooves HMa and HMb are formed by etching the wiring groove insulating film H in the wiring formation planned region. The silicon nitride film Ha is used as an etching stopper at the time of the etching.

Next, as shown in FIG.
a, a barrier layer BM made of titanium nitride is deposited on the wiring trench insulating film H including the inside of HMb by a sputtering method or a CVD method, and then a copper film M is formed on the barrier layer BM by a sputtering method.

Next, as shown in FIG. 32, the copper film M and the barrier layer BM outside the wiring groove are removed by CMP to form wirings Ma and M made of the copper film M and the barrier layer BM.
b (embedded wiring) is formed. Here, for example, the wiring Ma is connected to a power supply potential (V
DD), and the wiring Mb is connected to the ground potential (GND) via a wiring or a plug (not shown). Since these wirings (Ma, Mb) are so-called power supply wirings,
The wiring width is almost equal, and is designed to be several tens μm, which is wider than other wirings.

Next, as shown in FIG.
A capacitor insulating film CZ is formed by depositing a silicon nitride film having a thickness of about 10 nm on the interlayer insulating film TH including the upper portion by a plasma CVD method. Here, the thickness of the capacitor insulating film CZ is set so as to withstand the power supply voltage (VDD). In this case, the capacitor insulating film CZ also serves to prevent copper in the wires Ma and Mb from diffusing into the interlayer insulating film.

Next, as shown in FIG. 34, a tungsten film W having a thickness of about 100 nm is deposited on the capacitor insulating film CZ by a sputtering method.

Next, as shown in FIG. 35, the tungsten film is etched using the resist film (not shown) on tungsten film W as a mask to form floating electrode F.
Form E. The floating electrode FE is not electrically connected to the lower-layer wirings Ma and Mb and the upper-layer wiring. The floating electrode FE extends on the wires Ma and Mb in a divided state (see FIG. 5).

Note that, as shown in FIG.
Ba and Bb are formed as barrier films (copper diffusion preventing films) on the substrate b, and a capacitor insulating film CZ is formed on the barrier films Ba and Bb by depositing, for example, a tantalum oxide film. An FE may be formed.

Thereafter, the formation of the interlayer insulating film, the insulating film for the wiring groove, the wiring, the capacitor insulating film, and the floating electrode is repeated to form a semiconductor integrated circuit device having a plurality of wiring layers. However, it is not necessary to form a capacitor insulating film and a floating electrode on all wirings.

Further, the seven-layer wirings of the second and third embodiments may be formed by the above-mentioned buried wirings. The method of manufacturing the semiconductor integrated circuit device in this case is the same as that described in Embodiment 2 or 3, and the method of forming the wiring is the same as the method of forming the wiring groove insulating film, forming the wiring groove, and forming the metal film Are the same except for the embedding and CMP.

As described above, according to the present embodiment, since the floating electrode is formed via the capacitor insulating film on the pair of wirings to which the power supply potential (VDD) and the ground potential (GND) are applied, power supply noise is reduced. For example, the same effects as those described in the first to third embodiments can be obtained.

Further, according to the present embodiment, since each wiring is a buried wiring, the flatness of the capacitor insulating film can be ensured, and the reliability of the capacitor can be improved.

(Fifth Embodiment) In the first to fourth embodiments, a floating electrode is formed via a capacitor insulating film on a wiring pair to which a power supply potential (VDD) and a ground potential (GND) are applied. A capacitor insulating film and a floating electrode (capacitance) may be formed on the information storage section of the SRAM memory cell.

FIG. 38 shows an SRAM according to the present embodiment.
FIG. 2 is an equivalent circuit diagram showing a memory cell of (Static Random Access Memory). As shown, this memory cell M
C is disposed at the intersection of a pair of complementary data lines (data line DL, data line / (bar) DL) and word line WL, and a pair of driving MISFETs Qd1 and Qd2, a pair of load MISFETs Qp1 and Qp2, and It is constituted by a pair of transfer MISFETs Qt1 and Qt2. Drive MISFETs Qd1 and Qd2 and transfer MISFET
ETQt1 and Qt2 are composed of n-channel MISFETs, and load MISFETs Qp1 and Qp2 are composed of p-channel MISFETs.

The above six MIs forming the memory cell MC are
Among the SFETs, the driving MISFET Qd1 and the load MISFET Qp1 are formed by a CMOS inverter IN
V1 and the driving MISFET Qd2 and the load MISFET Qp2 are connected to the CMOS inverter INV2.
Is composed. These pair of CMOS inverters I
Mutual input / output terminals of NV1 and INV2 (storage nodes A,
B) is cross-coupled to form a flip-flop circuit as an information storage unit that stores 1-bit information.
One input / output terminal (storage node A) of this flip-flop circuit is connected to one of the source and drain regions of the transfer MISFET Qt1, and the other input / output terminal (storage node B) is connected to the source of the transfer MISFET Qt2. , And one of the drain regions.

Further, the other of the source and drain regions of the transfer MISFET Qt1 is connected to the data line DL,
The other of the source and drain regions of the transfer MISFET Qt2 is connected to the data line / DL. Further, one end of the flip-flop circuit (the load MISFETs Qp1 and Qp1
Each source region of p2 is connected to the power supply voltage (Vcc), and the other end (each source region of the driving MISFETs Qd1 and Qd2) is connected to the reference voltage (Vss).

The operation of the above circuit will be described.
When the storage node A of the OS inverter INV1 is at a high potential ("H"), the driving MISFET Qd2
Is turned ON, the other CMOS inverter INV2
Storage node B attains a low potential (“L”). Therefore, the driving MISFET Qd1 is turned off, and the high potential (“H”) of the storage node A is held. That is, the state of the storage nodes A and B is held by a latch circuit in which a pair of CMOS inverters INV1 and INV2 are cross-coupled, and information is stored while the power supply voltage is applied. On the storage nodes A and B, the above-mentioned capacitor insulating film and floating electrode (capacitance) are added.

A word line WL is connected to each gate electrode of the transfer MISFETs Qt1 and Qt2, and the transfer MISFETs Qt1 and Qt2 are connected to the word line WL.
Is controlled. That is, the word line WL
Is high potential (“H”), the transfer MISFE
Since TQt1 and Qt2 are turned on and the flip-flop circuit and the complementary data lines (data lines DL and / DL) are electrically connected, the potential state of the storage nodes A and B ("H" or "L") ) Appear on the data lines DL and / DL and are read as information of the memory cells MC.

To write information into the memory cell MC, the word line WL is set to the “H” potential level and the transfer MISFET Q
By turning on t1 and Qt2, information on the data lines DL and / DL is transmitted to the storage nodes A and B.

Next, a method of manufacturing the SRAM of this embodiment will be described with reference to FIGS.

First, as shown in FIGS. 39, 40 and 41, an element isolation 2 is formed in a semiconductor substrate 1. FIG.
1 is a plan view of a semiconductor substrate showing a region for about one memory cell, and FIGS.
It is A sectional drawing and BB sectional drawing. This element isolation 2 is formed as follows. For example, the semiconductor substrate 1 made of p-type single crystal silicon is etched to a depth of 25.
An isolation trench of about 0 nm is formed.

Thereafter, the semiconductor substrate 1 is thermally oxidized at about 1000 ° C. to form a thin silicon oxide film (not shown) having a thickness of about 10 nm on the inner wall of the groove.

Next, C is formed on the semiconductor substrate 1 including the inside of the groove.
A silicon oxide film having a thickness of about 450 to 500 nm is deposited by a VD method, and the silicon oxide film on the upper portion of the groove is polished by a chemical mechanical polishing (CMP) method to planarize the surface.

Next, a p-type impurity (boron) and an n-type impurity (for example, phosphorus) are ion-implanted into the semiconductor substrate 1, and then the impurities are diffused by a heat treatment at about 1000 ° C., so that the p-type impurity is added to the semiconductor substrate 1. Well 3 and n
A mold well 4 is formed. As shown in FIG. 41, a p-type well 3, an n-type well 4, active regions Ap1 and Ap2 in the p-type well, and active regions An1 and An2 in the n-type well are formed in the semiconductor substrate 1. A p-type well 3 and an n-type well 4 (An1, An2) are formed. These active regions An1, An2, Ap1, and Ap2 are surrounded by an element isolation 2 in which a silicon oxide film is embedded.

As will be described in detail later, six MISFETs (Qt1, Qt1,
Of the Qt2, Qd1, Qd2, Qp1, Qp2), the n-channel MISFET (Qt1, Qd1) is formed on the active region Ap1 (p-type well 3), and the n-channel M
The ISFET (Qt2, Qd2) is connected to the active region Ap2 (p
Formed on the mold well 3). In addition, p-channel type MI
The SFET (Qp2) is formed on the active region An1 (n-type well 4), and the p-channel MISFET (Qp2)
1) is formed on the active region An2 (n-type well 4).

Next, an n-channel MISFET (Qt1, Qd1, Qt2, Qd2) and a p-channel MISFET (Qp1, Qp2) are formed on the main surface of the semiconductor substrate 1.

First, the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is wet-cleaned using a hydrofluoric acid-based cleaning solution, and then a film is formed on each surface of the p-type well 3 and the n-type well 4. A clean gate oxide film (not shown) having a thickness of about 6 nm is formed.

Next, as shown in FIGS. 42, 43 and 44, a gate electrode G is formed on the gate oxide film on the semiconductor substrate 1. FIG. 44 is a plan view of the semiconductor substrate showing a region for about one memory cell, and FIGS.
44 is a sectional view taken along the line AA and a sectional view taken along the line BB of FIG. 44, respectively. This gate electrode G is formed as follows. First, a low-resistance polycrystalline silicon film having a thickness of about 100 nm is deposited on the gate oxide film by a CVD method. Next, a gate electrode G made of a polycrystalline silicon film is formed by dry-etching the polycrystalline silicon film using a photoresist film (not shown) as a mask. As shown in FIG. 44, on the active region Ap1, the transfer MISFET Qt1
Is formed, and the gate electrode G of the driving MISFET Qd1 is formed.
The gate electrode G of the SFET Qt2 and the driving MISFET
A gate electrode G of Qd2 is formed. The gate electrode G of the load MISFET Qp2 is formed on the active region An1, and the load MISFET Qp2 is formed on the active region An2.
The gate electrode G of the FET Qp1 is formed. These gate electrodes are formed in the AA direction in the figure, respectively. The gate electrode G of the load MISFET Qp1 and the gate electrode of the drive MISFET Qd1 are common, and the gate electrode of the load MISFET Qp2 and the drive MISFET Qd2 And the gate electrode is common.

Next, as shown in FIG.
P by implanting p-type impurities (boron) in the upper ^-
-Type semiconductor region 14, also, although not shown in n by implanting n-type impurity (phosphorus) on both sides of the gate electrode G on the p-type well 3 in FIG. 43 ^- -type semiconductor regions.

Next, a silicon nitride film having a thickness of about 40 nm is deposited on the semiconductor substrate 1 by the CVD method, and is etched anisotropically to form a sidewall spacer 16 on the side wall of the gate electrode G.

Next, ap ⁺ -type semiconductor region 18 (source, drain) is formed by ion-implanting a p-type impurity (boron) into the n-type well 4. An n ⁺ -type semiconductor region (source, drain) is formed by ion-implanting an n-type impurity (phosphorous or arsenic) on 3.

In the steps up to this point, the six MISFETs (driving MISFETs Qd1,
Qd2, transfer MISFETs Qt1 and Qt2 and load MISFETs Qp1 and Qp2) and n-channel MISFETs and p-channel MISs constituting peripheral circuits.
The SFET is completed.

Subsequently, after cleaning the surface of the semiconductor substrate 1, a Co film and a Ti film are sequentially deposited on the semiconductor substrate 1 by a sputtering method, and a heat treatment is performed at 600 ° C. for 1 minute to expose the semiconductor substrate 1. Part (n ⁺ type semiconductor region 17, p ⁺
Type semiconductor region 18) and gate electrode G, CoSi
Form a layer (not shown).

Next, after the unreacted Co film and Ti film are removed by etching, the film is heated at 700 to 800.degree.
A heat treatment is performed for about a minute to form a low-resistance CoSi ₂ layer (not shown).

Next, as shown in FIGS. 45 and 46, after a silicon oxide film 21 is deposited on the semiconductor substrate 1, the surface of the silicon oxide film 21 is polished by the CMP method to flatten the surface.

Next, a photoresist film (not shown) is
By dry-etching the silicon oxide film as a mask, a contact hole C1 and a wiring groove HM are formed on the n ⁺ -type semiconductor region (source and drain) and the p ⁺ -type semiconductor region 18 (source and drain) (see FIG. 49). ). Further, a contact hole C1 is formed on the gate electrodes G of the transfer MISFETs Qt1 and Qt2. One wiring groove HM passes from above the drain of the driving MISFET Qd1 to above the drain of the load MISFET Qp1,
It extends to above the gate electrode of the driving MISFET Qd2. The other wiring groove HM is a driving MISFET.
It extends from above the drain of Qd2 to above the drain of the load MISFET Qp2 to above the gate electrode of the drive MISFET Qd1 (see FIG. 49).

Next, as shown in FIGS. 47, 48 and 49, a plug P1 and wirings MD1, MD2 (conductive layer) are formed by embedding a conductive film in C1 and the wiring groove HM. FIG. 49 is a plan view of the semiconductor substrate showing a region for about one memory cell, and FIGS.
50 is a sectional view taken along the line AA and a sectional view taken along the line BB of FIG. 49, respectively. To form these, first, contact holes C
1 and a TiN film (not shown) having a thickness of about 10 nm and a TiN film (not shown) having a thickness of about 50 nm are sequentially formed on the upper portion of the silicon oxide film 21 including the inside of the wiring groove 1 and the wiring groove HM. Heat treatment is performed at 700 ° C. for 1 minute. Next, a tungsten film is deposited by a CVD method, etched back or CMP is performed until the surface of the silicon oxide film 21 is exposed, and the Ti film, the TiN film and the tungsten film outside the contact hole C1 and the wiring groove HM are removed.

Then, as shown in FIGS. 50 and 51, the silicon oxide film 21, the plug P1, and the wiring MD
1. A silicon nitride film 23 having a thickness of about 5 nm is formed on MD2. The silicon nitride film 23 is formed by wirings MD1 and MD2 serving as lower electrodes and a floating electrode 24 described later.
To form a capacitive insulating film.

Next, as shown in FIG. 52, FIG. 53 and FIG. 54, a tungsten film having a thickness of about 50 nm is deposited on the silicon nitride film 23 by a sputtering method, and is patterned to form a film on the wirings MD1 and MD2. Floating electrode 24 is formed. FIG. 54 is a plan view of a semiconductor substrate showing a region for about one memory cell,
52 and 53 are cross-sectional views taken along line AA of FIG.
It is -B sectional drawing. This floating electrode 24 is patterned so as not to extend over the plug P1 (FIG. 54).
reference).

Through the above steps, a wiring MD1, a capacitance Ca1 composed of the silicon nitride film 23 and the floating electrode 24, and a wiring MD2, and a capacitance Ca2 composed of the silicon nitride film 23 and the floating electrode 24 are formed. be able to. That is, the capacitors Ca1 and Ca2 are connected in series between the wirings MD1 and MD2 (between the storage nodes AB).

As described above, according to the present embodiment, since the floating electrode 24 is formed on the wirings MD1 and MD2 via the silicon nitride film 23, soft errors caused by α rays incident on the memory cells of the SRAM are reduced. Can be reduced.

Since the wirings MD1 and MD2 are buried wirings, the flatness of the silicon nitride film 23 can be ensured, and the reliability of the capacitance can be improved.

Further, the floating electrode 24 is
As shown in FIG. 8, since the memory cell MC is arranged in a divided state, similarly to the first embodiment, in order for the floating electrode FE to be defective, it is necessary to set the distance between the floating electrode FE and the wiring MD1. Is low and the withstand voltage between the floating electrode FE and the wiring MD2 is low, so that a decrease in yield can be avoided. FIG. 55 is a plan view of the semiconductor substrate showing a region of about four memory cells (two by two).

Also, for example, the storage nodes A and B
When a lower electrode (LE) and an upper electrode (UE) to be connected to each other are provided, through holes for connecting these electrodes to storage nodes A and B (source, drain) must be formed. In addition, the number of masks and the number of steps increase, and the quality of the capacitor insulating film deteriorates.

An example of a process for providing such a lower electrode and an upper electrode will be described. First, as shown in FIG. 62A, after removing the interlayer insulating film TH on the drain of the driving MISFET Qd1, a contact hole CA is formed.
A plug PA is formed by embedding a metal layer in the contact hole, and a lower electrode LE is formed on the plug PA.
To form Next, as shown in FIG. 62B, a capacitance insulating film CZ is formed on the lower electrode LE, and thereafter, as shown in FIG. 62C, a resist film (not shown) on the capacitance insulating film CZ is formed. MISFET Qd2
Is removed (etched) to form a contact hole CB. Next, as shown in FIG. 62D, a plug PB is formed by burying a metal layer in the contact hole CB, and an upper electrode UE is formed on the plug PB. As a result, the lower electrode (LE), the upper electrode (UE) and the capacitance insulating film CZ
Thereby, a capacitance is formed between the storage nodes AB.

However, in the case of the above-described steps, the contact hole CA, the lower electrode LE, the contact hole CB
In addition, four masks for patterning the upper electrode UE are required, and the number of steps increases.

On the other hand, according to the present embodiment, only the floating electrode FE need be patterned.
The number of masks and the number of steps can be reduced.

In the steps of FIGS. 62 (a) to 62 (d), the surface of the capacitive insulating film CZ required to improve the film quality is
Since the substrate is exposed to various processes such as formation of a resist film, photolithography, etching and removal of the resist film, the quality of the capacitor insulating film is deteriorated, which may lead to a decrease in yield.

On the other hand, in the present embodiment,
Without forming a resist film on the capacitance insulating film CZ,
The quality of the capacitor insulating film can be improved. As a result, the yield can be improved.

Next, a first layer wiring M1 and a second layer wiring M2 are formed on the floating electrode 24 via an interlayer insulating film. Subsequently, the steps of forming these wirings will be described with reference to FIGS.

First, as shown in FIGS. 56, 57 and 58, a silicon oxide film 25 is deposited on the floating electrode 24 by the CVD method. Next, the silicon oxide film 25 and the silicon nitride film 23 on the plug P1 are removed by etching to form a contact hole C2.
To form FIG. 58 is a plan view of a semiconductor substrate showing a region for about one memory cell, and FIGS. 56 and 57 are AA cross-sectional view and BB cross-sectional view of FIG. 58, respectively.

Next, a plug P2 is formed by embedding a conductive film in the contact hole C2. First,
Silicon oxide film 25 including inside contact hole C2
A Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially deposited on the upper surface of the substrate by sputtering, and then a tungsten film is deposited by the CVD method to expose the surface of the silicon oxide film 25. The plug P2 is formed by performing etch back or CMP until the Ti film, the TiN film, and the tungsten film outside the contact hole C2 are removed.

Subsequently, a first layer wiring M1 is formed on the silicon oxide film 25 and the plug P2. First, a Ti film (not shown) having a thickness of about 10 nm and a TiN film having a thickness of about 50 nm are sequentially deposited by a sputtering method.
A first layer wiring M1 is formed by depositing and patterning a tungsten film by the method D. First layer wiring M1
Of these, the first layer wiring M that connects the gate electrodes G of the transfer MISFETs Qt1 and Qt2 via plugs P1 and P2
1 becomes the word line WL.

Next, as shown in FIGS. 59, 60 and 61, a silicon oxide film 27 is deposited on the first layer wiring M1 and the silicon oxide film 25 by the CVD method, and then on the first layer wiring M1. The contact hole C3 is formed by removing the silicon oxide film 27 by etching (see FIG. 61).

Next, a plug P3 is formed by embedding a conductive film in the contact hole C3. This plug P3 is formed similarly to the plug P2 (see FIG. 61).

Subsequently, a second-layer wiring M2 is formed on the silicon oxide film 27 and the plug P3 (FIGS. 59 and 61).
reference). First, a T film having a thickness of about 10 nm is formed by sputtering.
An i film (not shown) and a TiN film having a thickness of about 50 nm are sequentially deposited, and then an aluminum film having a thickness of about 300 nm is formed and patterned to form a second layer wiring M.
Form 2

The driving MISF via the two-layer wiring M2
Reference potential (Vss) applied to the sources of ETQd1 and Qd2
Is supplied, and the power supply potential (Vcc) is supplied to the sources of the load MISFETs Qp1 and Qp2. Further, a second MISFET Qt1, Qt2 connected to one end of
The layer wiring becomes the data line (DL, / DL).

Through the above steps, the SRAM memory cell described with reference to FIG. 38 is almost completed.

As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

In the second and third embodiments,
Although a MISFET was formed as a semiconductor element,
Not limited to ET, other elements such as a bipolar transistor can be formed.

[0146]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

Since the conductive film extending via the insulating film is formed on the power supply wiring and the ground wiring of the semiconductor integrated circuit device, noise on the power supply wiring and the ground wiring can be reduced. Further, the yield can be improved by dividing the conductive film into a plurality. Further, by using this conductive film as a metal film, the transient response of the capacitor can be improved.

In addition, a pair of n-channel MISFs of a memory cell including a pair of n-channel MISFETs whose gate electrodes and drains are cross-connected are constituent elements.
Since the third conductive layer is formed on the first and second conductive layers connecting the gate electrode and the drain of the ET via the capacitive insulating film, it is possible to reduce a soft error due to α rays incident on the memory cell. it can.

In a memory cell array in which a plurality of memory cells are arranged in a matrix, the third conductive layer is divided for each memory cell, so that the yield can be improved.

Further, it is possible to improve the degree of integration, reduce the number of steps for forming the noise reducing capacitor, and improve the reliability.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is an essential part plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a diagram showing a relationship between a capacitor yield and the number of divisions (N).

FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 17 is a cross-sectional view of a principal part of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

20 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention; FIG.

FIG. 21 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 24 is an essential part plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to Embodiment 2 of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 27 is an essential part cross sectional view of the substrate for illustrating the method of manufacturing the semiconductor integrated circuit device of Embodiment 3 of the present invention.

FIG. 28 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 29 is a fragmentary plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;

FIG. 32 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of the fourth embodiment of the present invention.

FIG. 33 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;

FIG. 34 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of Embodiment 4 of the present invention.

FIG. 35 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 37 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 38 is an equivalent circuit diagram showing a memory cell of the SRAM according to the fifth embodiment of the present invention;

FIG. 39 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 40 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 41 is a main part plan view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 42 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 43 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 44 is an essential part plan view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 45 is an essential part cross sectional view of the substrate for illustrating the method of manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 46 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 47 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 48 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 49 is an essential part plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 50 is an essential part cross sectional view of the substrate for illustrating the method of manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 51 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 52 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 53 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 54 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 55 is a plan view of a main portion of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 56 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 57 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 58 is a substantial part plan view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 59 is an essential part cross sectional view of the substrate for illustrating the method of manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.

FIG. 60 is a cross-sectional view of a principal part of the substrate, illustrating the method of manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIG. 61 is an essential part plan view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;

FIGS. 62 (a) to 62 (d) are diagrams for describing effects of the fifth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 element isolation 3 p-type well 4 n-type well 9 gate electrode 14 n ^- type semiconductor region 15 silicon oxide film 16 sidewall spacer 18 n ⁺ type semiconductor region 21 silicon oxide film 23 silicon nitride film 24 floating electrode 25 oxidation Silicon film 27 Silicon oxide film 201 Element formation region 202 Core region A, B Storage node An1, An2 Active region Ap1, Ap2 Active region Ba Barrier film BM Barrier metal film (barrier layer) BP Bonding pad BPn, BPo, BPa, BPb Solder bump electrode C1~C7 contact hole CA, CB contact holes CZ capacitor insulating film (capacitor insulating film) CZ1 capacitor insulating film CZ5~CZ7 capacitor insulating film Ca _1, Ca ₂ capacitors (capacitance) DL, / DL data lines E Floating electrode FE1 Floating electrode FE5 to FE7 Floating electrode G Gate electrode H Wiring groove insulating film HM Wiring groove HMa, HMb Wiring groove Ha Silicon nitride film Hb Silicon oxide film INV1, INV2 CMOS inverter LE Lower electrode LI Local interconnect wiring M Copper Films M1, M1a, M1b First layer wiring M2 Second layer wiring M3 Third layer wiring M4 Fourth layer wiring M5, M5a, M5b Fifth layer wiring M6a, M6b Sixth layer wiring M7, M7a, M7b Seventh layer wiring MC memory cell MD1 wiring MD2 wiring Ma, Mb wiring P1 to P7 plug PA, PB plug PV passivation film Qd1 driving MISFET Qd2 driving MISFET Qp1 load MISFET Qp2 load MISFET Qt1 transfer M ISFET Qt2 Transfer MISFET TH Interlayer insulating film TH1 to TH7 Interlayer insulating film UC Unit capacitor UE Unit electrode UE Upper electrode W Tungsten film WL Word line

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F038 AC02 AC05 AC15 AC18 BE07 BH19 CA10 CD02 CD03 CD18 CD20 DF05 EZ11 EZ20 5F083 BS05 GA12 GA18 JA06 JA36 JA37 JA39 JA40 MA06 MA18 MA19 NA08 PR40

Claims (23)

[Claims] 1. A semiconductor integrated circuit device having a power wiring and a ground wiring formed on an upper part of a semiconductor substrate, comprising: an insulating film formed on the power wiring and the ground wiring; A conductive film formed so as to extend through the insulating film, the conductive film not being electrically connected to the power supply wiring and the ground wiring. A semiconductor integrated circuit device wherein a capacitive element is constituted by a conductive film and an insulating film. 2. A power supply wiring and a ground wiring formed on a semiconductor substrate, a dielectric film formed on the power supply wiring and the ground wiring, and a dielectric film formed on the power supply wiring and the ground wiring via the dielectric film. And a floating conductive film formed so as to extend. 3. The semiconductor integrated circuit device according to claim 1, wherein said conductive film is a metal film. 4. The semiconductor integrated circuit device according to claim 1, wherein said insulating film is a tantalum oxide film or a silicon nitride film. 5. The semiconductor integrated circuit device according to claim 1, wherein the power supply wiring and the ground wiring are wirings formed on an interlayer insulating film on the semiconductor substrate. 6. The semiconductor integrated circuit device according to claim 1, wherein the power supply wiring and the ground wiring are buried wirings formed on a main surface of an insulating layer on the semiconductor substrate. 7. The power supply wiring, the ground wiring, and the conductive film extend in a first direction, and the conductive film is divided into a plurality of parts in a second direction orthogonal to the first direction. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged in a vertical direction. 8. The method according to claim 1, wherein the power supply wiring and the ground wiring extend in a first direction and are divided into a plurality of parts in the first direction. Semiconductor integrated circuit device. 9. The embedded wiring is made of a copper film, an outer periphery of the embedded wiring is covered with a copper diffusion preventing film, and the copper diffusion preventing film on the embedded wiring is the insulating film. Item 7. A semiconductor integrated circuit device according to item 6. 10. A step of depositing and patterning a first conductive film on a semiconductor substrate to form a power supply wiring and a ground wiring which run in parallel, and forming an insulating film on the power supply wiring and the ground wiring. Forming a floating electrode extending on the power supply wiring and the grounding wiring via the insulating film by depositing a second conductive film on the insulating film and patterning the second conductive film. A method for manufacturing a semiconductor integrated circuit device. 11. The power supply line, the ground line, and the floating electrode are formed to extend in a first direction, and the floating electrode is divided into a plurality of parts in a second direction orthogonal to the first direction. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is formed so as to be arranged. 12. A semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected to each other, the memory cell being formed on the pair of n-channel MISFETs. An interlayer insulating film, first and second conductive layers connecting a gate electrode and a drain of the pair of n-channel MISFETs, and a capacitive insulating film formed on the first and second conductive layers And a third floating conductive layer formed on the capacitor insulating film and formed on the first and second conductive layers via the capacitor insulating film. Semiconductor integrated circuit device. 13. The semiconductor device according to claim 13, wherein the first and second conductive layers are formed in connection holes in the interlayer insulating film and in connection holes extending from the gate electrode to the drain. 13. The semiconductor integrated circuit device according to claim 12, wherein 14. The memory cell includes a pair of transfer n-channel MISFETs in addition to the pair of n-channel MISFETs.
MISFE for ISFET and a pair of p-channel type loads
13. The semiconductor integrated circuit device according to claim 12, wherein T is a component. 15. The semiconductor integrated circuit device has a memory cell array in which a plurality of the memory cells are arranged in a matrix, and the third conductive layer is divided for each of the memory cells. The semiconductor integrated circuit device according to claim 12. 16. The semiconductor integrated circuit device according to claim 12, wherein said first, second, and third conductive layers are metal films. 17. The semiconductor integrated circuit device according to claim 12, wherein said insulating film is a silicon nitride film. 18. A method for manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, wherein said pair of n-channel MISFETs is provided. Forming a first conductive layer and a second conductive layer extending from above a gate electrode to a drain of the pair of n-channel MISFETs; and forming a capacitor on the first and second conductive layers. A method for manufacturing a semiconductor integrated circuit device, comprising: forming an insulating film; and forming a floating electrode by forming a third conductive layer on the capacitor insulating film and patterning the third conductive layer. 19. The semiconductor integrated circuit device has a memory cell array in which a plurality of the memory cells are arranged in a matrix, and the floating electrode is divided for each of the memory cells. The manufacturing method of the semiconductor integrated circuit device described in the above. 20. The method according to claim 18, wherein the first, second and third conductive layers are metal films. 21. The method according to claim 18, wherein the insulating film is a silicon nitride film. 22. A method of manufacturing a semiconductor integrated circuit device having a memory cell including a pair of n-channel MISFETs each having a gate electrode and a drain cross-connected, wherein said pair of n-channel MISFETs is provided. Forming an interlayer insulating film on the pair of n-channel MISFETs; forming first and second connection holes extending from a gate electrode of the pair of n-channel MISFETs to a drain. Forming; depositing a conductive film on the interlayer insulating film including the inside of the first and second connection holes; polishing the conductive film until the surface of the interlayer insulating film is exposed Forming first and second conductive layers buried in the connection holes by: and forming a capacitor insulating film on the first and second conductive layers Forming a third conductive layer on the capacitor insulating film and patterning the third conductive layer to form a floating electrode, the method comprising: 23. The semiconductor integrated circuit device has a memory cell array in which a plurality of the memory cells are arranged in a matrix, and the floating electrode is divided for each of the memory cells. A manufacturing method of the semiconductor integrated circuit device according to the above.