JP2002314098A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having low ON resistance and excellent reverse direction characteristics. SOLUTION: A p-type silicon region 5 having circular openings periodically is formed on the surface of an n-type silicon region 3. The n-type silicon region 3 is branched into a plurality of columnar insular regions by the p-type silicon region 5 to form a current passage. A barrier metal layer 7 and a surface electrode layer 8 are formed on the p-type silicon region 5 and the n-type silicon region 3 exposed to the surface thus forming an SBD structure. In the SBD, the forward end face of a depletion layer (a) spreads into the columnar n-type silicon region 3 toward the central axis and pinches off efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a Schottky barrier diode (hereinafter referred to as "SBD") which can be used, for example, for power supplies of power electronics equipment / systems, information-related equipment, and control of various motors. ").

[0002]

2. Description of the Related Art In general, an SBD has a disadvantage that although the on-voltage (forward voltage drop) is small, the leakage current in the reverse direction is large. As one of power semiconductor devices (power devices), there is a junction barrier / control type SBD (hereinafter referred to as “JBS diode”). This JBS diode has a normal n-type S
The BD has a structure in which a plurality of p-type semiconductor regions 102 are buried under a Schottky electrode 104. JB
The features of the S diode are that the depletion layer a extends from each p-type semiconductor region 102 in the reverse characteristics and pinches off, thereby alleviating the electric field applied to the Schottky interface, suppressing the reverse leakage current and the reverse breakdown voltage characteristics. It is an improvement of. FIG. 10 is a plan view showing an arrangement of a plurality of circular p-type semiconductor regions 102 exposed on one main surface of the semiconductor substrate 101. The p-type semiconductor region 102
In some cases, as shown in FIG. 11, a rectangular object may be uniformly arranged.

On one main surface of the semiconductor substrate 101,
As shown in FIG. 9, a field oxide film (SiO ₂ ) 10
3 are formed. At the center of the field oxide film 103, an opening 103A for exposing the n-type semiconductor substrate 101 serving as an active region is provided. An n-type semiconductor substrate 101 serving as an active region includes a plurality of p-type semiconductor regions 1.
02 are arranged in an island shape. Then, a metal film 104 as a Schottky electrode is formed so as to be in contact with n-type semiconductor substrate 101 in opening 103A of field oxide film 103. The metal film 104 makes ohmic contact with the plurality of p-type semiconductor regions 102 arranged in an island shape. The metal film 104 is formed to extend on the field oxide film 103 on the periphery of the opening 103A. In the SBD 100, when a negative voltage, that is, a reverse bias is applied to the Schottky electrode 104 with respect to the n-type semiconductor substrate 101, as shown in FIG. 12, the island-shaped p-type semiconductor region 102 and the n-type semiconductor The depletion layer a expands from the pn junction interface with the substrate 101 toward the n-type semiconductor substrate 101. That is, the depletion layer a is formed so as to surround the island-shaped p-type semiconductor region 102, the electric field applied to the Schottky interface between the Schottky electrode 104 and the n-type semiconductor substrate 101 is reduced, and the reverse breakdown voltage is maintained high. As a result, high breakdown voltage is achieved.

As shown in FIG. 9, this SBD 10
0, on one main surface side of the semiconductor substrate 101, along the opening edge of the opening 103A of the field oxide film 103,
A p ⁺ guard ring 105 of a conductivity type opposite to the conductivity type of the semiconductor substrate 101 is formed around the periphery. By forming the guard ring 105, the reverse current in the peripheral portion of the metal-semiconductor contact is reduced.

[0005]

However, in the SBD 100 having the geometrical shape (topology) shown in FIG. 9, the depletion layer a extends outside the island-shaped p-type semiconductor region 102,
In order to form the entire depletion layer a on the entire n-type semiconductor substrate 101 serving as a channel region between the p-type semiconductor regions 102,
It was necessary to apply a relatively strong electric field. For example, FIG.
In the case of the p-type semiconductor regions 102 arranged in a circular island-like pattern as shown in FIG. 13, by applying a reverse bias, as shown in FIG. 2) extending the depletion layer a. FIG. 13 shows a state in which the tip surfaces of adjacent depletion layers a are pinched off. The neutral gap region b shown in FIG.
In order to reach the state of being completely filled with the depletion layer a,
It is necessary to apply a stronger reverse bias. That is,
A larger reverse bias is needed to reduce the reverse leakage current.

In the state shown in FIG. 13, the fact that the undepleted neutral region b remains means that there is an extreme point in the potential distribution. This potential distribution is due to boundary conditions determined by the geometric structure (topology) of the semiconductor device, and thus affects the potential distribution in a completely pinched-off state. For this reason, it is difficult to obtain a uniform potential distribution even in a completely pinched-off state, electric field concentration is likely to occur, and it is disadvantageous to alleviate the electric field, so that it is difficult to increase the reverse breakdown voltage.

The fact that a strong reverse bias is required to completely fill the neutral region b between the p-type semiconductor regions 102 with the depletion layer a means that a p-type semiconductor having a rectangular pattern as shown in FIG. The same applies to the case of the topology including the region 102. For this reason, the depletion layers a extending from the respective p-type semiconductor regions 102 spread more efficiently, and the neutral region b does not remain even in a part between the depletion layers a when viewed in plan. It is desired to have a structure that can be used.

[0010] In the topologies shown in FIGS. 10 and 11, the distance between the p-type semiconductor regions 102 depends on a manufacturing process such as a variation in exposure amount in a photolithography process, a difference in pattern conversion in an etching process, and a variation in diffusion depth. In the case of variation for various reasons, the area and shape of the neutral region b greatly change, and thus there is a disadvantage that the reverse characteristics are easily affected.

The present invention has been made to solve the above problems. Accordingly, it is an object of the present invention to provide a Schottky barrier semiconductor device having a low forward voltage drop (on resistance) and excellent reverse characteristics.

[0010]

In order to solve the above-mentioned problems, the present invention is characterized by a first semiconductor region of a first conductivity type,
A second conductive type second semiconductor region formed on the surface of the first semiconductor region and having a plurality of openings for exposing the first semiconductor region in an island shape therein; and a second semiconductor region exposed to the plurality of openings. The gist is to provide a semiconductor device including a first semiconductor region formed on a surface of one semiconductor region and a Schottky electrode layer forming a Schottky junction. That is, a metal having a predetermined Schottky barrier with respect to the first semiconductor region is selected for the Schottky electrode layer. Here, the “first conductivity type” and the “second conductivity type” are the opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type.

In the feature of the present invention, it is preferable that the “second semiconductor region” is a semiconductor region having a higher impurity density than the “first semiconductor region”. By making the second semiconductor region a high impurity density region, the Schottky electrode layer makes ohmic contact with the second semiconductor region and forms a Schottky junction only with the first semiconductor region. For example, when a bias in the forward direction of the Schottky junction is applied to the first semiconductor region to the Schottky electrode layer, carriers are injected into the first semiconductor region via the Schottky junction having a low barrier height. Although the first semiconductor region and the second semiconductor region form a pn junction, the contact potential (built-in potential) of the pn junction is usually higher than the Schottky barrier, so that the injection of carriers through the second semiconductor region is normally performed. This does not occur unless the directional bias is increased. For example, in the case of silicon, the impurity density of the first semiconductor region is set to 1 × 10 ¹⁵
If it is set to about cm ^{−3 to 1} × 10 ¹⁷ cm ⁻³ , the contact potential (built-in potential) of the pn junction is about 0.87 V to 1.0 V. On the other hand, the Schottky barrier of tungsten (W) for n-type silicon is about 0.65 to 0.67 eV.

The opening is, for example, circular and has a diameter of
The pn junction formed by the first semiconductor region and the second semiconductor region may be set so that the neutral region remains inside the circular second semiconductor region at zero bias. The “neutral region” means a semiconductor region that is not depleted. In a state where a voltage having a polarity that causes the pn junction formed by the first semiconductor region and the second semiconductor region to become a forward bias is applied, carriers are injected through the Schottky junction.
The forward current of the Schottky barrier flows through the neutral region of the semiconductor region as a channel region. When the opening is circular, the channel region has a columnar shape.

On the other hand, the first semiconductor region and the second semiconductor region
The reverse bias voltage at the pn junction
When applied, the depletion layer expands from the pn junction interface. here,
The impurity density of the first semiconductor region is changed to the impurity density of the second semiconductor region.
Use a one-sided stair joint structure that is sufficiently lower than the density.
In this case, the depletion layer spreads mainly toward the first semiconductor region. example
For example, the impurity density of the first semiconductor region is set to 1 × 1
0¹⁵cm^-3~ 1x10^{1 7}cm^-3And the second semiconductor
The impurity density of the region is set to 5 × 10¹⁷cm ^-3~
1x10^{twenty one}cm^-3It should just be about.

However, in a low reverse bias state near zero bias, the first semiconductor region portion exposed in an island shape in the second semiconductor region is not filled with the depletion layer, and the neutral region remains. A reverse current flows through the Schottky junction interface with one semiconductor region. When the reverse bias voltage is gradually increased, the tip surface of the depletion layer extending from the pn junction interface expands toward the central axis of the first semiconductor region, and the neutral region extends toward the central axis of the first semiconductor region. Shrink. When the opening is circular, the tip surface of the depletion layer has a cylindrical shape. In a state where a certain reverse bias is applied, the depletion layer extending toward the central axis of the columnar first semiconductor region pinches off, and the completely integrated depletion layer occupies (fills) the first semiconductor region. . That is, when the depletion layer pinches off, the neutral region disappears at the central axis of the first semiconductor region. As a result, the reverse current of the Schottky barrier is prevented from flowing.

Further, the depletion layer also extends from the pn junction interface formed between the bottom surface of the second semiconductor region and the first semiconductor region in contact with the bottom surface to the first semiconductor region side. Even at the pn junction interface including the bottom surface, the reverse current is prevented from flowing.

In the semiconductor device according to the feature of the present invention, when a reverse bias voltage is applied, the tip surface of the depletion layer in the columnar first semiconductor region surrounded by the second semiconductor region has the diameter of the neutral region. Are gradually spread out so as to be gradually reduced, and finally, at the center of the pillar, the leading end surfaces of the depletion layer are connected and integrated without excess or shortage. That is, the neutral region finally disappears monotonously at the center of the pillar. In this manner, the first semiconductor region portion surrounded by the second semiconductor region can be completely filled with the depletion layer efficiently with a lower reverse bias.

Finally, as a result of the first semiconductor region portion being occupied by the uniform depletion layer, the potential distribution becomes uniform and the electric field at the Schottky junction interface is easily alleviated. Therefore, the reverse breakdown voltage characteristics are improved.

In a feature of the invention, the plurality of openings are
Preferably, the semiconductor devices are two-dimensionally arranged at the same pitch. As described above, if a bias in the forward direction of the Schottky junction is applied to the Schottky electrode layer with respect to the first semiconductor region, carriers are injected into the first semiconductor region through the Schottky junction having a low barrier height. The first columnar semiconductor region becomes a channel region. Therefore, by arranging a plurality of openings two-dimensionally at the same pitch, a multi-channel structure is realized, and a large current can flow. The plurality of openings may be determined in consideration of the rated current. In addition, by arranging two-dimensionally at the same pitch, the current distribution can be made uniform.

Although the opening is circular, the opening is polygonal, and the distance between two opposing sides of the polygon is set such that a neutral region remains inside at zero bias. Is the same. In particular, when this polygon is a regular hexagon, the area efficiency is good, and the on-resistance per unit chip area can be reduced. For example, if the shape connecting the centers of three mutually adjacent regular hexagons forms an equilateral triangle,
The Schottky junction interface between the semiconductor region and the Schottky electrode layer can be formed wider, and the area efficiency can be increased.

Various structures can be adopted for the Schottky electrode layer of the present invention. For example, a Schottky electrode layer
A barrier metal layer having a Schottky barrier with respect to the first semiconductor region and having low metallurgical reactivity with the first semiconductor region; and a surface electrode layer having higher conductivity than the barrier metal layer.
If the semiconductor device is realized with a layered structure, a semiconductor device with high reliability and low conduction loss can be realized.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device according to the present invention will be described with reference to the drawings, taking an SBD having a JBS structure as an example.
However, it should be noted that the drawings are schematic, and the thickness of each layer and the ratio of the thickness are different from actual ones. Also, the drawings include portions having different dimensional relationships and ratios. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description.

As shown in FIG. 1, the semiconductor device according to the embodiment of the present invention includes first semiconductor regions (n-type silicon regions) 3, 3A of the first conductivity type and first semiconductor regions 3, 3A. A second conductive type second semiconductor region (p-type silicon region) 5 formed on the surface and having a plurality of openings for exposing the first semiconductor region 3 </ b> A in an island shape therein, and a plurality of openings And a Schottky electrode layer (7, 8) formed to form a Schottky junction with the first semiconductor region 3A. The second semiconductor region 5 has a higher impurity density than the first semiconductor regions 3 and 3A. For the Schottky electrode layers (7 and 8), a metal that makes ohmic contact with the second semiconductor region 5 is selected. . The Schottky electrode layers (7, 8) have a Schottky barrier with respect to the first semiconductor regions 3, 3A, and have a weak metallurgical reactivity with the first semiconductor regions 3, 3A; It has a two-layer structure with the surface electrode layer 8 having higher conductivity than the metal layer 7. The first semiconductor region (n-type silicon region) 3 is formed on an n-type low-resistance Si substrate 2 serving as an ohmic contact layer. The surface of the first semiconductor region (n-type silicon region) 3 is a JBS-structured SBD 1 having a Schottky junction interface.

Second semiconductor region (p-type silicon region) 5
Are formed in a substantially mesh shape as a continuous and integral pattern as shown by hatching in FIG. The plurality of openings formed in the p-type silicon region 5 are two-dimensionally arranged at the same pitch as shown in FIG.
The opening is circular and has a diameter equal to that of the p-type silicon region 5 and n.
When a zero bias is applied between the silicon regions 3A,
The neutral region is set so as to remain inside n-type silicon region 3A. The p-type silicon region 5 is formed from the surface of the n-type silicon region 3 to a predetermined depth. The surface of n-type silicon region 3A is exposed at a circular opening surrounded by p-type silicon region 5.

FIG. 3 shows an SBD according to an embodiment of the present invention.
FIG. 2 is an exploded perspective view schematically drawn to facilitate understanding of the geometrical shape of FIG. As shown in FIG. 3, the n-type silicon region 3A in the n-type silicon region 3 surrounded by the p-type silicon region 5 can be expressed as a columnar island-like region.
The diameter of the cylindrical n-type silicon region 3A is a diffusion potential (built-in potential) at zero bias, and the impurity density of the n-type silicon region 3 is considered so that a neutral region remains inside the n-type silicon region 3A. To set.

As shown in FIGS. 1 and 3, a field oxide film 6 is formed on the surface of the n-type silicon region 3. The opening that exposes the surface of n-type silicon region 3 of field oxide film 6 defines active region 6A. Inside the active region defined by the field oxide film 6, a p-type silicon region 5 and an n-type silicon region 3 surrounded by the p-type silicon region 5 are arranged. Then, Schottky electrodes (7, 8) are formed on the surface of n-type silicon region 3 exposed on the surface of active region 6A. The Schottky electrodes (7, 8)
A is formed so as to extend over the entire region A and further on the field oxide film 6 around the active region 6A.

The Schottky electrodes (7, 8) have a two-layer structure of a barrier metal layer 7 having a fixed Schottky barrier for the n-type silicon region 3 and a surface electrode layer 8. The barrier metal layer 7 is a metal having low metallurgical reactivity with the n-type silicon region 3 and having a certain Schottky barrier with respect to the n-type silicon region 3. For example, tungsten (W), platinum (Pt), palladium (Pd), molybdenum (Mo), or the like can be used as the barrier metal layer 7. The barrier metal layer 7 is a metal that suppresses a metallurgical reaction between the n-type silicon region 3 and the metal forming the surface electrode layer 8. For example, when aluminum (Al) is used as the surface electrode layer 8, the metal is a metal for preventing an alloy reaction between Al and the n-type silicon region 3 and a spike of Al to the n-type silicon region 3. The barrier metal layer 7 further functions as a substantially Schottky barrier metal layer.

The surface electrode layer 8 has a fixed Schottky barrier to the n-type silicon region 3 and is a metal having higher conductivity than the barrier metal layer. For example, aluminum (Al), aluminum alloy (Al-1% Si), gold (Au), copper (Au), silver (Ag), or the like is used as the surface electrode layer 8.
Can be used as Since the barrier metal layer 7 substantially functions as a Schottky barrier metal layer, the Schottky barrier of the surface electrode layer 8 with respect to the n-type silicon region 3 may be low. Practically, easily workable Al or aluminum alloy (Al-1% Si)
Is preferred. Further, on the other main surface of the silicon substrate 4, that is, on the back surface of the ohmic contact layer 2, a back surface electrode layer (ohmic electrode layer) 9 is formed.

In the SBD 1, the surface of the n-type silicon region 3 under the field oxide film 6 has
The guard ring region 10 of the mold is formed annularly along the opening edge. The guard ring region 10 is formed as a pattern independent of the p-type silicon region 5.
The guard ring region 10 relaxes the electric field at the Schottky junction interface by a depletion layer having a large radius of curvature in which a depletion layer extending from the guard ring region 10 and a depletion layer extending from the p-type silicon region 5 are combined, and the active region 6A The Schottky barrier breakdown voltage is improved.

In the SBD 1 according to the embodiment of the present invention,
With only the diffusion potential (built-in potential), a neutral region is left inside the n-type silicon region 3A, and an n-type channel is formed. First, the front electrode layer 8 and the back electrode layer 9
When a forward bias is applied between the n-type silicon region 3A and the columnar island region, the forward current passes through the Schottky junction interface having a small voltage drop as shown by an arrow in FIG. Flows. When the forward bias is deepened, holes are injected from the p-type silicon region 5 into the n-type silicon regions 3 and 3A, thereby contributing to a forward current.

Next, when a reverse bias is applied between the front surface electrode layer 8 and the back surface electrode layer 9, when the reverse bias value close to zero bias is low, the barrier metal layer 7 and n
A reverse current flows through a Schottky barrier region composed of the p-type silicon region 3A and a pn junction region composed of the p-type silicon region 5 and the n-type silicon region 3.

When the reverse bias is further increased, as shown in FIG. 5, the depletion layer a extending from the pn junction interface composed of the p-type silicon region 5 and the n-type silicon regions 3 and 3A becomes an n-type silicon region. It spreads to the 3A side. That is, as compared with the impurity density of the n-type silicon regions 3 and 3A,
If the impurity density of the p-type silicon region 5 is sufficiently high, it can be regarded as a one-sided step junction, so that the depletion layer a extending from the pn junction interface mainly extends to the n-type silicon regions 3 and 3A. Therefore, at the center of the n-type silicon region 3A, which is a columnar island region, the depletion layer a extending from the side surface of the column simultaneously pinches off along the central axis, and the neutral region disappears. Therefore, the columnar island region below the barrier metal layer 7 that contacts the surface of the silicon substrate 4 is a region where the depletion layer a is completely distributed. The path composed of all the cylindrical island-shaped regions is completely and uniformly pinched off by the depletion layer a.

When the inside of the columnar island region 3A is completely pinched off by the depletion layer a, the depletion layer a expands below the p-type silicon region 5 and is further synthesized with the depletion layer expanding from the guard ring region 10. . As a result, the electric field at the Schottky junction interface is reduced by the depletion layer having a large radius of curvature in which the depletion layer extending from the guard ring region 10 and the depletion layer extending from the p-type silicon region 5 are combined, and the reverse breakdown voltage of the Schottky barrier is reduced. improves. FIG. 6 shows forward characteristics and reverse characteristics of the SBD 1 according to the embodiment of the present invention. A low on-voltage (forward voltage drop), a small reverse leakage current, and a large reverse breakdown voltage are shown.

The trajectory of the depletion layer a extending into the island-shaped n-type silicon region 3A, being connected along the central axis of the columnar n-type silicon region 3A and being integrated will be described with reference to FIG. I do. When a reverse bias is applied between the surface electrode layer 8 (barrier metal layer 7) and the back electrode layer 9, as shown in FIG. 7, a pn junction interface J between the p-type silicon region 5 and the n-type silicon region 3A is formed. From the column-structured n-type silicon region 3
The tip surface of the depletion layer a expands so that the diameter of the concentric circle decreases toward A (in the direction of the arrow). That is, the outer diameter of the cylinder forming the neutral region gradually decreases. The leading end surface of the depletion layer a is simultaneously connected and integrated while reaching the central axis C of the n-type silicon region 3A sequentially through the positions indicated by the broken line and the dashed line, and the neutral region disappears on the central axis C. . As a result, n-type silicon region 3A is completely pinched off by depletion layer a.

As described above, S according to the embodiment of the present invention
In the BD1, the n-type silicon region 3A has a columnar shape (circular cross-section), so that the depletion layer a extends from the pn junction interface J between the p-type silicon region 5 and the n-type silicon region 3A at any position. Therefore, the formed depletion layer a can be uniformly connected (integrated) without waste. Therefore, the columnar n-type silicon region 3A
Can be pinched off completely with low reverse bias,
It is easy to suppress reverse leakage current. Moreover,
Since the potential distribution inside the columnar n-type silicon region 3A is uniform, the electric field applied to the Schottky junction interface is reduced, and the reverse breakdown voltage is improved.

The breakdown voltage can be set appropriately by changing the radius of the n-type silicon region 3A.
Withstand voltage control can be easily performed according to the use of D1.

SB according to the embodiment of the present invention shown in FIG.
A description will be given of a manufacturing method of D1. (A) First, as shown in FIG.
¹⁹cm^-3N-type low-resistance Si having a thickness of 300 to 600 μm
An impurity density of 1 is formed on a substrate 2 by an epitaxial growth method.
x10¹⁵cm^-3~ 1x10¹⁷cm^-3Degree, preferably
3x10¹⁶cm ^-3Degree, thickness about 5-50μm, preferred
Specifically, an n-type silicon region 3 of about 10 μm to 20 μm is formed.
Form.

(B) Next, a buffer oxide film having a thickness of about 100 nm is formed on the surface of the n-type silicon region 3. Then, a photoresist film (hereinafter simply referred to as “resist”) is spin-coated on the buffer oxide film. Then, the resist is patterned by a photolithography technique. Then, ions serving as acceptor impurities are selectively implanted from the surface of the n-type silicon region 3 using the patterned resist as an ion implantation mask. For example, selectively ion-implanting boron ⁽¹¹ B ^+). As an example, boron is accelerated with an acceleration energy E _ACC = 100 to 200 keV, and a total dose Φ =
Multistage injection of 3 × 10 ¹⁵ cm ⁻² is performed. As a result, the impurity density of 1 × is set in a region having a depth of 0.38 to 0.7 μm from the surface.
A boron implanted layer of 10 ²⁰ cm ^-3 is formed. For example: First ion implantation: Φ = 1 × 10 ¹⁵ cm ⁻² / E _ACC = 1
00 KeV; second ion implantation: Φ = 1 × 10 ¹⁵ cm ⁻² / E _ACC = 1
50 KeV; Third ion implantation: Φ = 2 × 10 ¹⁵ cm ⁻² / E _ACC = 2
00 KeV;

(C) After that, use as an ion implantation mask
The remaining resist is removed, and the substrate temperature T _SUB= 1050 ° C ~
By the activation heat treatment at about 1150 ° C., as shown in FIG.
And a p-type silicon region 5 and a p-type guard ring.
Forming region 10. Part of this activation heat treatment
The n-type silicon region 3
A thermal oxide film 6 having a thickness of 350 nm to 1 μm is formed on the surface.

(D) At this time, since a thermal oxide film is also formed on the back surface of the n-type low-resistance Si substrate 2, the surface of the n-type low-resistance Si substrate 2 is covered with a resist, The thermal oxide film on the back surface of the substrate 2 is removed, and the n-type low-resistance Si substrate 2 is removed.
Expose the back of Further, if necessary, the n-type low resistance S
The back surface of the i-substrate 2 is polished by chemical mechanical polishing (CMP) or the like to reduce the thickness of the n-type low-resistance Si substrate 2 to 50 to 100 μm.
May be adjusted. Then, as shown in FIG. 1, an Al-Si film is deposited on the back surface of the n-type low-resistance Si substrate 2 to a thickness of about 1 to 4 μm. Further, the substrate temperature T _SUB = 420 to 45
An ohmic electrode (backside electrode layer) 9 is formed by sintering at about 0 ° C.

(E) Next, a resist is spin-coated on the thermal oxide film on the surface of the n-type silicon region 3. Then, the resist is patterned by photolithography to form an etching mask. Then, using this etching mask, the thermal oxide film on the surface of the n-type silicon region 3 is selectively removed with an etching solution such as a buffered hydrofluoric acid solution to expose the surface of the n-type silicon region 3 to the active region. . Immediately, about 2 n
A W film 7 having a thickness of 00 nm and an Al film 8 having a thickness of about 1-2 μm are sequentially deposited.

(F) Then, a resist is spin-coated on the Al film 8. Then, the resist is patterned by photolithography to form an etching mask. Then, using this etching mask, the Al film 8 and the W film 7 are selectively removed by etching to form Schottky electrodes (7, 8), thereby completing the SBD 1.

As described at the beginning, in the conventional topologies shown in FIGS. 10 and 11, the distance between the p-type semiconductor regions 102 varies depending on the exposure amount in the photolithography process, the pattern conversion difference in the etching process, and the diffusion depth. In the case where the variation is caused by the influence of the variation in the neutral region b, the influence on the reverse characteristics caused by the large change of the area and the shape of the neutral region b is serious. In the SBD 1 according to the embodiment of the present invention, in the step of forming the p-type silicon region 5, even if a slight shift occurs in the pattern formation at the time of the selective ion implantation mask or the selective vapor phase diffusion of the impurity, The electric field can be reliably reduced. That is, even if the diameter of the circular n-type silicon region 3A is slightly varied due to process reasons in the photolithography process, the etching process, and the diffusion process, the inside is efficiently pinched off by the depletion layer a. Therefore, there is an advantage that it is hardly affected by the manufacturing process. This is because, even if the reverse voltage until the inside of the circular n-type silicon region 3A is completely pinched off slightly changes, the uniformity of the potential can be maintained and the influence on the reverse characteristics is small.

(Other Embodiments) The embodiments of the present invention have been described above. However, it should be understood that the description and drawings which constitute a part of the disclosure of the above embodiments limit the present invention. is not. From this disclosure, various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art.

For example, in the above-described embodiment, an example is shown in which the n-type silicon region 3A is exposed in a circular shape on the surface (one main surface) of the silicon substrate 4, but as shown in FIG. N-type silicon regions 3 exposed on the surface of
A is formed in a honeycomb shape such that the planar shape is formed in a substantially regular hexagon and the opposite sides of the exposed surfaces of the adjacent n-type silicon regions 3A are parallel to each other. In addition,
When the exposed shape of the n-type silicon region 3A is a regular hexagon as described above, the entire shape of the n-type silicon region 3A is a hexagonal prism, and the opposing surfaces of the adjacent n-type silicon regions 3A are also parallel. . Other configurations in this modification are the same as those in the above-described embodiment.

In this modification, when the tips of the depletion layers extending inward from the respective sides of the regular hexagon pinch off each other, a neutral region remains partially. However, according to actual experimental results, the contribution of this neutral region is small, and it seems that the inside of the hexagonal prism is almost completely pinched off. Therefore, n is substantially the same as in the above-described embodiment.
The electric field strength for filling the depletion layer a in the silicon region 3A can be reduced, and the occupation area of the n-type silicon region 3A can be increased by adopting a regular hexagonal topology. Since the area efficiency of the Schottky junction interface is improved in this manner, the barrier metal layer 7 and the n-type silicon region 3A
It is possible to increase the amount of current flowing through the Schottky junction interface with the substrate. Also, by changing the size of the hexagonal n-type silicon region 3A, it is possible to easily control the breakdown voltage.

In the above embodiment, the epitaxial growth layer into which carrier impurities of the same conductivity type as the silicon substrate are introduced at a low impurity density is used as n-type silicon region 3A. May be formed.

Although the case where the n-type is used as the first conductivity type and the p-type is used as the second conductivity type has been described, it goes without saying that the conductivity types may be completely reversed. Metals having a Schottky barrier to p-type silicon include Al,
Lead (Pb), Ag, nickel (Ni) and the like can be used.

In the present invention, gallium arsenide (GaAs) or silicon carbide (Si) is used as a semiconductor material other than silicon.
It is also possible to use a compound semiconductor material such as C).

Further, in the above embodiment, the active region 6
Although the guard ring region 10 is provided along the lower portion of the field oxide film 6 near A, a double guard ring structure, a field ring structure, a VL
Of course, a configuration in which a D structure, a SIPOS structure, or the like is provided may be used.

As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the matters specifying the invention according to the claims that are appropriate from the above description.

[0051]

As is apparent from the above description, according to the present invention, a Schottky barrier semiconductor device having a low forward voltage drop (on-resistance) and excellent reverse characteristics can be realized.

[Brief description of the drawings]

FIG. 1 shows a semiconductor device (SB) according to an embodiment of the present invention.
It is sectional drawing of D).

FIG. 2 shows a semiconductor device (SB) according to an embodiment of the present invention.
It is a top view which shows the surface exposure shape of the n-type silicon region in D).

FIG. 3 shows a semiconductor device (SB) according to an embodiment of the present invention.
FIG. 3D is an exploded perspective view showing a schematic geometric shape of D).

FIG. 4 shows a semiconductor device (SB) according to an embodiment of the present invention.
It is sectional explanatory drawing which shows the direction in which the forward current flows in the Schottky junction interface in D).

FIG. 5 shows a semiconductor device (SB) according to an embodiment of the present invention.
FIG. 4D is an explanatory sectional view showing a state in which the n-type silicon region is filled with a depletion layer in D).

FIG. 6 shows a semiconductor device (SB) according to an embodiment of the present invention.
FIG. 4D is a characteristic diagram showing a forward voltage characteristic and a reverse bias characteristic of D).

FIG. 7 shows a semiconductor device (SB) according to an embodiment of the present invention.
It is a plane explanatory view showing the state where the depletion layer gradually expands to the n-type silicon region in D).

FIG. 8 shows a semiconductor device (SB) according to another embodiment of the present invention.
D) Plane (exposed) shape of n-type silicon region and p
FIG. 4 is a plan view showing a planar shape of a mold silicon region.

FIG. 9 is a sectional view of a conventional SBD.

FIG. 10 is a plan view showing the shape of a (p-type) semiconductor region in a conventional SBD.

FIG. 11 is a plan view showing another shape of a (p-type) semiconductor region in a conventional SBD.

FIG. 12 is a cross-sectional view showing a state in which a depletion layer is formed between (p-type) semiconductor regions in a conventional SBD.

FIG. 13 is an explanatory plan view showing a state in which a depletion layer is formed via a gap between (p-type) semiconductor regions in a conventional SBD.

[Explanation of symbols]

 Reference Signs List 1 SBD 3, 3A n-type silicon region (first semiconductor region) 5 p-type silicon region (second semiconductor region) 7 barrier metal layer (metal layer for Schottky barrier) 8 front electrode layer 9 back electrode layer

Claims (7)

[Claims] A first semiconductor region of a first conductivity type; and a plurality of openings formed on a surface of the first semiconductor region and exposing the first semiconductor region in an island shape. A second semiconductor region of a second conductivity type; and a Schottky electrode layer formed on the surface of the first semiconductor region exposed to the plurality of openings so as to form a Schottky junction with the first semiconductor region. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein said second semiconductor region has a higher impurity density than said first semiconductor region, and said Schottky electrode layer makes ohmic contact with said second semiconductor region. 2. The semiconductor device according to 1. 3. The plurality of openings are two-dimensionally arranged at the same pitch.
13. The semiconductor device according to claim 1. 4. The opening according to claim 1, wherein the opening has a circular shape and a diameter thereof is set such that a neutral region remains inside at zero bias.
13. The semiconductor device according to claim 1. 5. The apparatus according to claim 1, wherein the opening is a polygon, and a distance between two opposing sides of the polygon is set such that a neutral region remains inside at zero bias. The semiconductor device according to any one of claims 1 to 3. 6. The semiconductor device according to claim 5, wherein said polygon is a regular hexagon. 7. The Schottky electrode layer has a Schottky barrier with respect to the first semiconductor region, and has a weak metallurgical reactivity with the first semiconductor region. Also with the highly conductive surface electrode layer
The semiconductor device according to claim 1, wherein the semiconductor device has a layer structure.