JP2002312255A - Main signal monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a system for executing data communication between packages, capable of monitor even if a silent failure wherein a path pattern to be inserted is not normally inserted because of a data error between the packages is generated. SOLUTION: In this system, parity rules attached to a main signal and the path pattern are differed. When monitoring the data error in the PKG, parity for the main signal attached to the communication data is monitored. When a parity rule except the parity rule for the main signal is detected, an alarm is outputted. After a differential circuit detects a change point of the alarm, a signal wherein the detected signal is expanded to one time slot width and the alarm signal are compared. In the case of disagreement, an error is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique related to error monitoring of communication data in a system for performing data communication between packages (hereinafter, referred to as PKGs), and in particular to the technique.
The present invention relates to a technique in which a data error in a PKG is performed in the PKG, and error monitoring of communication data between the PKGs is performed in a received package.

[0002]

2. Description of the Related Art For data communication between PKGs, for example, a package having a signal processing section for inputting a frame-structured data signal, performing predetermined processing, and outputting the processed signal to the outside, and an output of the signal receiving section are input. And a subsequent package on which a signal transmission unit for outputting data after performing appropriate processing is mounted. FIG. 4 shows the system. Error monitoring of communication data of such a system is performed by monitoring errors in communication data received from PKGs facing each other and monitoring errors in communication paths between PKGs, thereby monitoring errors in the entire system. Controls error monitoring. As shown in FIG. 4, by crossing both monitoring sections, a system having no unmonitored section in the main signal line can be configured.

As an example of this, there is a method in which monitoring within a PKG is performed using vertical parity with respect to a main signal, and monitoring between PKGs is performed by inserting a fixed pattern called a path pattern into an unused time slot of a main signal frame. The path pattern area is an area where a fixed pattern determined for each device is inserted at a transmission source mounted on a predetermined PKG. PKG
The error monitoring during the period is performed by detecting the path pattern in the communication data in which the path pattern is inserted by the PKG at the subsequent stage.

FIG. 5 shows a monitoring point where a monitoring section in / within a PKG is crossed, and the details will be described below.

[0005] The PKG1 has a PTY GEN1 for generating parity for monitoring communication data in the PKG1 at its input end,
PATH INS2 for inserting a path pattern for monitoring between G1 and PKG2
And PTYDET3 for monitoring the parity added to the communication data at the output terminal of the PKG.

[0006] PKG2 is a PTY GEN4 for generating a parity to be added to the communication data received from PKG1.
And PATH for detecting a path pattern of the communication data.
The monitoring operation will be described below.

[0007] Regarding the PKG monitoring, first, PKG1
The communication data received at is transmitted to the P
After the parity bit is added by TY GEN1,
A path pattern is added to the empty area of the communication data by PATH INS2. The communication data to which the parity and the path pattern are added is the PTYDE at the output terminal of PKG1.
Parity is checked by T3, and monitoring of the main signal in PKG1 is completed (section indicated by solid arrow). The multiplexing means of the main signal and the path pattern constituting the communication data is constituted by a selector as shown in FIG. 6, and selectively outputs either the A input or the B input based on the control signal S.

Next, regarding monitoring between PKGs, P
The communication data output from the KG1 is input to the PKG2, and the PKG2 is arranged at the input terminal of the PKG2 to generate the PKG.
(2) After parity for internal monitoring is added, PK in PATH DET5
Check the path pattern inserted in G1, check PKG1 → PK
The main signal monitoring between G2 is completed (section indicated by dotted arrow).

FIG. 7 is a time chart showing addition of a parity and a path pattern. When a path pattern for monitoring between PKGs is inserted into a main signal, this is realized by inputting an insertion pulse to the control signal of the selector at the timing of an unused time slot of the main signal frame into which the path pattern is to be inserted.

As described above, the occurrence of a failure in the PKG 1
Alternatively, even if the connection between PKG1 and PKG2 becomes abnormal, an error in the main signal can be detected.

When a path pattern is inserted into the main signal by PATH INS2 in PKG1, the PTY is already included in the main signal.
Since parity is added by GEN1, it is necessary to add in advance the vertical parity of the same parity rule as the main signal to the path pattern to be inserted by PATH INS2.

[0012]

However, a failure occurs in the main signal to which parity is added and the control signal of the selector for selecting the path pattern, and the path pattern is selected at a position where the main signal should be selected and output. If it is output, an abnormality cannot be detected in the subsequent parity monitoring control because a valid parity is added.

Hereinafter, such an abnormal state will be described with reference to a time chart shown in FIG. For example, when the control signal S of the selector is fixed at the H level from the timing indicated by the mark *, the output Y of the selector also inserts a path pattern where the main signal should be originally inserted (FIG. 8).
X)). In this case, there is a parity checkpoint for monitoring in the PKG after this path pattern insertion point, but the vertical parity of the same parity rule is also added in advance to the path pattern itself overwritten on the main signal. Not detected. Also, after this abnormal main signal is input to the next stage PKG, there is a checkpoint of the inter-PKG path pattern. However, as shown in FIG. Therefore, no abnormality is detected here.

If the failure mode of the 2-1 SEL control signal S in FIG. 8 is fixed at the L level, no path pattern is inserted into the main signal. In such a case, monitoring of the next-stage PKG is performed. Abnormalities can be detected at points.

As described above, when a control signal for inserting a path pattern for monitoring between PKGs with respect to a main signal becomes abnormal, the subsequent main signal is irrespective of an error.
Since the abnormality cannot be detected by the monitoring function inside the PKG or the monitoring function between the PKGs, it is not possible to cope with a so-called silent failure by the conventional technology.

The following two reasons can be considered. First, the vertical parity method used for monitoring in a PKG is to monitor whether data in a vertical direction is correct for data in a certain time slot. Is the main signal area,
Cannot determine whether it is a path pattern area. Second, PK
The path pattern method used for monitoring between G monitors only the time slots that should contain the path pattern, and can detect abnormal data other than the main signal in other time slots. It is probably because there is no.

Accordingly, the present invention aims to provide a system capable of reliably detecting an error in communication data even in the case of a silent failure due to a malfunction as described above, thereby further improving reliability. It is intended.

[0018]

According to the present invention, there is provided a system for performing data communication between packages, wherein a parity added to a main signal of the data signal at every fixed length is monitored to enable the communication within the package. The data transmission between the packages is monitored by monitoring the path pattern periodically inserted into the unused area of the data signal in the package of the data transmission source in the package on the opposite side. In the signal monitoring system, the package includes a first parity generation unit configured to generate the parity, a second parity generation unit configured to generate a parity for a path pattern different from the bit arrangement of the parity, and the package based on a control signal. Selecting means for selectively outputting the main signal after parity addition and the path pattern after parity addition for the path pattern; A parity detection unit that receives an output of the selection unit as an input and outputs an alarm for a time slot in which the parity is not detected, an expansion unit that expands data to one time slot length after detecting a change point of the alarm, It is possible to obtain a main signal monitoring system including an error determination unit that compares the output of the parity detection unit and the output of the decompression unit and determines an in-package monitoring error when they do not match.

[0019]

Next, an embodiment of the present invention will be described in detail with reference to FIG.

Each PKG has an EVEN PTY GE for generating an EVEN parity to be added to the main signal at its input terminal.
N1 and an ODD PTY GEN2 for generating an ODD parity which is a parity added to the path pattern and which is a parity added to the main signal, for example, in which the parity rule is inverted.
And a selection circuit 3 for selecting a main signal system and a path pattern system. An output terminal of the PKG receives an output of the selection circuit 3 as an input and detects an EVEN parity.
PTY DET 4, a differentiating circuit 5 for differentiating this output to detect a change point, and a parity alarm 104 differentiated by the differentiating circuit 5 as a set input and a C signal synchronized with the main signal.
A flip-flop 6 having LK102 as a CLK input and an L level as a data input, and an output 10 of the flip-flop 6
5 and an EXOR 7 for inputting a parity error 103 and outputting a monitoring error 106 in the PKG.

Next, the normal operation will be described first with reference to the time chart shown in FIG. In the selection circuit 3,
Either the main signal to which the EVEN parity is added or the path pattern to which the ODD parity is added is selected, and the signal 101 is output.

Then, EVEN PT at the output terminal of the PKG
Since Y DET4 monitors the EVEN parity added to the main signal, a parity error (H level) is generated at its output for each time slot of the path pattern as shown by a signal 103.

A differential pulse 104 is obtained through a differentiating circuit 2 in order to extract a rising component of a parity error 103 generated at the timing of the path pattern.

In the flip-flop 3, the differential pulse 104 is H
The level is set and H is output. At the next rising edge of the CLK 102, the differential pulse is L, so that the input L level is output.

As described above, the output 105 of the flip-flop 3
Always outputs an H pulse having the same rising timing as the error pulse of the parity error 103 and a time slot width (for one clock) in which the path pattern is inserted.

Therefore, during normal operation, 105 has the same waveform as 103, so that 103 and 1
If 05 is compared with XOR4 and there is no difference, it can be obtained by outputting L (normal).

Next, a failure mode in which no abnormality is detected in the conventional example will be described. FIG. 3 shows a time chart at the time of abnormal operation. When the path pattern insertion timing is fixed at H (path pattern insertion) from a certain timing, a signal whose path pattern is overwritten is also input to a time slot which is originally a main signal, as indicated by 101 in FIG.

As a result of the parity check for this signal, since the path pattern portion becomes a parity error,
The waveform looks like 3.

As described above, even when the parity error 103 becomes H level which is longer than the time slot width (here, one clock) for inserting the path pattern, the differential circuit 5 and the flip-flop 6 operate. Since the output 105 of the flip-flop 6 is always an H pulse having a time slot width (one clock here) for inserting a pass pattern, the waveform of the 103 and 105 is different in the XOR 7 and the output of the monitoring error 106 in the PKG is high. (Error) is output.

[0030]

As described above, in the conventional circuit configuration in which a parity check is simply applied to the main signal and the path pattern after the same vertical parity is added to the main signal and the path pattern, If the insertion timing becomes abnormal, there is no means for detecting the abnormality depending on the mode, but according to the present invention, it can be detected as a monitoring alarm in the PKG.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram according to an embodiment of the present invention.

FIG. 2 is an operation time chart of the embodiment (normal operation).

FIG. 3 is an operation time chart of the embodiment (when abnormal).

Fig. 4 Monitoring section within / between PKGs

FIG. 5: Prior art

FIG. 6 is a diagram showing a conventional path pattern insertion circuit

FIG. 7 is an operation time chart of a conventional technique (in a normal state).

FIG. 8 is an operation time chart of the related art (when an abnormality occurs).

[Explanation of symbols]

1 EVEN PTY GEN 2 ODD PTY GEN 3 Selection circuit 4 EVEN PTY DET 5 Differentiator 6 Flip-flop 7 EXOR 101 Main signal + path pattern + vertical parity (output of path pattern insertion block) 102 Clock synchronized with signal 103 Priority alarm (path) 104 Alarm DF / F3 output with set 105 Monitoring error in PKG

Claims (2)

[Claims] 1. A system for performing data communication between packages, wherein a data error in the package is monitored by monitoring a parity added to the main signal of the data signal at regular intervals. In a main signal monitoring system for monitoring a data error between packages by monitoring a path pattern periodically inserted in an unused area of the data signal in a source package in an opposite package, the package includes: First parity generating means for generating the parity, second parity generating means for generating a parity for a path pattern different from the bit arrangement of the parity, and a main signal and a path pattern after the parity addition based on a control signal. Selecting means for selecting and outputting the path pattern after adding the parity for use, and Parity detection means for outputting an alarm for a time slot in which no parity is detected, expansion means for expanding data to one time slot length after detecting a change point of the alarm, output of the parity detection means, A main signal monitoring system, comprising: an error determination unit that compares outputs of the decompression means and sets an in-package monitoring error when they do not match. 2. A package A having a signal receiving section for inputting a frame-structured data signal and performing predetermined processing and then outputting the processed signal to the outside, and inputting an output of the signal receiving section and performing the predetermined processing. And a package B equipped with a signal transmitting unit for outputting after performing the data transmission, wherein a parity added to the main signal of the data signal at a fixed length is monitored to check data errors in the package. Signal monitoring system that monitors the data pattern between the packages by monitoring the path pattern periodically inserted into the unused area of the data signal in the package of the data transmission source in the package of the data transmission source. In the package A, first parity generation means for generating the parity, and a parity bit for a path pattern different from the bit arrangement of the parity. Second parity generating means for generating parity, selecting means for selecting and outputting the main signal after adding the parity and the path pattern after adding the parity for the path pattern based on the control signal, and receiving the output of the selecting means as an input. Parity detection means for outputting an alarm for a time slot in which no parity is detected, expansion means for expanding data to one time slot length after detecting a change point of the alarm, output of the parity detection means, A main signal monitoring system, comprising: an error determination unit that compares outputs of the decompression means and sets an in-package monitoring error when they do not match.