JP2002304166A - Frequency converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce errors in the frequency set value of a horizontal synchronization circuit due to input frequency by conducting signal operations, in which the horizontal frequency is made approximately constant in matching with the characteristics of a CRT monitor, and the vertical frequency is set to the frequency that is determined by the number of input lines and the vertical fly-back time. SOLUTION: The circuit is provided with a frame memory 31, which stores input video signals, PLLs 36 to 38 which generate read clocks of the memory 31 based on a reference clock, a timing pulse generating circuit 34 which controls the memory 31, a signal discriminating circuit 35 which discriminates the synchronization frequency of the input video signals, and a timing control circuit 39 which controls the circuit 34 and a frequency divider 38, based on the discrimination result of the synchronization frequency, writes the input video signals into the memory 31, makes the horizontal synchronization frequency, the horizontal fly-back interval and the vertical fly-back interval approximately constant, regardless of the horizontal synchronization frequency of the input video signals, reads the video signals from the memory 31 and outputs them and outputs the horizontal synchronization frequency data of output video signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cathode ray tube (CRT: Cat
h0de Ray Tube).

[0002]

2. Description of the Related Art In many cases, a cathode ray tube (CRT: Cathode Ray Tube) is used as a display means or a display element in a television receiver or a personal computer.

First, a display principle of a TV / monitor device using a general CRT will be described with reference to FIG.

A video signal, a horizontal synchronizing signal, and a vertical synchronizing signal are inputted to the monitor device 200 from a TV tuner, a video or a personal computer.

A video signal is amplified by a video control circuit 206 and a video drive circuit 207 and is amplified by a cathode 2 of a CRT 205.
08.

The horizontal synchronizing signal is input to a horizontal synchronizing circuit 202, and the vertical synchronizing signal is input to a vertical synchronizing circuit 212. The horizontal synchronizing circuit 202 and the vertical synchronizing circuit 212 generate pulses or deflection waveforms synchronized with horizontal and vertical frequencies. do it,
The horizontal deflection circuit 203 and the vertical deflection circuit 213 perform CR
The deflection yoke (DY) 210 at T205 is driven.

The electron beam EB is emitted from the cathode 208 in response to the video signal applied to the cathode 208 and accelerated by the acceleration / focusing electrode 209.
Is deflected horizontally and vertically by the magnetic field generated at 10,
Light is emitted by hitting the phosphor applied to the front surface 211 of the CRT 205.

A high voltage is applied to the anode electrode 204 and the acceleration / focusing electrode 209 of the CRT 205 by a high voltage generation circuit 201.

The horizontal deflection circuit 203 includes a high voltage generation circuit 20 for an anode voltage as shown in FIG.
1 and a separate system in which horizontal deflection and high voltage generation are performed by separate circuits as shown in FIG.

The conventional horizontal deflection circuit 203A shown in FIG. 11 has a simple structure, but has an FBT (Fly Back Transformer) 214 for generating a high voltage.
And the horizontal deflection yoke (HDY) 219 at the same time,
It is difficult to simultaneously satisfy the deflection performance and the high voltage performance, and the usable horizontal frequency range is also limited.
In the horizontal deflection, the pincushion distortion correction is performed.
In this example, a vertical parabolic wave generated by using a vertical synchronization pulse is input to the left and right pin distortion correction driving circuit 225 by using a diode modulation circuit, and the left and right pin distortion driving FET 2
23 is corrected.

The horizontal deflection circuit 203A shown in FIG. 11 does not use a stabilizing circuit to which feedback is applied, but may employ a stabilizing circuit in a region where performance is required.

A horizontal deflection circuit 203B of the separate type shown in FIG. 12 includes a horizontal drive circuit 203 'for driving a horizontal deflection yoke (HDY) 219 and an FBT (Fly Back Transfection).
Ormer) 214 is separately provided with a high-voltage drive circuit 201, and in most cases, a high-voltage generation circuit 201 employs a stabilizing circuit to which feedback is applied. In FIG. 12, the power supply + B is
6, 233 and the PWM circuits 227, 234 modulate and control by the chopper method and apply negative feedback to stabilize, but the method is not limited to this. Here, the horizontal pin distortion correction is performed by modulating the power supply of the main deflection circuit with a vertical parabolic wave. This method is used when the frequency range is wide and performance is required.

With respect to vertical deflection, a feedback amplifier circuit 238 as shown in FIG. 13 is generally used, and almost all are integrated into an IC. In the vertical deflection circuit 213, the horizontal deflection circuit 20 is used.
3 does not require a high voltage, but the vertical deflection yoke (V
Since the current flowing through the (DY) 244 has a sawtooth waveform, the flyback voltage generated in the vertical deflection yoke (VDY) 244 during the vertical retrace period increases, so the power supply voltage of the drive circuit is increased only during the vertical retrace period. Such a power supply boosting method is mainly employed.

Here, in the case of a consumer TV that mainly displays TV broadcasts, its signal format is NTSC.
In the case of 525 lines / 60 Hz, and in the case of PAL / SECAM, it is 625/50 Hz.
When a CRT is used as a display element, one type of signal or several types of signals including high-definition broadcasts are handled. Therefore, the horizontal deflection circuit 203 generally employs a conventional system. The vertical deflection is almost 50 Hz or 60 Hz, which facilitates the design of the vertical deflection circuit. In such a deflection system in the consumer TV region, one or several signal formats are handled, and the frequency corresponding to the deflection circuit is a single frequency or several types corresponding thereto.

However, in the case of a monitor for a workstation or a personal computer, a high resolution is required, and since still images such as texts and graphics are mainly handled, the display quality is much more severe than that of a consumer TV. Is required. Because the frequency range is very wide, the frequency band of video control circuit and video drive circuit, the frequency corresponding to horizontal and vertical deflection are wide, and it is difficult to design and manufacture compared to consumer TV. It is based on a separate system instead of a conventional system, and has a wide frequency range for vertical deflection. Therefore, unlike the consumer TV, it is configured to support input signal formats of all frequencies within the corresponding range.

FIG. 14 shows an example of such a horizontal deflection circuit. When the horizontal frequency of the input signal changes, the horizontal image size changes as it is. Therefore, the power supply of the horizontal deflection circuit 203 is controlled by the power supply modulation circuit 233 in accordance with the horizontal frequency, and the S for correcting horizontal image distortion is corrected. Character correction capacitor 23
It is necessary to switch a component called 7 according to the horizontal frequency. In FIG. 14, the horizontal image size control is performed by the power supply modulation circuit 233 and the PWM circuit 234, and the S-shaped correction capacitors 237A and 237B are connected to the FET control circuit 2.
38, S-shaped correction capacitor switching FET 239
A and 239B are switched according to the frequency.

The vertical synchronizing circuit also has to synchronize with a wide range of frequencies like the horizontal synchronizing circuit, and when the vertical frequency changes, the vertical picture size changes. Therefore, an AGC (Automatic Gain Control) is performed so that the amplitude of the driving vertical sawtooth waveform input to the vertical deflection circuit is constant.
rol), and the transient response at the time of signal switching becomes severe, but the burden is smaller than horizontal deflection.

For such a CRT monitor, a signal from various personal computers having different formats is provided by a consumer TV using a CRT corresponding to a single frequency or several kinds of frequencies, or a display element of a fixed pixel such as an LCD. There is pixel conversion as one method used to display the image.

If this method is applied, the horizontal and vertical frequencies can be kept constant even on a CRT monitor. However, a CRT monitor configured to support an input signal format of any frequency within a corresponding range requires the same. Due to the high display quality to be performed, image quality deterioration (blurring of contours, etc.) due to interpolation due to these pixel conversions is not allowed.

[0020]

Therefore, the present applicant has proposed that the horizontal frequency is substantially constant and the vertical frequency is set to the number of input lines and the vertical frequency without performing an interpolation operation such as pixel conversion such as a consumer TV or an LCD monitor. Japanese Patent Application No. 11-358382 has previously proposed a frequency conversion circuit capable of greatly reducing the load on the horizontal deflection circuit by converting the frequency into a frequency determined by the set value of the retrace time and the output horizontal frequency.

FIG. 1 shows a block diagram of the frequency conversion circuit.
It is shown in FIG.

The Video Data and Timing & Control Data input to the frequency conversion circuit 250 shown in FIG. 15 convert an analog video signal into an A / D converter (Analog to Digital Convert).
er), a digital video signal converted to digital data, a synchronization signal or a clock, or a video signal decoded from digital data transmitted by a digital interface such as TMDS, a synchronization signal, a clock, a control signal, and the like.

The signal discriminating circuit 261 converts the horizontal frequency and the vertical frequency of the input signal from the synchronizing signal of the digital video signal and the like.
Alternatively, a video signal section or a signal position is detected, and the data S9 is input to the timing control circuit 260. The timing control circuit 260 is a microcomputer or DSP
Or it is composed of hardware logic or the like.

The timing control circuit 260 calculates the number of dots of the horizontal signal, the number of lines of the vertical signal, etc. from the information of the input signal detected by the signal discrimination circuit 261 or from a table (look-up table) prepared in advance. The read / timing pulse generation circuit 259 uses the frame memory 25
3 is generated.

In FIG. 15, the clock (C
LKR) is the output of the voltage controlled oscillator 256 and is generated by the PLL including the phase comparator 257 and the frequency divider 258. The frequency division ratio of the frequency divider 258 is determined by the timing control circuit 26.
It is set by data S10 from 0. REF-CL
K is a clock input serving as a time reference, and is a signal of a very stable frequency oscillated by a crystal oscillator or the like.

The frequency _{f clk} of the read clock generated by the voltage controlled oscillator 256, the frequency of the frequency division ratio of the frequency divider 258 is set by the data S10 N (N is an integer), the reference clock (REF-CLK) _Is f _ref , this PLL controls the following equation (1).

F _clk = N · f _ref Equation (1) The number of horizontal dots obtained by the timing control circuit 260 is n _H [dots] from the information of the input signal detected by the signal discrimination circuit 261, and the horizontal frequency of the output _Is set as f _H , and the horizontal retrace time is set as n _HBLK [dots].

The timing control circuit 260 is constituted by a microcomputer or DSP is had hard logic, wherein, in order to correspond to properly clock to each dot of the image, the horizontal frequency set value f _H and the reference clock frequency f It is necessary that the relationship with _clk be an integral multiple including the horizontal retrace period. That is, the following equation (2)
Needs to be satisfied.

F _clk = (n _HBLK + n _H ) · f _H Equation (2) From the equation (2) and the equation (1), the value of the value N for dividing the voltage controlled oscillator 270 of the frequency divider 271 is calculated. , N are given by the following equation (3).

[0030]

(Equation 1)

However, since N is an integer, the value actually set is given by the following equation (4).

[0032]

(Equation 2)

Here, int (x) is a function that rounds off the decimal part of x to obtain an integer. Although the calculation is truncated here, the calculation may be performed after rounding off.

By setting the value of N obtained in this way, the frequency f _clkO of the read-out clock (CLKR) actually output is _given by the following equation (5).

[0035]

(Equation 3)

The timing pulse generation circuit 259 determines a read enable signal (DER) for the horizontal cycle from the clock frequency set in this manner, and for the vertical cycle, the cycle is determined by the number of input signal lines and the vertical blanking period. A read permission signal (DER) is generated so as to be the sum of the line number setting values. As a result, the horizontal frequency f of the actually output signal
_HO , horizontal retrace time t _HBLKO , vertical frequency f _VO, and vertical retrace time t _{VB LKO} are represented by the following equations (6), (7), (8), and (9).

[0037]

(Equation 4)

Here, n _VBLK [line] is a vertical blanking time set value, and n _V [1ine] is the number of input vertical lines.

In equation (6), since the division ratio of the divider 258 is calculated as an integer when calculating the division ratio, an error occurs between the actual output horizontal frequency and the set horizontal frequency. _ref of accuracy is shown that is substantially f _H is higher.

The read permission signal (DER), the horizontal / vertical synchronization signal, and the read clock are input to the memory controller 255, and the video data is read from the frame memory 253.

From equation (8), the output vertical frequency is a value determined by (the number of vertical lines + vertical retrace time) and the output horizontal frequency, but the number of horizontal dots and the number of vertical lines in the video section are the same as those of the input. Yes, no interpolation.

The read video data is finally D / A
It is converted into an analog signal by a converter (Digital to Analog Converter) 254.

Therefore, the value of f _H is
2. If the output horizontal frequency is fixed to a value corresponding to the horizontal deflection circuit 203, the output horizontal frequency is substantially constant although there is an error generated by converting it into an integer when obtaining the value of N. (Return time) and the output horizontal frequency. Further, as can be seen from Equations (4) and (6), this error is smaller as the frequency of the reference clock is lower than the product of the output horizontal frequency and the number of input dots, and the frequency division ratio of the frequency divider is larger. Become. In other words, if the value of this reference clock is determined so as to fall within the frequency correspondence range of the horizontal synchronization circuit 202 and the horizontal deflection circuit 203, and if a high frequency accuracy is selected by using a crystal oscillator or the like, the horizontal system can be adjusted. Can realize a substantially single frequency response.

By performing the frequency conversion by the above hardware and system, the horizontal synchronization circuit 202 and the horizontal deflection circuit 203 have a substantially single frequency, and the vertical synchronization circuit 212 and the vertical deflection circuit 213 have the conventional C frequency.
As with the RT monitor, a circuit configuration that can support a wide range can be employed.

From the equation (6), when calculating the frequency division ratio of the frequency divider 258, an integer is calculated for calculation, so that an error occurs between the actual output horizontal frequency and the set horizontal frequency.
Since the error (N−N _A ) of N is 0 ≦ (N−N _A ) <1, the frequency error Δf _HO is given by the following equation (10).

[0046]

(Equation 5)

That is, the lower the frequency of the reference clock, the smaller the frequency error. Therefore, in terms of the horizontal frequency setting error, the frequency f _{ref of the} reference clock is used.
It is more desirable to lower. However, as can be seen from equation (1), the multiplication ratio in the PLL increases. This means that the jitter (fluctuation of the clock frequency) in the PLL becomes large. Therefore, from the viewpoint of the jitter performance, although the frequency error becomes large, it is desirable that the frequency f _{ref of the} reference clock be high.

A description will be given below of the effect of an increase in the frequency error.

FIG. 16 shows the horizontal synchronizing circuit 20 shown in FIG.
2 shows a detailed block configuration example.

The horizontal synchronizing signal is supplied to a horizontal phase control circuit 264.
And to the frequency measurement circuit 262. In the case of the above system, HSYNC OUT corresponds to a horizontal synchronization signal.

The frequency measurement circuit 262 is unnecessary in a system in which only a single frequency is input. Since the above system has a substantially single horizontal frequency, it is desirable that the frequency measurement circuit 262 be not provided. Frequency measurement circuit 262
Is a part that controls the position of the display area on the screen by controlling the phase of the horizontal synchronization signal. This is not the case depending on the system, or if another PLL loop is used to control the phase within this loop. There is also.

The phase comparator 265 is connected to the horizontal phase control circuit 2
The phase of the 64 output pulses S14 is compared with the phase of a pulse S18 called a flyback pulse generated during the horizontal retrace period by the horizontal deflection circuit 269, and the voltage output S corresponding to the phase difference is determined.
Generate 15.

The output S13 of the phase comparator 265 is input to the voltage controlled oscillator 267 via the smoothing filter 266. Thereby, the oscillation frequency of the voltage controlled oscillator 267 is controlled so that the phase difference becomes small. Voltage controlled oscillator 2
The output pulse S17 of the horizontal drive pulse control circuit 26
8 and is controlled to have a width suitable for the horizontal deflection circuit 269 and is input to the horizontal deflection drive circuit 270.
9 is driven.

In addition to this signal path, a signal for controlling the horizontal phase and an oscillation frequency control signal for setting the center frequency of the voltage-controlled oscillator 267 are input to the voltage-controlled oscillator 267, depending on the circuit type or control method. You. These control signals may be analog voltages or digital data when controlled by a microcomputer via a bus.

Examples of the phase comparator 265 include an exclusive OR circuit and a multiplier, a frequency phase comparator using a flip-flop, and the like.
In the case of LL, even if the horizontal synchronizing signal is lost, the deflection circuit may be destroyed if the frequency is not stable. Therefore, a frequency phase comparator whose frequency is not stable when the horizontal synchronizing signal is lost is almost used. Instead, a circuit using an exclusive-OR circuit or a multiplier is usually used. In this case, the oscillation frequency of the voltage controlled oscillator 267 is
The frequency is set to be substantially equal to the frequency of the input horizontal synchronization signal. If the set frequency is deviated from the input frequency, the difference between the horizontal synchronization signal and the flyback pulse returned from the horizontal deflection circuit 269 is equal to the frequency difference and P.
A phase error determined by the loop gain of the LL loop occurs. When viewed on the screen, this is recognized as a shift in the horizontal position of the screen. Normally, the pull-in range of the horizontal synchronizing circuit is about ± 5% with respect to the input frequency, and when the frequency error is shifted by about several% with respect to the center frequency, this horizontal position shift becomes visible.

In the case of a conventional monitor configured to support input signal formats of all frequencies within the corresponding range, a frequency measurement circuit 262 for a synchronization signal is provided as shown in FIG. The frequency of the voltage controlled oscillator 267 is controlled by the oscillation frequency control circuit 263 according to the frequency measurement result. Even in a system where the horizontal frequency is substantially a single frequency as described above, if a frequency measurement is performed using the same method, the frequency error between the horizontal synchronization signal and the flyback pulse returned from the horizontal deflection circuit 269 can be reduced. However, what can be deleted with a single frequency cannot be deleted, and the system cannot be simplified.

As described above, in order to simplify the system, it is desired to lower the frequency f _{ref of the} reference clock. However, if so, the jitter performance of the PLL deteriorates, and it is difficult to achieve both.

The present invention has been made in view of such circumstances, and has as its object the purpose of always keeping the horizontal frequency substantially constant according to the characteristics of the CRT monitor, and the vertical frequency being the frequency determined by the number of input lines and the vertical retrace time. In order to reduce the error of the frequency setting value of the horizontal synchronization circuit with respect to the input frequency without performing the signal operation such that the interpolation operation is performed and further reducing the frequency of the reference clock and increasing the multiplication ratio of the PLL. To provide a CRT monitor frequency conversion circuit.

[0059]

According to the present invention, the horizontal synchronizing frequency data of the output video signal calculated in the frequency conversion circuit is output, thereby controlling the oscillation frequency of the voltage controlled oscillator of the horizontal synchronizing circuit.

[0060] The frequency conversion circuit according to the present invention comprises: storage means for storing an input video signal; clock generation means for generating a read clock for the storage means based on a reference clock; and a horizontal synchronizing signal for the input video signal. And a timing for generating a write control signal synchronized with the vertical synchronization signal, generating a read control signal from a read clock generated by the clock generation means, and controlling writing and reading of the input video signal to and from the storage means. A pulse generating unit, a signal determining unit for determining a horizontal and vertical synchronization frequency of the input video signal, and controlling operations of the clock generating unit and the timing pulse generating unit based on a determination result of the signal determining unit. Then, the input video signal is written into the storage means, and the horizontal synchronization frequency of the input video signal is Regardless, the video signal is read from the storage means and output so that the horizontal synchronization frequency, the horizontal retrace period and the vertical retrace period are substantially constant, and the timing control for outputting the horizontal synchronization frequency data of the output video signal is performed. Means.

[0061]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The present invention is applied to, for example, a monitor device 100 having a configuration as shown in FIG.

In the monitor device 100 shown in FIG. 1, an input video signal S 11 is supplied from an input terminal 11 to a frequency conversion circuit 30 via an input interface circuit 20.
Further, a horizontal and vertical synchronization signal Ssync corresponding to the input video signal S11 is supplied from the input terminal 12 to the frequency conversion circuit 30 via the input interface circuit 20.

In this case, it is assumed that the video signal S11 is a three primary color signal composed of red, green and blue signals.
The frequency conversion circuit 30 has a frame memory 31 as shown in FIG. 2, and converts the synchronization frequency of the supplied video signal S11 to output a video signal.

The output video signal is subjected to processing such as gamma correction in the video control circuit 41 and then applied to the cathode 51 of the color CRT 50 via the video drive circuit 42.

The frequency conversion circuit 30 supplies a horizontal synchronization signal Hsync synchronized with the output video signal to the horizontal synchronization circuit 61. The horizontal synchronization circuit 61 generates a pulse or a deflection waveform of a horizontal frequency synchronized with the horizontal synchronization signal Hsync, and a horizontal deflection current is formed by the horizontal deflection circuit 62. Then, the horizontal deflection current is supplied to the horizontal deflection coil 81, and the horizontal deflection of the color CRT 50 is performed.

Further, a horizontal pulse is taken out from the horizontal deflection circuit 62, and the horizontal pulse is supplied to a high voltage generation circuit 63 to form a high voltage.
Is supplied to the anode electrode 52 and the like.

The frequency conversion circuit 30 supplies a vertical synchronization signal Vsync synchronized with the output video signal to the vertical synchronization circuit 71. The vertical synchronization circuit 71 generates a pulse or a deflection waveform of a vertical frequency synchronized with the vertical synchronization signal Vsync, and a vertical deflection current is formed by the vertical deflection circuit 72. Then, the vertical deflection current is supplied to the vertical deflection coil 82 to perform vertical deflection of the color CRT 50.

In the color CRT 50, an electron beam EB is emitted from the cathode 51 according to a video signal applied to the cathode 51. After being accelerated by the accelerating / focusing electrode 83, the electron beam EB is deflected in the horizontal and vertical directions by a magnetic field generated by the deflection yoke 80, and hits the phosphor applied to the front surface 53 of the color CRT 50 to emit light. The color CRT 50 displays an image according to the image signal by scanning the front surface 53 with the electron beam EB.

A high voltage is applied to the anode electrode 52 and the acceleration / focusing electrode 83 of the CRT 50 by a high voltage generating circuit 63.

The frequency conversion circuit 30 is configured, for example, as shown in FIG.

This frequency conversion circuit 30 is an improvement of the frequency conversion circuit 250 shown in FIG.
Is input to the frame memory 31, and the video data S1 read from the frame memory 31 is supplied to the D /
A converter (Digital to Analog Converter) 32, a memory controller 33 for controlling writing and reading of data to and from the frame memory 31, Timing & Control
A timing pulse generating circuit 34 and a signal discriminating circuit 35 to which Data is input, a voltage controlled oscillator 36 constituting a PLL for generating a clock, a phase comparator 37 and a frequency divider 38,
It comprises a timing control circuit 39 which controls the operations of the timing pulse generation circuit 34 and the frequency divider 38 and has a function of outputting frequency data HFREQ.

The phase comparator 37 further receives a reference clock REF-CLK serving as a time reference.

Also, Video Data and Timing & Control Dat
a is a digital video signal, a synchronizing signal or a clock converted into digital data in the input interface circuit 20, or a video signal, a synchronizing signal, a clock, a control signal, etc. obtained by decoding digital data transmitted by a digital interface such as TMDS. It is.

In the frequency conversion circuit 30, the signal discrimination circuit 35 detects the horizontal frequency and vertical frequency of the input signal or the video signal section and signal position from the synchronization signal of the digital video signal and the like, and converts the data S9 to the timing. Input to the control circuit 39. The timing control circuit 39 is configured by a microcomputer, a DSP, or a hardware logic.

The timing control circuit 39 calculates the number of dots of the horizontal signal, the number of lines of the vertical signal, etc. from the information of the input signal detected by the signal discriminating circuit 35, or from a table (look-up table) prepared in advance. The control signal S5 to be read and written into the frame memory 31 by the timing pulse generation circuit 34 is generated.

The control signal S5 varies depending on the memory used and the like. For example, a horizontal control signal (HDW), a vertical control signal (VDW), a write enable signal (DEW) as shown in FIGS.
And so on. Input clock according to these control pulses
If writing is performed by (CLK), writing to the frame memory 31 is properly performed by the number corresponding to the resolution of the input video signal. In FIG. 3, M [i] and M [i + 1] represent data at addresses i and i + 1 in the frame memory 31.

In the frequency conversion circuit 30, the clock (CLKR) on the read side is the output of the voltage controlled oscillator 36, and is generated by the PLL including the frequency divider 38 and the phase comparator 37. The frequency division ratio of frequency divider 38 is set by data S10 from timing control circuit 60. REF
-CLK is a clock input serving as a time reference, and is a signal of a very stable frequency oscillated by a crystal oscillator or the like.

Note that there are various types of clock generation circuits, and the clock generation circuit is not limited thereto.
This configuration will be described.

The frequency of the read clock generated by the voltage controlled oscillator 36 is f _clk , the frequency division ratio of the frequency divider 38 set by the data S 10 is N (N is an integer), and the frequency of the reference clock (REF-CLK) the When _{f ref,} in the PLL, is controlled to be the following equation (11).

F _clk = N · f _ref Equation (11) From the information of the input signal detected by the signal discriminating circuit 35,
The number of horizontal dots obtained by the timing control circuit 39 is represented by n _H [d
ots], the set value of the output horizontal frequency is f _H , and the horizontal retrace time is n _HBLK [dots].

The timing control circuit 39 is constituted by a microcomputer, a DSP or a hard logic. Here, in order to make the clock correspond to each dot of the video, the horizontal frequency set value f _H and the reference clock frequency f It is necessary that the relationship with _clk be an integral multiple including the horizontal retrace period. That is, the following equation (12)
Needs to be satisfied.

F _clk = (n _HBLK + n _H ) · f _H Equation (12) From the equations (12) and (11), the value of the value N for dividing the voltage controlled oscillator 36 of the frequency divider 38 is calculated. , N are given by the following equation (13).

[0084]

(Equation 6)

However, since N is an integer, the value actually set is given by the following equation (14).

[0086]

(Equation 7)

Here, int (x) is a function of rounding down the decimal part of x to an integer. Although the calculation is truncated here, the calculation may be performed after rounding off.

By setting the value of N obtained in this way, the frequency f _clkO of the read-out clock (CLKR) actually output is _given by the following equation (15).

[0089]

(Equation 8)

From the clock frequency thus set, the timing pulse generator 34 determines a read enable signal (DER) for the horizontal period, for example, as shown in FIG. 5, and for the vertical period, the period is determined by the input signal. The read permission signal (DER) is generated as shown in FIG. 6 by determining the sum of the number of lines and the set number of lines in the vertical flyback period.
That is, the horizontal frequency f _HO , the horizontal retrace time t _HBLKO , the vertical frequency f _VO and the vertical retrace time t _VBLKO of the actually output signal are _represented by the following equations (16), (17),
Expressions (18) and (19) are obtained.

[0091]

(Equation 9)

Here, n _VBLK [line] is a vertical blanking time set value, and n _V [1ine] is the number of input vertical lines.

In the equation (16), since the frequency division ratio of the frequency divider 38 is calculated and converted into an integer, an error occurs between the actual output horizontal frequency and the set horizontal frequency. _ref of accuracy is shown that is substantially f _H is higher.

The read permission signal (DER), the horizontal / vertical synchronization signal, and the read clock are input to the memory controller 33, and the video data is read from the frame memory 31.

From equation (18), the output vertical frequency is a value determined from (the number of vertical lines + vertical retrace time) and the output horizontal frequency, but the number of horizontal dots and the number of vertical lines in the video section are the same as those of the input. Yes, no interpolation.

The read video data is finally stored in the D / A
It is converted into an analog signal by a converter (Digital to Analog Converter) 32.

Therefore, the value of f _H is
1. If the output horizontal frequency is fixed to a value corresponding to the horizontal deflection circuit 62, the output horizontal frequency is substantially constant although there is an error caused by converting it into an integer when obtaining the value of N, and the vertical frequency is (the number of vertical lines + vertical line). (Return time) and the output horizontal frequency. Further, as can be seen from equations (14) and (16), this error is smaller as the frequency of the reference clock is lower than the product of the output horizontal frequency and the number of input dots, and the frequency division ratio of the frequency divider is larger. Become. In other words, the horizontal synchronization circuit 61 and the horizontal deflection circuit 62 fall within the frequency range.
If the value of the reference clock is determined, and a crystal oscillator or the like is adopted and a high-precision one is selected, it is possible to realize substantially a single frequency in the horizontal system.

[0098] Here, with respect to the set frequency _{f H,} the frequency of the horizontal synchronizing signal HSYNCOUT actually output is calculated by the aforementioned formula (16). That is, this is the frequency measurement data itself obtained by the frequency measurement. Therefore, if this data is processed and output in accordance with the control method of the voltage controlled oscillator of the horizontal synchronization circuit 61, the frequency f _{ref of the} reference clock is higher than the desired value, and the horizontal frequency output for the set frequency f _H is obtained. Even if there is some error in the frequency of the synchronization signal, the center frequency of the horizontal synchronization circuit 61 automatically follows the actually output frequency.
The horizontal phase error in the synchronized state is small.

Therefore, in the frequency conversion circuit 30, the frequency data HFREQ is output from the timing control circuit 39.
Is output.

By performing the frequency conversion by the above hardware and system, the horizontal synchronization circuit 61 and the horizontal deflection circuit 62 have a substantially single frequency and the vertical synchronization circuit 7
As for the 1 and vertical deflection circuit 72, a circuit configuration that can support a wide range can be adopted as in the conventional CRT monitor device.

FIG. 7 shows a detailed block configuration example of the horizontal synchronization circuit 61 shown in FIG. The horizontal synchronizing circuit 61 also has a PLL configuration, and there are some other systems besides the example shown in FIG. 7, but the basic concept is the same, so that this example will be described.

In the horizontal synchronization circuit 61, the horizontal synchronization signal HSYNC OUT output from the timing control circuit 39 of the frequency conversion circuit 30 is input to the horizontal phase control circuit 164. The frequency data HFREQ output from the timing control circuit 39 of the frequency conversion circuit 30 is supplied to the oscillation frequency control circuit 163.

The phase comparator 165 is provided with the horizontal phase control circuit 1
64 output pulses S14 and a pulse S called a flyback pulse generated during a horizontal flyback period by the horizontal deflection circuit 62.
18 and a voltage output S1 corresponding to the phase difference.
5 is generated.

The output S15 of the phase comparator 165 is input to the voltage controlled oscillator 167 as the control voltage S16 via the smoothing filter 166. Thereby, the voltage controlled oscillator 1
The oscillation frequency of 67 is controlled to reduce the phase difference. The output pulse S17 of the voltage control oscillator 167 is input to the horizontal drive pulse control circuit 168, and the horizontal deflection circuit 62
Is controlled to have a width suitable for the horizontal deflection driving circuit 169 to drive the horizontal deflection circuit 62.

In addition to this signal path, the signal for controlling the horizontal phase and the oscillation frequency control signal for setting the center frequency of the voltage-controlled oscillator 167 are supplied from the oscillation frequency control circuit 163 to the voltage control circuit 163, although this differs depending on the circuit type or control method. It is input to the control oscillator 167.

The oscillation frequency control signal is generated by the oscillation frequency control circuit 163 based on the frequency data HFREQ, and may be an analog voltage.
When controlled by a microcomputer via a bus, the data is digital data.

The example shown in FIG. 8 is an example in which the oscillation frequency control circuit 163A of the horizontal synchronization circuit 61A is constituted by an analog circuit, and the dotted line is formed as an LSI.
In this case, the frequency data HFREQ is input from the frequency conversion circuit 30 to the oscillation frequency control circuit 163A via the D / A converter 172. As the control, a method may be used in which a voltage corresponding to the frequency data HFREQ whose setting frequency is determined in an analog manner and only the difference with respect to this frequency is controlled.

Further, the example shown in FIG. 9 has a configuration in which the control is performed via the BUS, and is an example in which the dotted line is implemented as an LSI. In this case, the frequency data HFREQ is
The signal is converted into a US protocol and transmitted to the BUS receiving circuit 174 of the horizontal synchronization circuit 61B. There are various BUSs such as a serial BUS and a parallel BUS.

[0109]

According to the present invention, a signal operation is performed such that the horizontal frequency is always substantially constant while the frequency _{fref of the} reference clock is set to a relatively high level, and the vertical frequency is a frequency determined by the number of input lines and the vertical retrace time. Can be performed without performing an interpolation operation, and the frequency set value of the horizontal synchronization circuit can be reduced with respect to the input frequency without providing a frequency measurement circuit or the like.

Thus, the PLL used for signal processing can be used.
The multiplication ratio of the circuit can be kept low, and the jitter characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a monitor device to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of a frequency conversion circuit in the monitor device.

FIG. 3 is a timing chart showing a write control operation in a horizontal cycle in a frame memory in the frequency conversion circuit.

FIG. 4 is a timing chart showing a write control operation to the frame memory in a vertical cycle.

FIG. 5 is a timing chart showing a read control operation in a horizontal cycle from the frame memory.

FIG. 6 is a timing chart showing a read control operation in a vertical cycle from a frame memory.

FIG. 7 is a block diagram showing a detailed configuration example of a horizontal synchronization circuit in the monitor device.

FIG. 8 is a block diagram showing a specific configuration example of the horizontal synchronization circuit.

FIG. 9 is a block diagram showing another specific configuration example of the horizontal synchronization circuit.

FIG. 10 is a block diagram for explaining the display principle of a TV / monitor device using a CRT.

FIG. 11 is a configuration diagram of a conventional horizontal deflection circuit.

FIG. 12 is a configuration diagram of a horizontal deflection circuit of a separate system.

FIG. 13 is a configuration diagram of a vertical deflection circuit.

FIG. 14 is a configuration diagram of a separate type horizontal deflection circuit compatible with multi-scan.

FIG. 15 is a configuration diagram of a frequency conversion circuit proposed earlier.

FIG. 16 is a block diagram showing a detailed configuration example of the horizontal synchronization circuit shown in FIG. 10;

[Explanation of symbols]

11 input terminals, 12 input terminals, 20 input interface circuits, 30 frequency conversion circuits, 31 frame memories, 32 D / A converters, 33 memory controllers, 34 timing pulse generation circuits, 35 signal discrimination circuits, 36 voltage controlled oscillators, 37 Phase comparator, 38
Frequency divider, 39 timing control circuit, 41 video control circuit, 42 video drive circuit, 50 color CRT, 5
1 cathode, 52 anode electrode, 53 front face, 61,
61A, 61B horizontal synchronization circuit, 62 horizontal deflection circuit,
63 high voltage generation circuit, 71 vertical synchronization circuit, 72 vertical deflection circuit, 81 horizontal deflection coil, 82 vertical deflection coil, 83 acceleration / focusing electrode, 100 monitoring device, 16
3,163A oscillation frequency control circuit, 164 horizontal phase control circuit, 165 phase comparator, 166 smoothing filter,
167 voltage controlled oscillator, 168 horizontal drive pulse control circuit, 169 horizontal deflection drive circuit, 172 D / A converter, 173 BUS transmission circuit, 174 BUS reception circuit, EB electron beam

Claims (6)

[Claims] 1. A storage means for storing an input video signal, a clock generation means for generating a read clock for the storage means based on a reference clock, and a clock synchronized with a horizontal synchronization signal and a vertical synchronization signal of the input video signal Timing pulse generating means for generating a write control signal, generating a read control signal from a read clock generated by the clock generating means, and controlling writing and reading of an input video signal to and from the storage means; A signal discriminating means for discriminating the horizontal and vertical synchronization frequencies of the video signal; and controlling the operations of the clock generating means and the timing pulse generating means based on the discrimination result of the signal discriminating means. Write to the storage means, regardless of the horizontal synchronization frequency of the input video signal Timing control means for reading and outputting the video signal from the storage means so that the horizontal retrace period and the vertical retrace period are substantially constant, and outputting the horizontal synchronization frequency data of the output video signal. Frequency conversion circuit. 2. The timing pulse generating means writes the same number of data as the number of pixels determined from the number of horizontal dots and the number of vertical lines of the input video signal signal to the storage means based on the result of the determination by the signal determining means. The frequency conversion circuit according to claim 1, wherein the frequency conversion circuit generates a write control signal. 3. The timing control means according to claim 1, wherein said read clock is a horizontal video period of an input video signal within an output horizontal cycle based on a determination result by said signal determination means and a set value of an output horizontal frequency and a horizontal retrace time. The ratio of the frequency of the read clock generated by the clock generation means to the reference clock frequency is set so that the horizontal video period is equal in number to the number of dots of (1).
The described frequency conversion circuit. 4. The timing control means converts a blanking time into a number of dots and a number of lines based on a horizontal frequency set value and a frequency of a read clock generated by the clock generating means. 4. The frequency conversion circuit according to claim 3, wherein a vertical blanking time is set. 5. The timing control means according to claim 1, wherein said read control signal of said storage means is read by said timing pulse generation means based on a read clock generated by said clock generation means. 4. The frequency conversion circuit according to claim 3, wherein the same number of dots are generated in the horizontal video period as the number of dots in the period. 6. The timing control means, based on a result of the discrimination by the signal discrimination means and a set vertical blanking time, determines the number of lines read in a vertical video period within an output vertical cycle by the number of lines of an input video signal. 4. The frequency conversion circuit according to claim 3, wherein a read control signal of a vertical cycle of said storage means having the same number as the number is generated by said timing pulse generation means.