JPH1070672A - Amplitude correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplitude correction circuit by which an amplitude is corrected without complicated component constant design by improving a circuit drift. SOLUTION: A/D-converted luminance and color difference signals 103, 109 are stored in a line memory circuit 128 and in the case of reading a stored signal, a read frequency by a read clock 124 is modulated in response to fluctuation in a high voltage detection signal from a high voltage detection circuit 116 and the digital signal readout by a read clock is D/A-converted to restore a signal into analog luminance and color difference signals thereby making correction so that a horizontal amplitude on a screen is made constant. Since an amplitude is corrected by modulating a video signal itself through digital processing, a circuit drift generated by a conventional analog correction is eliminated and a complicated analog circuit design is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude correction circuit mounted on a television receiver or the like for correcting a change in horizontal and vertical amplitudes of a screen caused by a change in high voltage supplied to a cathode ray tube anode.

[0002]

2. Description of the Related Art Conventionally, in the deflection of a color cathode ray tube (hereinafter referred to as CRT), the radius of curvature of the fluorescent screen is larger than the distance on the tube axis from the center of deflection to the fluorescent screen (the fluorescent screen is almost flat). The raster on the phosphor screen is distorted like a pincushion. That is,
The horizontal amplitude gradually decreases from the top and bottom of the screen to the center.

In order to correct such pincushion distortion,
It is necessary to modulate the horizontal deflection current in a parabolic manner with a vertical cycle.

The left and right pincushion distortion correction circuits include a saturable reactor system, a diode modulation system, a power supply voltage modulation system, and the like. Among them, the diode modulation method is such that even when parabolic modulation is applied to the deflection current to correct the pincushion distortion, the collector pulse of the horizontal output transistor is always constant, and the secondary voltage of the flyback transformer does not fluctuate. There is a feature.

However, when a high-luminance portion appears in a relatively wide range on the screen of the CRT, the secondary high voltage drops due to an increase in the anode current, and the horizontal and vertical amplitudes of the portion widen. The change in the horizontal amplitude or the vertical amplitude with respect to the change in the secondary high voltage has the characteristics shown in FIG. As a result, as shown in FIG. 5B, the rectangular window pattern on the screen is distorted in a trapezoidal shape, and the vertical lines are bent at the left and right ends of the screen.

FIG. 6 is a circuit diagram showing an example of a conventional right and left pincushion distortion correction circuit of a diode modulator system called a positive system. This circuit is described in Japanese Utility Model Laid-Open No. 4-114260 proposed by the present applicant.

In FIG. 6, a left and right pincushion distortion correcting circuit includes a horizontal output circuit 1 of a diode modulation system in which a sawtooth current is supplied to a horizontal deflection coil, and one end of a primary winding connected to a horizontal output transistor 10 of the horizontal output circuit 1. Connected to the collector of
The other end of the primary winding is connected to the DC power supply + B1, the secondary winding is connected to the anode of the CRT as a high voltage winding, and the flyback transformer 11 is connected to the anode of the CRT, and the detection resistor 14 is connected to the vertical deflection coil 13 in series. Miller integrating circuit 15 for integrating a sawtooth wave voltage to generate a parabolic wave voltage having a vertical period.
An amplification / output circuit 16 for amplifying this parabolic wave voltage and outputting it to the modulation capacitor 6 in the horizontal output circuit 1;
A resistor 22 is provided between a terminal 24 on the return side of the high voltage winding of the flyback transformer 11 and the base of the output transistor 18 to transmit a voltage proportional to the high voltage ripple generated at the terminal 24 to the base of the transistor 18. And circuit means including a capacitor 23. The voltage proportional to the high voltage ripple generated at the terminal 24 is obtained from the capacitor 25 connected between the return terminal 24 of the high voltage winding and the reference potential point.

The horizontal output circuit 1 includes a first resonance circuit including a horizontal deflection coil 2, an S-shaped correction capacitor 3, and a resonance capacitor 4, a modulation coil 5, a modulation capacitor 6,
A second resonance circuit including a resonance capacitor 7 is connected in series, and switching is performed by two diodes 8 and 9 and a horizontal output transistor 10. A pulse having a horizontal period is input to the base of the horizontal output transistor 10. ing.

The amplifying / output circuit 16 is composed of an amplifying stage transistor 17 and an output stage transistor 18. The parabolic wave voltage from the Miller integrating circuit 15 is supplied to the base of the amplifying stage transistor 17.
7 is connected to a DC power supply + B2 via a load resistor 19, the collector of the transistor 17 is connected to the base of the output transistor 18, the emitter of the transistor 18 is connected to the reference potential point, and the collector of the output transistor 18 is connected. An output is supplied to one end of the modulation capacitor 6. The resistors 20 and 21 are connected between the collector of the transistor 18 and the emitter of the transistor 17.
Feedback circuit is connected.

In the circuit shown in FIG. 6, when a signal having a high luminance portion over a relatively wide area of the screen is received as shown in FIG. 5B, the return terminal 24 of the flyback transformer 11 is The voltage gradually decreases, and when the black portion is reached again, the voltage gradually increases. When this voltage change is superimposed on the base voltage (parabolic wave voltage) of the output stage transistor 18 via the resistor 22 and the capacitor 23, the collector voltage waveform of the output stage transistor 18 (that is, the voltage across the modulation capacitor 6) becomes On the parabolic wave voltage, a voltage that rises in the white portion and falls when it turns black again is superimposed. Since the sum of the voltages of the S-shaped correction capacitor 3 and the modulation capacitor 6 is equal to the voltage of the DC power supply + B1, the voltage across the S-shaped correction capacitor 3 and the voltage across the modulation capacitor 6 change in opposite polarities. Therefore, the horizontal deflection current flowing in the horizontal deflection coil 2 works so as to gradually decrease in the white portion and increase again in the black portion. As a result, it is possible to prevent the horizontal amplitude from unnecessarily widening due to a decrease in high voltage when receiving an image of a high luminance portion.

In this manner, on the screen, the white square portion is not trapezoidal distortion but rather square, and the vertical lines at the left and right ends of the screen are corrected so as to be closer to a straight line.

The conventional amplitude correction circuit shown in FIG. 6 and the like described above is an analog signal processing circuit, and in the case of correcting horizontal amplitude and bending due to high-voltage fluctuation, correction is performed by analog processing. There is a circuit drift, and it is necessary to perform a complicated circuit design in order to prevent a phase shift due to a circuit time delay. Further, every time the inductance of the deflection coil or the curvature of the picture tube is changed due to a model change or the like, it is necessary to design component constants, and the operation is complicated.

[0013]

As described above, in the conventional circuit, in the case of correcting the amplitude and the bending due to the high voltage fluctuation, the correction is performed by analog processing, so that there is a circuit drift and a circuit time is reduced. In order to prevent a phase shift due to a delay, it was necessary to design a complicated circuit. Further, every time the inductance of the deflection yoke or the curvature of the picture tube is changed, it is necessary to set the component constant, which is complicated in designing.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an amplitude correction circuit capable of improving circuit drift and performing amplitude correction without having to design complicated component constants. It is.

[0015]

According to a first aspect of the present invention, there is provided an amplitude correction circuit for inputting a high voltage detecting means for detecting a fluctuation of a DC high voltage supplied to a cathode ray tube anode, and an analog type luminance signal and color difference signal. A / D conversion means for respectively converting digital signals, memory means for storing the A / D-converted digital signals, and control of writing and reading to and from the memory means. When reading data, the read / write control means for controlling the read speed to be modulated in accordance with the high-voltage fluctuation detected by the high-pressure detection means, and the signal read from the memory means are analogized again. And a D / A conversion means for converting into a luminance signal and a color difference signal.

According to a second aspect of the present invention, in the amplitude correction circuit according to the first aspect, the memory means comprises a line memory circuit, and the write / read control means comprises:
On the basis of the horizontal synchronization signal, a first timing signal of a horizontal cycle and a first timing signal for writing at a frequency that is a predetermined multiple of the horizontal frequency are used.
And a clock generation circuit for generating a second clock having a predetermined multiple of a horizontal frequency different from the above, and oscillating a clock based on the second clock, wherein the oscillation frequency is equal to the high voltage. A digitally controlled oscillator that is modulated in accordance with a high-voltage fluctuation detected by the detecting unit, a D / A converter that converts an output of the digitally controlled oscillator into an analog signal, and outputs the analog signal as a read clock to the memory unit; 1 to generate a write timing signal based on the first timing signal and the first clock.
A timing generation circuit for generating a read timing signal based on a read clock from the A converter.

According to a third aspect of the present invention, in the amplitude correction circuit according to the first aspect, the memory means is constituted by a field memory circuit, and the write / read control means is configured to determine a vertical period based on a vertical synchronization signal. A clock generation circuit that generates a first timing signal, a first clock for writing at a frequency that is a predetermined multiple of the vertical frequency, and a second clock that has a frequency that is a predetermined multiple different from the vertical frequency; Oscillating a clock based on a second clock, wherein a digitally controlled oscillator whose oscillation frequency is modulated in accordance with a high-voltage fluctuation detected by the high-voltage detecting means, and converting an output of the digitally controlled oscillator into an analog signal A D / A converter for outputting to the memory means as a read clock; the first timing signal and the first clock; While generating a write timing signal on the basis of said first timing signal and said D /
A timing generation circuit for generating a read timing signal based on a read clock from the A converter.

According to a fourth aspect of the present invention, in the amplitude correction circuit of the first aspect, the high voltage detecting means rectifies a secondary high voltage pulse of a flyback transformer connected to a horizontal output stage of a horizontal deflection circuit. A rectifier circuit that obtains a DC high voltage and supplies the same to the cathode ray tube anode, and a resistance circuit that divides and detects the DC high voltage obtained by the rectifier circuit.

According to a fifth aspect of the present invention, in the amplitude correction circuit of the first aspect, the high voltage detecting means rectifies a secondary high voltage pulse of a flyback transformer connected to a horizontal output stage of a horizontal deflection circuit. A rectifier circuit that obtains a DC high voltage and supplies it to the cathode ray tube anode, and a cathode ray tube anode connected between the return terminal of the secondary winding of the flyback transformer and a reference potential point and flowing through the secondary winding. And a capacitor for detecting a voltage proportional to the current.

According to the first aspect of the present invention, the luminance signal and the color difference signal which have been subjected to the A / D conversion are once stored in the memory means, and when the stored signals are read, the read speed by the read clock is determined by the high voltage detection means. The digital signal is modulated according to the magnitude of the high-voltage detection signal from the controller, and the read digital signal is D / A-converted into an analog luminance signal and a color difference signal, and is corrected so that the amplitude on the screen becomes constant. Since the amplitude is corrected by modulating the video signal itself by digital processing, there is no circuit drift caused by analog processing as in the prior art, and there is no need for complicated analog circuit design.

According to the second aspect of the present invention, the horizontal amplitude can be corrected.

According to the third aspect of the invention, the vertical amplitude can be corrected.

According to the fourth and fifth aspects of the present invention, the high voltage detecting means may detect a voltage proportional to the high voltage, or may detect a CRT anode current.

[0024]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a horizontal amplitude correction circuit according to one embodiment of the present invention, and FIG. 2 is a characteristic diagram for explaining the operation of FIG. FIG. 4 is a block diagram of a display device such as a television receiver in which the amplitude correction circuit of FIGS. 1 and 3 is used.

The description starts with the display device shown in FIG. In FIG. 4, the display device receives an analog luminance signal Y and color difference signals RY and BY, converts them into digital signals, writes the digital signals into the digital signals, writes the digital signals into the digital signals, and reads the digital signals from the memory. , R-Y, Y-R,
The reading speed of each signal of B-Y is modulated by a feedback signal (signal proportional to the high voltage) Srt from a circuit for detecting a high-voltage fluctuation, and read, and the analog luminance signal Y and the color difference signals R-Y, B- Amplitude correction circuit 100 for converting to Y and outputting
And the luminance signal Y and the color difference signals RY and BY output from the amplitude correction circuit 100, and R (red), G
A video output circuit 200 for outputting three primary color signals of (green) and B (blue), the horizontal synchronizing signal HD and the vertical synchronizing signal VD.
Is input to the deflection yoke of the CRT 500,
A deflection circuit 300 for supplying a vertical deflection current, and a deflection circuit 3
A high voltage is supplied to the anode of the CRT 500 and connected to the horizontal output stage of the CRT 500 while detecting the high voltage and using the high voltage detection signal as a feedback signal Srt.
High-voltage rectification / high-voltage detection circuit 400 and CRT 5
00. The deflection circuit 300 includes a horizontal deflection circuit and a vertical deflection circuit.

Next, a horizontal amplitude correction circuit as the amplitude correction circuit 100 will be described. In the horizontal amplitude correction circuit shown in FIG.
Is input, converted into a digital luminance signal 103 by the A / D converter 102, and supplied to a line memory circuit 128 as a memory means. Also, input terminals 104 and 10
5, analog color difference signals RY and BY are input, multiplexed and supplied to an A / D converter 108, where they are converted into digital color signals 109 and supplied to a line memory circuit 128. You.

A digital signal is written to the line memory circuit 128 in accordance with a write timing signal 126 from a timing circuit 125.
This is performed using the write clock 112 from.

A horizontal synchronizing signal HD is input to an input terminal 110 and is supplied to a clock generation circuit 111. The clock generation circuit 111 includes a timing signal 112 for giving a write / read timing of a horizontal cycle, and a clock signal 910 of a frequency 910 times the horizontal scanning frequency fH.
fH clock (113) and the horizontal scanning frequency fH of 27
A 2730.times.fH clock (114) of 30 times the frequency is generated.

The timing signal 112 is supplied to a timing generation circuit 125. 910 · fH clock (1
13) is supplied to the line memory circuit 128 as a write clock, while being supplied to the timing generation circuit 125. The timing generation circuit 125 uses the horizontal period timing signal 112 and the 910 · fH clock (113) to generate the 910 · fH clock (113).
And generates a write timing signal 126 having a horizontal cycle synchronized with the line timing.

The 2730 · fH clock (114) is supplied to the digitally controlled oscillator 115. The digitally controlled oscillator 115 outputs the 2730 · fH clock (11
4) digitally generates a read clock based on 4), and has a function of modulating the read clock frequency, that is, the read speed, with a secondary high voltage detection signal (ie, feedback signal) 117 of the flyback transformer FBT. Have.

As the feedback signal 117, a signal obtained by dividing the high voltage EH for the CRT anode obtained at the high voltage terminal of the secondary winding of the flyback transformer FBT connected to the horizontal output stage by the detection resistors R1 and R2 is used. Either used, or the voltage across the ABL detection capacitor C1 between the return terminal (ie, ABL terminal) of the secondary winding of the flyback transformer FBT and the reference potential point (this voltage is proportional to the anode current) Is used.

The feedback signal 117 is converted into a digital signal by the A / D converter 118 and is output to the digitally controlled oscillator 11.
5 is supplied as a control signal. The digitization of the feedback signal 117 synchronizes the feedback signal 117 from the flyback transformer FBT with another digital circuit (that is, synchronizes the feedback signal 117 with the digitized video signal and converts the feedback signal 117 into a digital signal). Time delay).

The digital clock signal 120 modulated by the feedback signal 117 output from the digitally controlled oscillator 115 is converted into an analog clock signal 122 by the D / A converter 121, and the waveform is shaped by the waveform shaping circuit 123. Thereafter, the signal is supplied to the line memory circuit 128 as a read clock 124 while the timing generation circuit 1
25. The timing generation circuit 125 includes a timing signal 112 having a horizontal cycle and a read clock 12.
4, a read timing signal 127 having a horizontal cycle synchronized with the read clock 124 is generated and supplied to the line memory circuit 128.

The circuit portions indicated by reference numerals 110 to 127 constitute write / read control means.

The line memory circuit 128 stores the stored digital luminance signal Y and digital color signal R-
Y and BY are read out as signals 129 and 130 with their read speeds modulated in accordance with high-voltage fluctuations, the digital luminance signal 129 is sent to the D / A converter 131, and the digital chrominance signal 130 is sent to the D / A The signals are supplied to converters 133 and 134.

The D / A converter 131 converts the digital luminance signal into an analog luminance signal Y,
Output from The D / A converter 133 separates the RY digital color difference signal from the multiplexed digital color signal, converts it into an analog color difference signal RY, and outputs it from the output terminal 135. The D / A converter 134 separates a BY digital color difference signal from the multiplexed digital color signal, converts it into an analog color difference signal BY, and outputs it from an output terminal 136.

In the above configuration, conventionally, the relationship between the high voltage supplied to the anode of the CRT and the horizontal amplitude of the image displayed on the CRT is such that the high voltage decreases in response to a high-luminance signal having a relatively large area. Then, in accordance with the characteristic of FIG. 5A, the horizontal amplitude of the image in the high-luminance portion increases according to the drop of the high voltage. However, the circuit of FIG. 1 corrects the characteristic of FIG. When the high voltage of the CRT anode drops, control is performed to increase the reading speed of the line memory circuit 128 as shown in FIG. As a result, when a high-luminance portion having a relatively large area appears and the high voltage drops, the reading speed of the image from the line memory circuit 128 increases, so that it is possible to suppress the horizontal amplitude of the displayed image from widening. The horizontal screen amplitude can be corrected to be constant.

FIG. 3 is a block diagram showing a vertical amplitude correction circuit according to another embodiment of the present invention.

In the vertical amplitude correction circuit shown in FIG. 3, an analog luminance signal Y is input to an input terminal 101 and A / A
The digital luminance signal 103 is converted by the D converter 102 into a digital luminance signal 103, and a field memory circuit 128A as memory means
Supplied to Analog color difference signals RY and BY are input to the input terminals 104 and 105, respectively, multiplexed and supplied to an A / D converter 108, where they are converted into digital color signals 109, It is supplied to the memory circuit 128A.

The writing of the digital signal to the field memory circuit 128A is performed using the write clock 112 from the clock generation circuit 111A in accordance with the write timing signal 126 from the timing circuit 125A.

The vertical synchronizing signal VD is input to the input terminal 110A, and is supplied to the clock generation circuit 111A. The clock generation circuit 111A includes a timing signal 112A for giving a write / read timing of a vertical cycle, an n1 · fV clock (113) having a frequency n1 times the vertical scanning frequency fV, and a vertical scanning frequency f
An n2 .multidot.fV clock (114) having a frequency of n2 (n2> n1) times V is generated.

The timing signal 112A is supplied to a timing generation circuit 125A. The n1 · fV clock (113) is supplied to the field memory circuit 128A as a write clock, while being supplied to the timing generation circuit 125A. Timing generation circuit 12
5A generates a vertical-period write timing signal 126A synchronized with the n1 · fV clock (113) using the vertical-period timing signal 112A and the n1 · fV clock (113).
28A.

The n 2 · fV clock (114) is supplied to the digitally controlled oscillator 115. The digitally controlled oscillator 115 digitally generates a read clock based on the n2 · fV clock (114), and determines the read clock frequency, that is, the read speed, by detecting the secondary high voltage detection signal of the flyback transformer FBT. (That is, a feedback signal).

The feedback signal 117 is obtained by dividing the high voltage EH for the CRT anode obtained at the high voltage side terminal of the secondary winding of the flyback transformer FBT connected to the horizontal output stage by the detection resistors R1 and R2. Either used, or the voltage across the ABL detection capacitor C1 between the return terminal (ie, ABL terminal) of the secondary winding of the flyback transformer FBT and the reference potential point (this voltage is proportional to the anode current) Is used.

The feedback signal 117 is converted into a digital signal by the A / D converter 118 and is converted into a digital signal by the digital control oscillator 11.
5 is supplied as a control signal. The digitization of the feedback signal 117 synchronizes the feedback signal 117 from the flyback transformer FBT with another digital circuit (that is, synchronizes the feedback signal 117 with the digitized video signal and converts the feedback signal 117 into a digital signal). Time delay).

The digital clock signal 120 modulated by the feedback signal 117 output from the digitally controlled oscillator 115 is converted into an analog clock signal 122 by the D / A converter 121 and shaped by the waveform shaping circuit 123. Thereafter, the clock signal is supplied to the field memory circuit 128A as the read clock 124, and is also supplied to the timing generation circuit 125A. Timing generation circuit 12
5A generates a vertical cycle read timing signal 127A synchronized with the read clock 124 using the vertical cycle timing signal 112A and the read clock 124, and supplies the generated read timing signal 127A to the field memory circuit 128A.

The circuit portions denoted by reference numerals 110 to 127A are:
Write / read control means is constituted.

In the field memory circuit 128A, the stored digital luminance signal Y and digital chrominance signals RY and BY are read out as signals 129 and 130 with their read speeds modulated in accordance with high-voltage fluctuations. And
The digital luminance signal 129 is supplied to a D / A converter 131, and the digital chrominance signal 130 is supplied to D / A converters 133 and 134.

The D / A converter 131 converts the digital luminance signal into an analog luminance signal Y,
Output from The D / A converter 133 separates the RY digital color difference signal from the multiplexed digital color signal, converts it into an analog color difference signal RY, and outputs it from the output terminal 135. The D / A converter 134 separates a BY digital color difference signal from the multiplexed digital color signal, converts it into an analog color difference signal BY, and outputs it from an output terminal 136.

In the above configuration, conventionally, the high voltage supplied to the anode of the CRT fluctuates with the luminance change of the picture displayed on the CRT, and the vertical amplitude of the image displayed on the CRT fluctuates. However, in the circuit of the present invention shown in FIG. 3, even when the vertical amplitude changes so as to increase, the read speed of the read clock 124 of the field memory circuit 128A can be increased. As a result, when a high-luminance portion having a relatively large area appears and the high voltage drops, the reading speed of the image from the field memory circuit 128A increases, so that it is possible to suppress the vertical amplitude of the displayed image from increasing. It can be corrected so that the vertical screen amplitude is constant.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an amplitude correction circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the amplitude correction circuit of FIG. 1;
FIG. 4 is a characteristic diagram illustrating a relationship between a reading speed and a high-voltage change.

FIG. 3 is a block diagram showing an amplitude correction circuit according to another embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a display device using the amplitude correction circuit of FIGS. 1 and 3;

FIG. 5 is a diagram showing a relationship between horizontal and vertical amplitudes with respect to a change in high voltage in a conventional display device, and a screen distortion caused by the relationship.

FIG. 6 is a circuit diagram showing a conventional amplitude correction circuit.

[Explanation of symbols]

 101: input terminal of analog luminance signal 102, 108: A / D converter 104, 105: input terminal of analog color difference signal 110: input terminal of horizontal synchronization signal 110A: vertical synchronization signal input terminal 111, 111A: clock generation circuit 115 ... Digital control oscillator 121 ... D / A converters 125 and 125A ... Timing generation circuit 128 ... Line memory circuit 128A ... Field memory circuit 131,133,134 ... D / A converter 132 ... Output terminal of analog luminance signal 135,136 ... Analog color difference signal output terminal

Claims (5)

[Claims] 1. A high voltage detecting means for detecting a fluctuation of a DC high voltage supplied to an anode of a cathode ray tube, an A / D converting means for inputting an analog luminance signal and a color difference signal and converting them into digital signals, respectively. A memory unit for storing the digital signal obtained by the D conversion; and a unit for controlling writing and reading to and from the memory unit. When reading the data written to the memory unit, the reading speed is controlled by the high voltage detecting unit. Writing and controlling to modulate according to the detected high voltage fluctuation
An amplitude correction circuit comprising: read control means; and D / A conversion means for converting a signal read from the memory means into an analog luminance signal and a color difference signal again. 2. The memory means comprises a line memory circuit, and the write / read control means writes a first timing signal of a horizontal cycle and a predetermined multiple of a horizontal frequency based on a horizontal synchronization signal. First for
And a clock generation circuit for generating a second clock having a predetermined multiple of a horizontal frequency different from the above, and oscillating a clock based on the second clock. A digitally-controlled oscillator that is modulated in accordance with a high-voltage fluctuation detected by the detection unit; a D / A converter that converts an output of the digitally-controlled oscillator into an analog signal and outputs the signal as a read clock to the memory unit; A timing generation circuit that generates a write timing signal based on the first timing signal and the first clock, and generates a read timing signal based on the first timing signal and a read clock from the D / A converter 2. The amplitude correction circuit according to claim 1, comprising: 3. The memory means comprises a field memory circuit, and the write / read control means writes a first timing signal of a vertical cycle and a predetermined multiple of a vertical frequency based on a vertical synchronization signal. First for
And a clock generation circuit for generating a second clock having a frequency that is a predetermined multiple of a vertical frequency different from the above, and oscillating a clock based on the second clock, wherein the oscillation frequency is the high voltage. A digitally-controlled oscillator that is modulated in accordance with a high-voltage fluctuation detected by the detection unit; a D / A converter that converts an output of the digitally-controlled oscillator into an analog signal and outputs the signal as a read clock to the memory unit; A timing generation circuit that generates a write timing signal based on the first timing signal and the first clock, and generates a read timing signal based on the first timing signal and a read clock from the D / A converter 2. The amplitude correction circuit according to claim 1, comprising: 4. A rectifier circuit for rectifying a secondary high voltage pulse of a flyback transformer connected to a horizontal output stage of a horizontal deflection circuit to obtain a DC high voltage and supplying the DC high voltage to a cathode ray tube anode. 2. The amplitude correction circuit according to claim 1, further comprising a resistance circuit that divides and detects a DC high voltage obtained by said rectification circuit. 5. A rectifier circuit comprising: a rectifier circuit for rectifying a secondary high voltage pulse of a flyback transformer connected to a horizontal output stage of a horizontal deflection circuit to obtain a DC high voltage and supplying the DC high voltage to a cathode ray tube anode; A capacitor connected between a return terminal of a secondary winding of the flyback transformer and a reference potential point and detecting a voltage proportional to a cathode ray tube anode current flowing through the secondary winding. The amplitude correction circuit according to claim 1, wherein: