JP2002299634A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress variations in a threshold caused by a thickness of a silicon layer film of a complete depletion type SOI MOSFET. SOLUTION: A method for manufacturing a semiconductor device comprises the steps of implanting silicon ion in an embedded oxide film 2 through a silicon layer 3 of an SOI structure having the film 2 and the layer 3 sequentially provided on a silicon substrate 1, forming a fixed oxide film charge layer 4 at a silicon ion arrival distance, and providing a gate electrode on the layer 3 via a gate oxide film 5. Since the charge layer 4 has a function of reducing the threshold of the SOI MOSFET, the more the thickness of the silicon layer film is increased, the SOI MOSFET in which an effect of the variations of the thickness of the layer 3 to the threshold voltage is small, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art SOI MOSFET SOI (silicon silicon)
On-insulator) structure on a silicon substrate
The buried oxide film layer and the single crystal silicon layer (Si layer) are formed sequentially.
It has a completed configuration. The thickness of this Si layer is extremely thin
Variations due to manufacturing process variations. Completed in FIG.
Si layer thickness T in fully depleted SOI MOSFET
_siAnd threshold voltage V_thFIG. Completely empty
Threshold voltage V of scarce SOI MOSFET_thIs the Si layer
Film thickness T_siDependent, as shown by the dotted line in FIG.
The threshold characteristic is the thickness T of the Si layer._siAffected by variation
Cheap. For example, due to manufacturing process variations
The thickness T of the Si layer of each chip on the wafer _siMinimum
T_si-1, Maximum value T_si-2Is assumed to have occurred. Do
And the respective film thickness T_si-1, T_si-2Threshold voltage at
Pressure V_th′ (T_si-1), V_th′ (T_si-2), Δ
V_th′, The variation of the threshold voltage
I will.

[0003]

## EQU1 ## δV_th'= V_th′ (T_si-1) -V_th′ (T_si-2) Variation of this threshold voltage δV_th′ For semiconductor devices
It is a factor that deteriorates the yield and is regarded as a problem. M
With the trend of miniaturization of the 0SFET, the Si layer thickness T _sis design
The values are only getting thinner. This has two factors
This will further increase the variation of the threshold voltage. (1) Sensitivity of threshold voltage to Si layer thickness (Sens
3) of the curve shown by the dotted line b in FIG.
Incline increases. (2) Relative variation in film thickness relative to Si layer thickness
Control becomes difficult.

Therefore, the variation δV _th 'of the threshold value
Is an issue to be solved promptly in the production of SOI MOSFETs.

An example of a conventional SOI MOSFET manufacturing method (Japanese Patent Laid-Open No. 8-293610) which can suppress the above-mentioned threshold variation will be described with reference to FIG.
A field oxide film 11 for element isolation is formed in an SOI structure in which a buried oxide film layer 2 and a Si layer 3 are sequentially formed on a silicon substrate 1, and oxidation is performed on the Si layer 3 in the same manner as in a normal MOSFET process. The film 12 is grown. Next, boron difluoride (BF ₂ ⁺ ) for adjusting the threshold value is ion-implanted into the Si layer 3, and then phosphorus ( P ⁺ ) is ion-implanted into the Si layer 3. At this time, phosphorus (P ⁺ ) is implanted to a depth deeper than the thickness of the Si layer 3.

Thereafter, an N type polysilicon gate electrode 13 is formed on the gate oxide film 12 ',
N ⁺ to be the source and drain of channel type MOSFET
The diffusion layer 14 is formed, and a portion facing the gate electrode 13 via the gate oxide film 12 'is defined as a body portion 15. In this case, phosphorus is used as a dopant.

[0007]

In the conventional threshold variation suppressing method, a film thickness region in which the net impurity amount after compensation by ion implantation of phosphorus and boron hardly changes with the film thickness of the Si layer 3 is generated. Although the threshold value does not change in this region, an ion implantation step of boron or phosphorus is required, and impurities increase.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor device and a method of manufacturing a semiconductor device in which variation in threshold voltage due to the thickness of a Si layer in a fully depleted SOIMOSFET is suppressed by fixed charges. It is intended to provide a method.

[0009]

SUMMARY OF THE INVENTION The present invention provides a fully depleted S
By providing a fixed oxide film charge layer in a buried oxide film such as an OI MOSFET, variations in the threshold value due to variations in the thickness of the Si layer are suppressed.

A fully depleted SOI MOS according to the present invention
The Si layer thickness-threshold voltage characteristic of the FET is schematically shown as a solid line a in FIG. The slope of the Si layer thickness-threshold voltage characteristic curve is expressed by the conventional Si layer thickness-dotted line b in FIG.
It is looser than the threshold voltage characteristic curve. That is,
(1) variations .DELTA.V _th of the threshold voltage V _th caused by variations of the resulting Si-layer thickness T _si based on the equation, the conventional expression (2) of the variation .DELTA.V _th of the threshold voltage V _th ''Is smaller and improved (Equation (3)).

[0011]

## EQU2 ## δV _th = V _th (T _si−1 ) −V _th (T _si−2 ) (1) δV _th ′ = V _th ′ (T _si−1 ) −V _th ′ (T _si−2 ) (2) δV _th <δV _th '(3) The principle of the present invention for improving the threshold voltage variation will be described below.

The present invention is based on the conventional Si shown in FIG.
Thickness - with respect to a threshold voltage characteristic, to have a function as a threshold higher the Si layer thickness T _si becomes thicker drops as indicated by the solid line a in FIG. The variation of the threshold value is defined as ΔV _th (T _si ) as a function of the Si layer thickness T _si . With this function, the slope of the Si layer thickness-threshold voltage curve shown by the dotted line b in FIG. 3 can be made gentle as shown by the solid line a in FIG.

Next, a semiconductor device having the above functions according to the present invention will be described with reference to FIG. This semiconductor device has an SOI structure composed of a silicon substrate 1, a buried oxide film layer 2 provided on the silicon substrate 1, an Si layer 3 provided on the buried oxide film layer 2, and It has a gate insulating film 5 and a gate electrode 6 provided. Although simplified here, there are also other general semiconductor device structures, such as a source and a drain.

In the semiconductor device according to the present invention, the fixed oxide film charge layer 4 is provided at a fixed distance X in the buried oxide film layer 2 from the interface between the Si layer 3 having the SOI structure and the buried oxide film layer 2. It is characterized by the following. Also, the buried oxide film layer 2
The position X of the fixed oxide film charge layer 4 is the thickness T of the Si layer 3.
It is characterized in that the _si is provided deeper (X1) as it becomes thinner and shallower (X2) as it becomes thicker. The influence of the fixed oxide film charge layer 4 on the threshold voltage change ΔV _th (T _si ) is stronger as the position X of the fixed oxide film charge layer is shallower and weaker as the position X of the fixed oxide film charge layer is deeper. Therefore, the threshold voltage change ΔV _th (T _si ) is smaller as the thickness T _si of the Si layer 3 is smaller, and ΔV _th (T _si ) is smaller as the thickness T _si is larger.
_th (T _si ) increases, and the slope of the Si layer thickness-threshold voltage curve in FIG.

[0015]

(Equation 3)

[0016] The above and fixed oxide charge layer position X, the substrate bias producing the same field as the field to produce its fixed oxide charge Q _f, so-called equivalent substrate bias variation △ V _es
Is expressed by equation (5). The relationship dV _th / dV _es between the substrate bias and the threshold voltage is known as a so-called back bias effect, and can be easily measured. Therefore, by using this relationship and the equivalent substrate bias variation ΔV _es , the relationship between the fixed oxide film charge layer position X and the threshold voltage variation ΔV _th (T _si ) is as shown in equation (6). Become. As the fixed oxide film charge layer position X becomes shallower, that is, S
As the thickness of the i-layer 3 increases, the threshold voltage change ΔV
_th (T _si ) is large.

The fixed oxide film charge layer 4 is formed by implanting excess Si by, for example, Si ion implantation after forming the SOI structure in the FET manufacturing process. In this case, the Si layer 3
The thickness T _si, and is fixed oxide charge layer position X buried oxide thickness Tbox, Si ions reach R _p and (4) the relationship of expression. By substituting equation (4) into equation (6), equation (7) is obtained, and the film thickness T _si of the Si layer 3 and the threshold voltage change ΔV _th
The relationship with (T _si ) becomes clearer.

[0018]

An embodiment of the present invention will be described with reference to FIG. 2 (a), 2 (b) and 2 (c) show an example of a method of manufacturing a fully depleted SOI MOSFET over time. In addition, on the left and right sides of FIG. 2, in consideration of the manufacturing variation of the Si layer thickness when fabricating the SOI structure,
It shows a method for manufacturing a thin and a thick Si layer.

FIG. 2A shows an SO having a Si layer 3a having a small thickness T _{si-1 and} a Si layer 3b having a large thickness T _si-2.
1 shows an I structure. This SOI structure has a buried oxide film layer 2 and a Si layer 3 (3a, 3b)
Are sequentially formed. Next, as shown in FIG. 2B, Si ions are implanted into the buried oxide film layer 2 through the Si layer 3 in order to form the fixed oxide film charge layer 4. This S
i ion implantation is designed to Si ions are implanted from the surface of the Si layer 3 to the position of the Si ions reach R _p as described in the section of means for solving the above problems. Then, as shown in FIG. 2C, a gate insulating film 5 and a gate electrode 6 are formed on the SOI structure provided with the fixed oxide film charge layer 4.
To form an FET structure.

The Si layer 3 (3a, 3b) of this FET structure
Relationship between the position X of the thickness of the fixed oxide charge layer 4, are the relationship expressed by Equation (4) using the Si ion arrival far R _p. Therefore, as shown in FIG.
The position X of the fixed oxide film charge layer 4 viewed from the interface between the silicon layer 1 and the buried oxide film layer 2 is deep (X1) for the FET having the thin Si layer 3a and shallow (X2) for the SOI structure having the thick Si layer 3b. ) Produced.

According to this manufacturing method, the Si ion arrival distance R from the surface of the i-layers 3a and 3b in the process of FIG.
By Si ion implantation so that _p, since each position X of the fixed oxide charge layer 4 can contribute a desired X1, X2, of no threshold voltage V _th regard to the thickness of the Si layer 3 It is possible to manufacture almost uniform FETs.

The above is a fully depleted SOI MOSFET
However, the present invention is not limited to the fully depleted type, but can be applied to the manufacture of another type of SOI MOSFET in which the threshold voltage of the FET changes depending on the thickness of the Si layer 3. Needless to say.

[0023]

As described in detail above, the semiconductor device of the present invention has a SOI structure such as a fully depleted SOI in which the threshold voltage changes due to the variation in the thickness of the silicon layer generated when the SOI structure is formed.
Since the fixed oxide film charge layer is provided in the buried oxide film layer of the IMOSFET, the threshold value decreases as the silicon layer film thickness of the fixed oxide film charge layer becomes thicker. An SOI MOSFET having little effect on the value voltage can be obtained.

According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a SOI MOSFET of a complete depletion type or the like, silicon ions are implanted into a buried oxide film through a silicon layer having an SOI structure and fixed at a silicon ion arrival distance. Since the oxide film charge layer is formed, the function of lowering the threshold value as the silicon layer film thickness of the fixed oxide film charge layer becomes thicker has a small influence on the threshold voltage due to the variation of the silicon layer film thickness. An SOI MOSFET is obtained. Therefore, the yield resulting from the variation in the thickness of the silicon layer during the manufacture of the SOI MOSFET can be improved, and the manufacturing cost of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 shows a fully depleted SO for explaining the principle of the present invention.
FIG. 3 is a schematic cross-sectional view of an IMOSFET.

FIG. 2 shows a fully depleted SOI according to an embodiment of the present invention.
FIG. 5A shows a manufacturing process of a MOSFET, wherein FIG.
FIG. 4 is a cross-sectional view of the OI structure, FIG. 4B is an explanatory view of forming a fixed oxide charge layer, and FIG.

FIG. 3 is a graph showing a relationship between a silicon layer thickness and a threshold voltage of a fully depleted SOI MOSFET.

FIG. 4 shows a conventional fully-depleted SOI MOSFE.
Sectional drawing which shows the manufacturing process of T.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 buried oxide film layer 3 silicon layer 4 fixed oxide film charge layer 5 gate oxide film 6 gate electrode T _si silicon film thickness T _box buried oxide film thickness C _box buried oxide film Capacitance R _p : reach distance of Si ions X ... fixed oxide film charge position Q _f ... fixed oxide film charge ΔV _es ... equivalent substrate bias

Continued on front page F term (reference) 5F058 BA20 BD03 BD04 BH15 BJ04 BJ10 5F110 AA08 CC01 CC02 DD05 DD13 DD24 DD25 DD30 GG02 GG12

Claims (5)

[Claims] 1. An SOI having an SOI structure in which a buried oxide film layer and a silicon layer are sequentially formed on a silicon substrate.
In a MOSFET, a fixed oxide film charge layer is provided in the buried oxide film. 2. The semiconductor device according to claim 1, wherein said SOI MOSFET is a fully depleted SOI MOSFET. 3. A position of the fixed oxide film charge layer from a boundary between the silicon layer and the buried oxide film layer is a shallow position in an element having a large thickness of the silicon layer, and a position is small in an element having a small thickness of the silicon layer. 3. The semiconductor device according to claim 1, wherein は is a deep position. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a buried oxide film layer and a silicon layer are sequentially formed on a silicon substrate to form an SOI structure. And implanting silicon ions into the buried oxide film through the through hole to form the fixed oxide film charge layer. 5. The semiconductor device according to claim 4, wherein the silicon ions are implanted so as to have a predetermined silicon ion arrival distance from the upper surface of the silicon layer regardless of the thickness of the silicon layer. Production method.