GB2464741A

GB2464741A - Field effect transistor

Info

Publication number: GB2464741A
Application number: GB0819684A
Authority: GB
Inventors: Aimin Song; Yanming Sun; Shiwei Lin
Original assignee: Nano ePrint Ltd
Current assignee: Nano ePrint Ltd
Priority date: 2008-10-27
Filing date: 2008-10-27
Publication date: 2010-04-28
Anticipated expiration: 2028-10-27
Also published as: WO2010049728A1; GB0819684D0; GB2464741B

Abstract

The FET comprises: a substantially fixed distribution of charge 5 arranged to produce an electric field; and insulative material 6 separating the distribution of charge from the semiconductor channel 3, the arrangement being such that the semiconductor material is exposed to the electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate 4 and by the charge distribution 5. The distribution of charge may be provided by a monolayer in which each molecule has a fixed polarisation, and a method of manufacturing the FET may include controlling a thickness of an insulating layer separating the charge distribution from the semiconductive material to tune the threshold voltage of inorganic and polythiophene organic FETs. The charged layer may be formed between the channel and the gate or on the opposite side of the channel to the gate (see figure 2).

Description

EEls, Semiconductor Devices and their Methods of Manufacture

Field of the Invention

The present invention relates to field effect transistors (FETs), to other semiconductor devices incorporating semiconducting material which provides an electrical conduction path, and to methods of manufacturing such devices and FETs.

Background to the Invention

FETs are very well known electronic devices. A variety of configurations are known, but in general a FET comprises a source, a drain, active semiconductor material arranged to provide a conduction path between the source and drain, and a gate. The conductance of the conduction path is controlled by the voltage applied to the gate. Enhancement mode devices are known, in which a voltage needs to be applied to the gate in order to open a conducting channel through the semiconducting material; in the absence of such a gate voltage the channel is normally closed (i.e. the conductance of the conduction path through the semiconducting material is normally low). Depletion mode devices are also known, in which the semiconducting material normally (that is, in the absence of an applied gate voltage) provides a conducting channel (i.e. the conductance of the conducting path is normally high) and application of a suitable gate voltage is required in *S.. . order to close that channel. In other words, a suitable voltage must be applied in order to switch the conduction path conductance from a high to a low state.

* 25 A parameter associated with FETs is therefore the threshold voltage. Generally speaking, this is the gate voltage above which the FET is in one conduction state (either on or off, with the conduction path conductance being high or low respectively) and below which the FET is in the other state. Clearly, the threshold voltage for a particular device depends on the criterion used to determine whether the device is on or off. This criterion will typically correspond to a predetermined threshold.

FETs incorporating inorganic semiconductor material are well known, and include devices based on silicon and other substrates, In such devices, the source, drain and body of active semiconductor material are produced by suitable doping. The degree of doping can be varied to influence the threshold voltage of the device, but it is an aim of certain embodiments of the present invention to provide an alternative method for influencing threshold voltage which can be used as an alternative to, or in addition to the doping technique.

FETs incorporating ferroelectric material, arranged between the gate and active semiconductor material, are also known. Such devices typically show hysteretic behaviour, in terms of channel conductance as a function of applied gate voltage, as the gate voltage affects the polarisation of the ferroelectric material. In other words, the charge distribution in the body of ferroelectric material changes with applied gate voltage.

Organic FETs, that is FETs incorporating organic sen,iconductive material to provide a controllable conduction path between source and drain, are also known.

Organic field-effect transistors (OFETs) have attracted a great deal of attention due to their potential applications in flexible, low cost and large-area electronic devices.

Although much progress has been made in OFETs recently, especially in improvements of the mobility and on/off ratio, which are approximately comparable to those of amorphous silicon (a-Si:H) devices, it remains a difficulty to control the threshold voltage (VT) of a device. In addition to the mobility, V1 is another important parameter in OFETs, *.** 20 which is crucial to the design and manufacture of complicated organic integrated circuits and also determines the power consumption of devices. Normally, VT could be affected Se..

by many factors such as the time of gate bias stress, the work function of gate electrode, the exposure of device to light, the thickness of organic active layer and the surface treatment of gate insulators, amongst others. Up to now, much effort has been devoted to strictly control V1, however, the results are limited.

Doping techniques suitable for controlling the threshold voltage in organic FETs are not yet available.

One document disclosing an attempt to control threshold voltage in organic FETs is Threshold Voltage Shift in Organic Field Effect Transistors by Dipole Mono Layers on the Gate Insulator", K.P. Pernstitch et al, Journal of Applied Physics, Volume 96, No. 11, 1 December 2004, PP6431-6438 the document discloses the use of self assembled mono layers (SAMs), having built-in dipole fields, in direct contact with organic semiconductor films of organic FETs to affect the threshold voltages of the devices. The disclosed technique offers some control of threshold voltage, but a disadvantage is that in order to achieve different threshold voltages, a variety of different organosilanes (forming the SAMs) and different surface treatments (ie of the surface on which the SAM is formed) are required. Furthermore, it is not trivial to achieve good adhesion of the semiconducting layer to the SAM layer, and the disclosed technique requires the organic semiconductor material (pentacene) to be formed on the SAM layer by deposition techniques involving the thermal evaporation of pentacene powder.

Another document disclosing the effect of a SAM in direct contact with a layer of organic semiconductor material on the threshold voltage of an organic FET is "Control of Carrier Density by Self-Assembled Mono Layers in Organic Field-Effect Transistors", Kobayashi, Nature Materials, Volume 3, May 2004, PP317-322. Again, different threshold voltages are achieved by using different SAM molecules.

Summary of the Invention

It is an aim of certain embodiments of the invention to solve, mitigate or obviate, at least partly, at least one or some of the problems and/or disadvantages associated with the

prior art.

*.. 20 Certain embodiments of the invention aim to provide a technique of controlling the conductance of a conduction path through semiconductor material in electronic devices.

Certain embodiments aim to provide a technique of controlling, setting or adjusting the threshold voltage of FETs, in certain instances FETs incorporating inorganic semiconductor material and in other instances FETs incorporating organic *. ..

: * semiconducting material. * **

Certain embodiments aim to provide techniques which facilitate the manufacture of FETs, and in particular organic FETs, compared with prior art techniques.

Certain embodiments aim to provide an FET structure and corresponding method of manufacture in which a parameter can be easily controlled in order to determine the threshold voltage of the eventual device.

Certain embodiments aim to provide a structure and corresponding method of manufacture of an organic FET which enables the semiconducting layer to be produced using techniques more compatible with the production of flexible andfor large area electronic devices than the prior art FETs and methods.

According to a first aspect of the present invention there is provided

A field effect transistor comprising:

a source (which may also be described as a source terminal or source electrode); a drain (which similarly may also be described as a drain terminal or drain electrode); semiconductor material arranged to provide an electrical conduction path between the source and the drain; and a gate (which again may also be described as a gate terminal or gate electrode) arranged such that an electrical conductivity (conductance) of the conduction path can be modulated by application of a voltage to the gate, characterised in that the FET further comprises: a substantially fixed distribution of charge arranged to produce an electric field; and insulative material separating said distribution of charge from said semiconductor material, the arrangement being such that the semiconductor material is exposed to said 20 electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate and by the charge distribution.

In other words, the threshold voltage of the FET is a function of both the gate voltage and the electric field associated with (i.e. arising from) the fixed distribution of charge.

The FET can be thought of as having a built-in electric field which is superimposed on * ..

: * the electric field associated with the gate when a gate voltage is applied. * **. *

In contrast to prior art organic FETs, the FET according to this first aspect of the present invention incorporates insulative material between the charge distribution and the active semiconducting material. Advantageously, this separation provides a convenient means of adjusting the electrical/electronic properties (including threshold voltage) of the FET; the separation can be increased to reduce the effect of the charged distribution on the semiconducting material, or decreased to increase the effect. The magnitude of the electric field from the charge distribution to which the semiconducting material is exposed is, of course, a function of the separation between the charged distribution and the semiconducting material. In general, the greater the separation, the smaller the magnitude of the electric field seen by the semiconducting material providing the conduction path.

It will be appreciated that the semiconductive material is exposed to the electric field produced by the fixed charge distribution in the sense that it is exposed to that electric field at least along a portion of the conduction path.

It will also be appreciated that the source may be provided by a single body of material, or may have a more complicated structure. For example, in certain embodiments where the FET comprises inorganic semi conductive material the source may comprise a doped region of semiconductive material, a conductive pad or body attached to that region, and perhaps a further electrical connection arranged to enable a voltage to be applied to the body or pad. Similarly, the drain and gate may comprise just single bodies of material, or may also have structure (ie they may comprise a plurality of distinct regions, bodies, or elements).

In embodiments of this first aspect of the invention, the distribution of charge is substantially fixed, in contrast to prior art ferroelectric FETs in which the polarisation of the ferro electric material is a function of gate voltage. In certain embodiments of the * 20 invention the distribution of charge is maintained and substantially fixed by the suitable arrangement of insulative material, such that there is substantially no mechanism available for supplying charge to the distribution or removing (conveying) charge from it.

S

* S. *** * * In certain embodiments, the semiconductive material is arranged as a layer. In certain embodiments this layer of semiconductive material has a thickness in the range 10 -200nm.

In certain embodiments, the semiconductor material is an inorganic semiconductor material. A wide variety of such materials is known to the skilled person, and may be used in embodiments of the invention.

Examples of inorganic semiconductor materials, which may be incorporated in embodiments of the invention, include group IV semiconductors such as silicon, germanium or the like; Ill-V semiconductor such as gallium arsenide, indium phosphide or the like; metal oxides such as zinc oxide, indium tin oxide, indium zinc oxide or the like.

Alternatively, in certain embodiments the semiconductive (semiconductor) material is an organic semiconductive material. The organic semiconductor material may be a material selected from a list comprising the following examples: Examples of polymer semiconductor include polyalkyithiophenes (e.g. P3HT), polyarylamines (e.g. PTAA), copolymers of fluorene and thiophene, polyparaphenylenevinylene (PPV). Other examples of n-or p-type organic semiconductor materials are described in the following references, the contents of which are incorporated herein by reference: Chern. Rev. 2007, 107, 953-1010; Chem. Rev.

2007, 107, 1066-1096 and US 7029945; Angew. Chem. mt. Ed. 2008, 47, 452 -483 (precursor organic semiconductors); US2004038459A1, Nature Materials VOL 4 Aug 2005 p601, Nature Materials VOL 5 Dec 2006 p950, EP1579518A1 (blends of organic semiconductors with semiconductors).

In certain embodiments, the distribution of charge is provided by a body of further material. The substantially fixed and non-uniform distribution of charge in such embodiments may be provided by the body of further material having a substantially fixed polarisation.

In certain embodiments, this body of further material is arranged as a layer. This layer of further material in certain embodiments has a thickness in the range 0.2nm -lOOnm. * * S....

In certain embodiments, the body of further material is a self assembled mono layer. *

S.....

* 25 The further material may, for example, be a material selected from a list comprising: * -:. Qrganosilane such as 3-Aminopropyl-triethoxysilane Trichloro(1 H, 1 H,2H,2H- * perfluorooctyl)silane [CF3(CF2)5CH2CH2SiCI3J, Trichloro(3, 3, 3-trifluoropropyl)silane 5.

[CF3CH2CH2SiCI3] ,Triethoxy( 1 H, 1 H,2H, 2H)perfluorodecylsilane [(CF3)(CF2)7(CH2)2Si(QC2H5)3], Octadecyltrichiorosilane [CH3(CH2)17SiCl3], Butyltrichlorosilane [CH3(CH2)3SiCI3J, Trichloro(octyl)silane [CH3(CH2)7SiCI3] and Hexamethyldisilazane [CH3)3SiNHSi(CH3)3]. Other organosilane materials, which may be used in embodiments of the invention, are contained within the following articles incorporated by reference herein: Nature Materials 3, 317 -322 (2004); PRAMANA-JOURNAL OF PHYSICS, 67(1), pp 17-32, JUL 2006; J. AppI. Phys. 96, 6431 (2004).; AppI. Phys. Lett. 91, 192112 (2007).

In certain embodiments, the insulative material is arranged as a layer. In such embodiments, the thickness of the layer of insulative material determines the magnitude of the effect of the embedded" charge distribution on the electrical properties! characteristics of the conduction path, and hence the threshold voltage of the FET. The thickness of the layer of insulative material is therefore a parameter which can be controlled during fabrication to achieve a desired threshold voltage. Clearly, this provides advantages over prior art techniques, in which surface treatments and/or materials had to be changed in order to change threshold voltage.

An additional advantage of providing the insulative material in the form of a layer is that it provides a useful intermediary between the body of material supporting the fixed charged distribution and the semiconductive material. For example, the insulative material may be a material selected for its ability to attach/bond well with both the material providing the charge distribution and the semiconductive material. Suitable selection of the insulative material can therefore enable more convenient techniques to be used to form the layer of semiconductive material, especially in the case of organic FETs, such as spin coating techniques.

In certain embodiments, the layer of insulative material has a thickness in the range of 1 20 -lOOnm. * .

In certain embodiments, the insulative material is a material selected from a list comprising: polymethyl methacrylate, polyvinylalcohol, polyvinyl acetate, polyvinyl * * pyrrolidone, polyvinyiphenol, polyvinyl chloride, polystyrene, polyamicie (e.g. Nylon), poly(hydroxyether), polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile I. butadiene styrene, 1-Methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl silsesquioxane (HSQ), polyimide, benzocyclobutene (BCB). Other examples, which may be used in embodiments, are described in the following documents, incorporated by reference herein: Chemistry of Materials (2004), 16(23), 4543-4555; Organic Electronics (2003), 4(1), 27-32; Advanced Functional Materials (2003), 13(3), 199- 204. The insulative material may, in certain embodiments, be an inorganic insulator or dielectric such as Si02, Al203, Hf02 and the like or an inorganic oxide such as described in AppI. Phys. Lett. 88, 123509 (2006) or WO20051 12045 and the like.

In certain embodiments, the FET further comprises a body of additional insulative material arranged to separate the distribution of charge from the gate terminal. This body of additional insulative material may be arranged as a layer, which may have a thickness in the range 50 500nm.

In certain embodiments, the additional insulative material is a material selected from a list comprising: polymethyl methacrylate, polyvinylalcohol, polyvinyl acetate, polyvinyl pyrrolidone, polyvinyiphenol, polyvinyl chloride, polystyrene, polyamide (eg. Nylon), poly(hydroxyether), polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile butadiene styrene, 1-Methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl silsesquioxane (HSQ), polyimide, benzocyclobutene (BCB). Other examples, which may be used in embodiments, are described in the following documents, incorporated by reference herein: Chemistry of Materials (2004), 16(23), 4543-4555; Organic Electronics (2003), 4(1), 27-32; Advanced Functional Materials (2003), 13(3), 199- 204. The insulative material may, in certain embodiments, be an inorganic insulator or dielectric such as Si02, A1203, Hf02, or an inorganic oxide such as described in AppI.

Phys. Lett. 88, 123509 (2006) or W020051 12045 and the like.

In certain embodiments the body of additional insulative material may comprise one or more (i.e. a plurality) of the above-mentioned materials. It may, for example, be a multilayer body or structure. 20 * 0 * * *

Thus, in certain embodiments there are layers of insulative material provided on either side of a layer of material providing the substantially fixed charge distribution. These surrounding insulative layers can thus prevent charge from being supplied to, or removed from, the distribution thereby maintaining it and so maintaining its effect on the threshold voltage of the FET. Thus charge distribution is maintained irrespective of the voltage applied to the gate.

I

In certain embodiments: the gate comprises a semiconducting substrate; the FET further comprises a first insulative layer formed on said substrate; the body of additional insulative material comprises a second insulative layer formed on the first insulative layer; the distribution of charge is provided by a layer of further material formed on the second insulative layer; the insulative material separating said distribution of charge from said semiconductor material comprises a third layer of insulative material formed on the layer of further material; and the semiconductor material is arranged as a layer on said third layer of insulative material.

In such embodiments, each of the source and drain can take the form of a respective conductive (eg metal) contact, pad, or terminal formed on a surface of the layer of semiconductive material (e.g. on top). It will, however, be appreciated that in other embodiments the configuration of the source, drain, and gate may be different.

According to another aspect of the invention, there is provided a method of manufacturing a field effect transistor, the method comprising providing a source; providing a drain; providing semiconductor material arranged to provide an electrical conduction path between the source and the drain; providing a gate arranged such that an electrical conductivity of the conduction path can be modulated by application of a voltage to the gate; providing a substantially fixed distribution of charge arranged to produce an

electric field; and $ ..

providing insulative material separating said distribution of charge from said S.S.

semiconductor material, the arrangement being such that the semiconductor material is exposed to said * electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate and by the charge distribution. ** S. * * *

* * In certain embodiments said providing of a substantially fixed distribution of charge S..

comprises providing a body of a further material containing said distribution of charge.

In certain embodiments said body of further material has a substantially fixed polarisation.

In certain embodiments said body of further material is formed as a layer.

In certain embodiments said layer is a self assembled monolayer.

In certain embodiments the method further comprises providing a body of insulative material having a surface, and providing the body of further material comprises forming a layer of said further material on said surface.

In certain embodiments forming said layer of further material on said surface comprises forming said layer using at least one technique selected from a list comprising: spin-coating or other solution processing deposition; vapour deposition; vacuum deposition.

In certain embodiments the method further comprises processing said surface before forming said layer on said surface.

In certain embodiments said processing is arranged to improve adhesion of the further material to the surface.

In certain embodiments said processing comprises exposing said surface to a plasma (i.e. the processing comprises plasma treating said surface).

Other processing techniques which may be used in embodiments of the invention include: ozone, corona discharge, piranha etch, and surface treatment such as described in EP1124791 or US7034129, the contents of which are incorporated by * reference herein. *.I. * * **.*

In certain embodiments providing said body of insulative material comprises forming a S.. S*, * layer of insulative material on a substrate.

S'S... * S

In certain embodiments the layer of insulative material is formed using at least one * technique selected from a list comprising: vacuum deposition; vapour deposition; sputter S..

coating; sol-gel processing; sputter coating; doctor blade techniques; spin coating; printing, including screen printing and ink-jet printing; aqueous processing for inorganic oxides such as described in AppI. Phys. Lett. 88, 123509 (2006) or W020051 12045, the contents of which are incorporated herein by reference.

In certain embodiments forming said layer of insulative material comprises spin coating the substrate with a solution containing the insulative material.

In certain embodiments the method further comprises selecting the concentration of said solution to determine the thickness of the layer of insulative material formed.

In certain embodiments said providing of insulative material separating said distribution of charge from said semiconductor material comprises forming a separating layer of insulative material on the layer of further material containing the distribution of charge In certain embodiments the forming of the separating layer comprises forming the separating layer of insulative material using at least one technique selected from a list comprising: vacuum deposition; vapour deposition; sputter coating; sol-gel processing; sputter coating; doctor blade techniques; spin coating; printing, including screen printing and ink-jet printing; aqueous processing such as described in AppI. Phys. Lett. 88, 123509 (2006) (incorporated by reference herein).

In certain embodiments the forming of the separating layer comprises spin coating the layer of material containing the distribution of charge with a solution containing insulative material.

In certain embodiments said providing of semiconductor material comprises forming a layer of said semiconductor material on the separating layer. * *0

In certain embodiments said forming of a layer of said semiconductor material comprises ***S forming the layer of semiconductor material using a technique selected from a list comprising: spin coating, sputter-coating, sol-gel processing, atomic-layer deposition S...

* such as described in W02007126582, W02007126585 or W02008091504, embossing S.....

* of nanoparticle precursors such as described in US6878184, US7078276, US7259100, US6936181, US7314513, US6957608 and US7294449; aqueous processing such as * described in AppI. Phys. Lett. 88, 123509 (2006), the contents of all these documents being incorporated herein by reference.

In certain embodiments said forming of a layer of said semiconductor material comprises spin coating the separating layer with a solution containing said semiconducting material.

In certain embodiments said providing of a source and a drain comprises forming said source and said drain on the layer of semiconductor material.

It will be appreciated that the present invention may be embodied in the wide variety of known FET and electronic device types, including: MOSFET; JFET; MESFET; HFET; MODFET; IGBT; FREDFET; DNA FET; light-emitting FET; Thin Film Transistors; 2-D FETs; Self-Switching Devices (SSDs); Side-Gated Transistors (SGTs); and devices as disclosed in International Applications PCT/GBO2/0 1807, PCT/GB2005/002756, and PCT/GB2006/001667, the contents of which are herein incorporated by reference.

According to another aspect of the invention there is provided an electronic device comprising: semiconductor material arranged to provide an electrical conduction path; a substantially fixed distribution of charge arranged to produce an electric field; and insulative material arranged to separate the distribution of charge from the semiconductor material, the arrangement being such that semiconductor material is exposed to said electric field and said electric field affects the electrical conductivity of the conduction path.

Another aspect of the invention provides an electronic circuit comprising at least one FET or electronic device in accordance with any one of the aspects defined above. In certain embodiments, the electronic circuit is flexible. * *. * . * * ** *S*.

Yet another aspect provides apparatus comprising at least one FET, electronic device, or electronic circuit in accordance with any one of the aspects defined above. The **SS.

* : apparatus may, for example, be a screen or display. In certain embodiments, the screen * or display is flexible, particularly (although not exclusively) where the FET and/or semiconductor device or devices comprise "printable" semiconducting materials such as *:. polymer, organic or transparent metal oxide semiconductors, where "printable" refers to the ability to deposit semiconductor material at conditions compatible with flexible substrates (generally 180°C or less). It will be appreciated that the above-mentioned display and screen are merely examples, and further embodiments of the invention may be other apparatus, for example apparatus from the following, non-exhaustive list: rfid tag, sensor, photovoltaic cell, e-paper, simple logic (e.g. NAND, NOR),.

According to another aspect of the invention there is provided a method of manufacturing an electronic device, the method comprising: providing semiconductive material arranged to provide an electrical conduction path: providing a substantially fixed distribution of charge arranged to produce an

electric field; and

providing insulative material arranged to separate the distribution of charge from the semiconductive material, the arrangement being such that the semiconductive material is exposed to the electric field and the electric field affects the electrical conductivity of the conduction path.

Brief Description of the Drawings

Embodiments of the invention will now be described with reference to the accompanying drawings, of which: Fig 1 is a schematic representation of a FET embodying the invention; Fig 2 is a schematic representation of another FET embodying the invention; Fig 3 is a schematic representation of another FET embodying the invention; Fig 4 is a schematic representation of the device structure of an organic FET embodying the invention; * Fig 5 is a schematic representation of part of the FET of Fig 4, at a stage during its manufacture *..

Fig 6 is a schematic representation of part of a FET structure to illustrate the possible arrangement of FOTS molecules on the surface of a layer of PMMA that has not been *** *** * plasma treated; **..S.

* Figs 7 -18 illustrate transfer characteristics of a variety of organic FETs having the general structure shown in Fig 4 but with different thicknesses of the PMMA layers and * with and without the FOTS layer; **.

Fig 19 is a graph illustrating the variation of threshold voltage with thickness of the second PMMA layer (i.e. the separating insulative layer 6) of the FET shown in Fig 4; Figs 20 -23 are schematic representations of further FETs embodying the invention; Fig 24 is a schematic representation of part of an electronic device also embodying the invention; Fig 25 is a plan view of another electronic device embodying the invention, and which may be described as a side-gated transistor (SGT); Fig 26 is a schematic cross-section of the devices of both Fig. 25 and Fig. 28 along lines A-A; Fig 27 is a schematic cross-section of both of the devices of Fig. 25 and Fig. 28 along lines B-B; and Fig 28 is a plan view of another electronic device embodying the invention, and which may be described as a self-switching device (SSD), which functions as a diode.

Detailed Description of Embodiments of the Invention Referring now to Fig 1, a first embodiment of the invention is a FET 100 comprising a source 1, a drain 2, and semiconductive material 3 arranged to provide an electrical conduction path P between the source and drain. The FET also comprises a gate 4 (which is formed from conductive material) to which a voltage or potential may be applied by means of connection 41. The arrangement is such that the electrical conductivity of the conduction Path through the semiconductive material can be modulated by the voltage applied to the gate 4. Thus, the gate potential can be used to control the flow of current between the source and drain, and hence the flow of current in an electrical circuit connected to the source and drain by means of connections 11 and 21. The FET also comprises a substantially fixed distribution of charge 5 (which in this example is supported, embedded, or otherwise provided in a body of material 50). This * * distribution of charge 5 is non-uniform and produces and electric field. The broken line labelled "B' in Fig 1 is a highly schematic representation of the boundary of a region in S...

which the magnitude of this electric field generated by the charge distribution is above a certain threshold. It will be appreciated that the shape of this boundary is not intended 5515.

* to be realistic or associated with any particular achievable charge distribution, it is for *SasS.

* illustrative purposes only. As can be seen in Fig 1, at least a portion of the semiconducting material 3 is exposed to an electric field above the predetermined threshold produced by the charge distribution. The FET also comprises a body of insulative material 6 arranged to separate the distribution of charge 5 from the semiconducting material 3. The overall arrangement is such that the semiconductive material is exposed to the electric field associated with the charge distribution and any electric field resulting from application of a voltage to the gate 4, such that the electrical conductivity of the conduction path through the semiconducting material is determined at least in part by the voltage applied to the gate 4 and by the charge distribution 5. The threshold voltage of the FET is thus a function of gate voltage, the charge distribution 5, and the separation between the charge distribution and the semiconducting material, In other words, the threshold voltage of the device is not determined solely by the semiconductive material and gate arrangement; it is altered by the presence of the charge distribution 5 and is dependent upon the position of that charge distribution.

In the embodiment of Fig 1, the fixed charge distribution 5 is arranged between the gate 4 and semiconducting material. In contrast, Fig 2 shows an FET 100 embodying the invention in which the charge distribution 5 is arranged on an opposite side of the semi-conducting material 3 from the gate 4. In this embodiment, the body of insulative material 6 is attached to a surface of the semiconducting material 3 on one side, and to a body of material 50 supporting the charge distribution 5 on the other side. In this example the charge distribution 5 is that resulting from a polarisation of the material from which the body 50 is formed. Again, the semiconducting material 3 experiences both the "built-in" electric field associated with charge distribution 5 and any electric field associated with application of a potential to the conductive gate 4 (in other words, these two electric fields, from their different respective sources, are superimposed).

Referring now to Fig 3, this shows another FET 100 embodying the invention and based on an inorganic silicone substrate. This substrate has been doped such that it provides a body of P-TYPE semiconducting material. The source 1 comprises a region 13 of the silicone substrate which has been doped so as to be N-TYPE, a conductive pad or body 12 formed on a surface of the region 13, and a source connection 11 enabling the pad *.. 12 to be connected to other devices and/or components. Similarly, the drain comprises * SS.

a second region 23 of the silicone substrate which has also been doped to become N-TYPE, a conductive pad 22 formed on a surface of the region 23, and a connection 21.

****..

* A gate 4 (which may also be described as a gate terminal or gate electrode) is arranged ** **** * * such that a potential may be applied to it by means of connection 41. By application of a suitable potential, a conductive channel (labelled "C" in the Figure) can be opened in the * body of semiconductive material 3, between the source and drain regions 13 to provide conduction through the device. Between the gate 4 and semiconductive material 3, there is a body of material 50 which contains a non-uniform and substantially fixed distribution of charge which produces a fixed, substantially constant electric field in the region of the conductive channel C. The body of material 50 is spaced from the semiconductive material 3 by a body 6 of insulative material, and is separated from the gate 4 by a second body of insulative material 45. The charge distribution in the body 50 and the thickness of the insulative body 6 may be set during manufacture so to achieve a desired threshold voltage for the device. This provides an alternative means of controlling threshold voltage to doping, and so can be used to adjust the threshold voltage in devices where the doping of the substrate has already been set, or indeed where the level of doping is constrained in some manner.

As will be appreciated from the following description, certain embodiments of the invention provide methods of tuning the threshold voltage of polythiophene-based field-effect transistors using multi-gate insulators. The following description demonstrates that, by employing a multilayer gate insulator, V1 in a polymer FET can be controlled with a high degree of precision over a finite range.

Referring now to figure 4, this shows a schematic cross-sectional profile of a P3HT OFET embodying the invention. Fig. 5 illustrates how FOTS dipoles lie normal to the top PMMA insulator after plasma treatment in a method of manufacture embodying the invention. Fig. 6 illustrates how FOTS molecules lie down and mass on the PMMA surface in a method without plasma treatment.

In a series of embodiments based on the structure of fig. 4, heavily n-doped silicon wafers 4 with a 300 nm thick Si02 covering (layer 451) were used as the substrates. The wafers were sequentially cleaned in Decon 75 cleaning agent, followed by ionized water, acetone and methanol in ultrasonic bath. After solvent cleaning, the wafers were placed into UV/Ozone depolymerization cleaner for 10 minutes. Subsequently, a thickness of about 230 nm PMMA (insulative layer 452) was spin coated on top of the Si02 and *S..

annealed at 180 °C for 10 minutes on a hotplate under ambient condition. After cooling down to room temperature, it was processed (i.e. surface processing was performed) by * : plasma treatment for 40 seconds with 30 W microwave power. Then *.**.

* trichloro(1H,1H,2H,2H-perfluorooctyl)silane (FOTS) was evaporated to form the Self-Assembled Monolayer (SAM) layer 50 on the surface of the PMMA 452. After the FOTS * treatment, a second PMMA layer 6 was formed by spin coating the FOTS surface with a PMMA solution having a different concentration (from 0.3% to 2%) and annealing at 180 °C for 10 mins. The thickness of the second layer of PMMA was varied from 0 nm to 100 nm in the different devices in the series. Afterwards, a solution having a concentration of 1% P3HT (organic semiconducting material) was spin coated on the suface of layer 6 and the sample was annealed in N2 atmosphere for 30 mins at 110°C. Finally, source 1 and drain 2 contacts were deposited using thermal evaporation of gold through a shadow mask at a pressure of 2 x 106 mbar. The channel width and length are 2 mm and 0.06 mm, respectively. All the I-V measurements were carried out under ambient conditions.

Plasma treatment is a critical step during the fabrication of certain embodiments; as there are no -OH groups on surface of the original PMMA layer 452, FOTS molecules fail to align vertically on the surface of the PMMA after evaporation, which is illustrated in Fig. 6. However, after a short time plasma treatment, there is an increase in -OH groups on the PMMA surface, which could react with FOTS during the FOTS evaporation to form a dipole and are subsequently arrayed normal to the PMMA layer (or at a certain other angle). As a result, without plasma treatment, the V1-of devices was almost unchanged, irrespective of the second PMMA layer 6 thickness (or concentration), for both FOTS or non-FOTS treatment. However, after plasma treatment, the VT of devices could be controlled by changing the thickness of the second PMMA layer 6.

It is believed that a strong electronegativity of the SAM molecule's functional group influences the charge distribution within the SAM molecule and can form the electric dipole.

Figures 7-18 show the output and transfer characteristics of P3HT devices in the saturated regime at drain-source voltage (VD) of -80 V. From the transfer curves, the VT mainly depends on the concentration of PMMA in the solution used for spin coating * ** (which determines the thickness of the PMMA layer 6 eventually formed) and could be tuned in the range of 65 V to 11 V. The dependence of VT versus of the thickness of top PMMA layer 6 is illustrated in Fig. 19. When the concentration of PMMA in the spin coating solution is increased up to 2%, the V-is approximately constant and is the same magnitude as the VT of the original device (Si02+PMMA). This can be thought of as * having the separating layer so thick that the charge distribution in the SAM 50 no longer affects the properties of the semiconductor material to an appreciable extent. In other words, once the separating layer is sufficiently thick, the electric field of the charge distribution in the semiconducting layer 3 is too weak (its magnitude is too small) to have an observable effect on threshold voltage. It should e noted that the density of -OH groups after plasma treatment depend on the time and the power applied during the treatment. If a long time or a large power were applied, the range of V1 tuned would be extended. For example, if the power was set to 100 W for a time of 40 s, VT could be controlled from 95 V to 10 V. The properties of the various devices manufactured using the above techniques are summarized in Table 1. The electronegativity of the molecule's functional group (-F) influences the charge distribution within the FOTS molecule and can lead to the formation of an electric dipole. Therefore, even no gate bias applied, amounts of mobile holes still exit in the channel, thus it needs a more positive gate bias to switch off the device. However, the precise details of the mechanism behind the operation of this is under investigation.

Table 1 Summarized data of the P3HT field-effect transistor.

Structures Thickness' Capacitance' Mobility On/Off ratio V1 a (cm2/Vs) (V) __________________________________ (nm) (nF/cm2) ____________ _____________ ________ Si02+PMMA I 5.34 0.001 2x10 11 Si02+PMMA+FOTS 0 6.40 0.009 2.5x10 65 Si02+PMMA+FOTS +PMMA 16 6.13 0.007 6x102 40 (0.3%) _________ ___________ _________ ________ ______ Si02+PMMA+FOTS +PMMA 24 6.00 0.002 3x10 30 (0.6%) ______ _______ ______ _______ ____ Si02+PMMA+FOTS+PMMA(1%) 66 5.40 0.002 1.3x10 13 Si02+PMMA+FOTS+PMMA(2%) 100 5.00 0.003 1.5x10 11 [a] Here, the thickness refers to second PMMA layer. The value is calculated by the equation: Ci =k/d [b] Capacitances were measured at the frequency of i05 Hz *... 20 Thus, figures 7 -18 illustrate the transfer characteristics of different organic FETs; some of which embody the present invention. The figures are arranged in pairs. In each pair, the upper figure shows the dependence of drain current on drain voltage for different *..S..

* applied gate voltages. The lower figure of each pair illustrates the dependence of the * * current through the device (from drain to source) on applied gate voltage. Beneath 25 each pair, the structure of the device whose characteristics are shown is indicated. For * example, the device whose characteristics are shown in Figs 7 and 8 has the structure **.

* Si02/PMMA (230nm)IP3HTIAu. This indicates that the substrate is silicone oxide, an insulative layer of PMMA of thickness 230 nanometres is formed on the substrate, a layer of organic semiconductive material P3HT is formed directly on top of the PMMA layer (i.e. in this example there is no polarised F-OTS layer), and gold contacts are formed on top of the semiconductor layer to form the source and drain.

Similarly, Figs 9 and 10 are the characteristics of a device having the structure Si02/PMMA (230nm)/F-OTS/PMMA (0%)/P3HT/Au. This device again has a silicone oxide substrate, a 230 nanometre thick layer of PMMA formed on top of that silicone oxide, an F-OTS SAM formed on top of the PMMA layer, no additional PMMA layer on top of the F-OTS layer (the zero percent concentration indicates that no PMMA is deposited on top of the F-OTS), a layer of semiconductive material P3HT is formed directly on the F-OTS layer, and again gold electrodes are used for the source and drain.

Moving on, Figs 11 and 12 correspond to a device in which an insulative, separating layer of PMMA is formed on the F-OTS layer by spin coating solution containing 0.3% PMMA on the F-OTS layer. It will be appreciated that the percentage of PMMA in the solution used in this spin coating technique determines the thickness of the layer of PMMA eventually formed. Thus, in the figures the percentage appearing after PMMA can be regarded as equivalent to a measure of the thickness of this PMMA layer in the finished device. Returning again to Figs 9 and 10, for that FET the relevant percentage is zero percent, indicating that no PMMA layer is formed on the F-OTS. Returning to Figs 13 and 14, these are the characteristics for an FET having a thicker upper PMMA layer than that corresponding to Figs 11 and 12. Then, Figs 15 and 16 correspond to a FET having an even thicker upper PMMA layer, and Figs 17 and 18 correspond to a FET in which the upper PMMA layer is thicker still.

Referring now to Fig 20, this shows another FET 100 embodying the invention and *:*::* incorporating organic semiconductive material 3. The device has a so-called bottom-gate structure, the gate 4 is formed from a suitable material, and a first layer of insulative material 45 is formed on top of the gate. Then, a body of material 50, incorporating a * fixed charge distribution is formed on top of the layer 45. A second layer of insulative **S...

* material 6 is formed on top of the layer carrying the charge distribution, and source and drain contacts or terminals 1, 2 are formed on an upper surface of this upper insulative * layer 6. Next, a body or layer of semiconductive material 3 is formed over the source, *** drain and upper surface of the layer 6. Application of a suitable voltage to gate 4 by means of connection 41 is able to induce carriers in the organic semiconductive material 3, which can carry a current between the source and drain, that voltage being determined, at least in part, by the charge distribution contained in the body or layer 50 and the thickness of the upper insulative layer 6.

Moving onto Fig 21, this shows an alternative organic FET embodying the invention having a top-gate structure. Here, source arid drain terminals 1, 2 are formed on a substrate 7, and a layer or body of organic semiconducting material 3 is formed over the source, drain and substrate 7. A separating layer of insulative material 6 is formed on the semiconductor layer 3, and the layer containing the charge distribution that produces and electric field seen by the semiconductor 3 is formed on top of layer 6. A further insulative layer 45 is then formed on top of the charge distribution carrying layer 50, separating that charge distribution from the gate 4. Again, the presence of charge distribution results in an electric field which is superimposed on that from the gate electrode, and which therefore influences the electrical and/or electronic properties of the semiconductor material 3. The precise mechanism by which the fixed charge distribution and gate electric fields affect conductance of the semiconductive material between the source and drain may vary depending on the precise device structure, and indeed in some devices may not yet be known (ie they may remain to be established).

However, it will be appreciated that whatever the particular mechanism, it has been established by the present inventors that the arrangement of the charge distribution in proximity to the semiconductive material, separated from that material by a layer of insulative material, does indeed affect the threshold voltage of the device in a wide variety of particular device configurations, including those shown in all of the accompanying figures.

Referring now to Fig 22, this shows an alternative embodiment in which the FET 100 * p. comprises a body of material 50 containing a substantially fixed charge distribution. A ***.

layer of insulative material 6 is formed on that body 50, and source and drain terminals 1, 2 are formed on the surface of the layer 6. Semiconductor material 3 is formed as a ****S.

* layer over the source, drain, and insulative layer 6, and a gate 4 is formed over the ***...

* upper surface of the semiconductor layer 3. Thus, the gate 4 is on the opposite side of the semiconductor layer 3 to the charge distribution in body 50. * ***

Moving on to Fig 23, this shows yet another FET 100 embodying the invention, in which the organic semiconductor material 3 is formed as a layer extending between source and drain terminals 1, 2 formed on top of an insulative layer 6 over a body of material carrying a charge distribution. That in turn is formed on another layer of insulative material 45 on top of a gate structure 4. Once again, application of a suitable voltage to the gate structure 4 enables a current to be carried between the source and drain (in certain embodiments it may induce the charge carriers necessary for this transport), and the threshold voltage of the device is determined by the embedded charge distribution and thickness of the layer 6.

Moving on to Fig 24, this shows an electronic device 200 embodying the invention which comprises semiconductor material 3 arranged to provide a conduction path (indicated highly schematically by a broken line "P" in the figure). The device includes an embedded charge distribution carried in a body of material 50, that charge distribution producing an electric field which is seen by (experienced by) the semiconductor material and which affects the conductivity of that material. A body of insulative material 6 separates the charge distribution from the semiconductor 3, and the thickness of the separating body can be controlled so as to modulate the effect of the charge distribution on the conductants (or equivalently, conductivity).

Referring now to Figs 25, 26 and 27, another electronic device embodying the invention is a side-gated transistor 150. This device comprises an upper layer of active semiconductor material 3 on which (or in which) a pattern of insulative features has been formed. In this example the insulative features are in the form of trenches or apertures 34 which extend from the upper surface of the semiconductor layer 3 completely down to an underlying insulative separation layer 6. These insulative trenches 34 are arranged to define a narrow, elongate channel C connecting a first area al of the semiconductive layer to a second area a2. The insulative features 34 also extend to edges of the upper * surface of the semiconductive device to enclose gate regions 4 on either side of the elongate channel C. In this example, the insulative features extend to the edges of the S..

substrate, although in alternative embodiments this is not necessarily the case. Instead, the insulative channels 34 may extend to the edges of an insulative perimeter which * S....

* separates the device from other portions of a larger substrate. Although not shown in * . *3** * the figures, potentials may be applied to the gate regions 4 by means of suitably arranged electrical contacts. in this way, voltages can be applied to the gate regions 4 * to influence and control, at least partly, the electrical and/or electronic properties (e.g.

S

conductance) of the elongated channel connecting the first and second areas al, a2. In this device, a source contact 1 has been formed in the first area al, and a drain contact 2 has been formed in the second area a2. Even in the absence of an applied gate voltage, the electrical conductance of the elongate channel C is a function of the potential difference applied between source 1 and drain 2. The device 150 is generally of the types shown in international applications PCT/GBO2/01807, PCT/GB2005/002756 and PCT/GB2006/001667, the contents of each of which are hereby incorporated in this specification by reference. The electrical properties of the device illustrated in Fig. 25 will be apparent to the skilled person in light of these three documents. A modification, however, results from the fact that, unlike the particular devices described in these three documents, the device of Figs. 25, 26 and 27 incorporates a layer of material 50 supporting a charge distribution which also affects the electrical conductivity of the elongate channel C (that is, the effect of the charge distribution is in addition to the effect of any potential applied to the gate regions 4). This layer of material supporting the charge distribution 50 is separated from the layer of semiconductive material 3 by an insulative layer 6. The charge distribution layer 50 is itself supported on an underlying substrate 30, which is shown in Figs. 26 and 27 as a single item, although it will be appreciated that in certain embodiments substrate 30 may itself have structure (for example, it may comprise a plurality of layers of one or more materials).

By appropriate arrangement of the conductive channel C dimensions (width and length, and thickness of the semiconducting layer 3) the electrical and/or electronic properties of the conductive channel (which provides a conductive path from the source 1 to the drain 2) may show hysteretic behaviour, making the device 150 suitable for use as a memory unit in a memory device as disclosed in PCT/GB2005/002756. The hysteretic behaviour may be observed in the absence of any applied potentials to the gate regions 4.

However, in certain embodiments suitable potentials may be applied to the gate regions 4 in order to affect the hysteretic behaviour. Thus, suitable voltages may be applied to gate regions 4 as part of a step of writing to the memory unit provided by device 150. * **

Indeed, application of suitable voltages to gate regions 4 can enable the state of the memory unit to be switched using a smaller source-to-drain current and/or using smaller source-to-drain voltages than would be required if the writing were done with no applied 4�SS*S * : gate potentials. * *

Referring now to Fig 28, this is another electronic device embodying the invention, the device 160 being a self-switching device, which functions as a diode, and generally of **.

the type disclosed in the PCT applications mentioned above in the description of Figs. 25 to 27. The cross-sections of the device along lines A-A and B-B are the same as for the device of Fig. 25, and so are shown in Figs. 26 and 27 also. The insulative features 34 are again in the form of trenches, which define an elongate channel C providing a conduction path from a first terminal 1 to a second electrical terminal 2. The conductivity of the channel C is a function of the potential difference applied between terminals I and 2, and exhibits a diode-like behaviour. The general operation of this device will again be apparent to the skilled person from the disclosures in the PCT applications referenced above. However, the characteristics of the device (and in particular the conductivity of the channel C) are further influenced by the presence of the charge distribution in the layer 50, separated from the semi-conductor layer 3 by insulative layer 6.

It will be appreciated that the use of the charge-carrying layer 50 and separating layer 6 in the embodiments shown in Fig. 25 and Fig. 28 enables the electrical and/or electronic properties of those devices to be tuned", that is adjusted, as compared with the characteristics that would be observed were the charge distribution layer 50 not present.

Again, this provides a convenient way, during manufacture, in which to determine electrical properties of the eventual devices.

It will be appreciated that the embodiments shown in Figs. 25 and 28 may incorporate a wide range of semiconductive material. This semiconductive material may be inorganic in certain embodiments, and organic material in other embodiments. Various techniques may be used in the manufacture of these devices, as will be appreciated from the above-referenced PCT applications, For example, the semiconductor layers or films 3 may be formed by printing techniques or spin-coating techniques. The insulative features may be formed by a variety of techniques, for example including printing or embossing.

These are merely examples, however, and a wider variety of alternative techniques will be apparent to the person skilled in the art. * S. * * a * **

It will be appreciated that embodiments of the invention provide a number of advantages. These include the following: *i.... * .

* For a given fixed (e.g. embedded) charge distribution, produced for example by a particular surface treatment in combination with a particular SAM material, one can * adjust the threshold voltage of the eventual FET simply by controlling the thickness of a S..

separating layer produced on top of the SAM layer.

Embodiments are able to solve material compatibility problems. For example, one can easily produce a separating layer (eg PMMA) on a layer incorporating the charge distribution (eg an F-OTS layer) by techniques such as spin coating. Furthermore, one can then easily produce a layer of active semiconducting material (in particular a layer of organic semiconducting material) on top of the separating layer, again by a technique such as spin coating. Adhesion probtems between the semiconductive material and F-OTS layer can thus be avoided.

In embodiments of the invention, one can use a single surface treatment and a single SAM material (molecule) in the manufacturing process yet still achieve a plurality of different threshold voltages, by controlling the thickness of the insulative separating layer * ** ** S * *b S... * S *SS.

S

S..... * S

S

S..... * S *. S. S. *

S S S..

S

Claims

CLAIMS1. A field effect transistor comprising:a source; a drain; semiconductor material arranged to provide an electrical conduction path between the source and the drain; and a gate arranged such that an electrical conductivity of the conduction path can be modulated by application of a voltage to the gate, characterised in that the FET further comprises: a substantially fixed distribution of charge arranged to produce an electric field; and insulative material separating said distribution of charge from said semiconductor material, the arrangement being such that the semiconductor material is exposed to said electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate and by the charge distribution.
2. A FET in accordance with claim 1, wherein said semiconductor material is arranged as a layer.
3. A FET in accordance with claim 2, wherein the layer of semiconductor material has a thickness in the range 10 -200nm. * ** * * * * ***.,. 25
4. A FET in accordance with any preceding claim, wherein said semiconductor material is an organic semiconductor material.

S

*** S.
5 * * 5. A FET in accordance with claim 4, wherein the organic semiconductor material is a material selected from a list comprising: polymer semiconductor; polyalkyithiophenes (e.g. P3HT); polyarylamines (e.g. PTAA); copolymers of fluorene and thiophene; and * polyparaphenylenevinylene (PPV).
6. A FET in accordance with any preceding claim, wherein said distribution of charge is provided by a body of a further material.
7. A FET in accordance with claim 6, wherein said body of further material has a substantially fixed polarisation.
8. A FET in accordance with claim 6 or claim 7, wherein said body of further material is arranged as a layer.
9. A FET in accordance with claim 8, wherein said layer of further material providing the distribution of charge has a thickness in the range 0.2nm -lOOnm
10. A FET in accordance with claim 8 or claim 9, wherein said body of further material is a Self Assembled Monolayer.
11. A FET in accordance with any one of claims 6 to 10, wherein said further material is a material selected from a list comprising: Organosilane such as 3-Aminopropyl-triethoxysilane, Trichloro(1 H, 1 H,2H,2H-perfluorooctyl)silane [CF3(CF2)5CH2CH2SiCI3J, Trichloro(3, 3, 3-trifluoropropyl)silane [CF3CH2CH2SiCI3},Triethoxy(1 H, 1 H,2H,2H)perfluorodecylsilane [(CF3)(CF2)7(CH2)2Si(0C2H5)3], Octadecyltrichiorosilane [CH3(CH2)17SiCI3], Butyltrichiorosilane [CH3(CH2)3SiCI3], Trichloro(octyl)silane [CH3(CH2)7SiCI3] and Hexamethyldisilazane [CH3)3SiNHSi(CH3)3].
12. A FET in accordance with any preceding claim, wherein said insulative material is arranged as a layer. * S. * . S*..: 25
13. A FET in accordance with claim 12, wherein the layer of insulative material has a * S..thickness in the range I -lOOnm.SS..... * S14. A FET in accordance with any preceding claim, wherein the insulative material is a material selected from a list comprising: polymethyl methacrylate, polyvinylalcohol, :. 30 polyvinyl acetate, polyvinyl pyrrolidone, polyvinyiphenol, polyvinyl chloride, polystyrene, * polyamide (e.g. Nylon), poly(hydroxyether), polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile butadiene styrene, 1 -Methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl silsesquioxane (HSQ), polyimide, benzocyclobutene (BCB).15. A EEl in accordance with any preceding claim, further comprising a body of additional insulative material arranged to separate said distribution of charge from the gate terminal.16. A FET in accordance with claim 15, wherein said body of additional insulative material is arranged as a layer.17. A FET FET in accordance with claim 16, wherein the layer of additional insulative material has a thickness in the range 50 -500nm.18. A FET in accordance with any one of claims 15 to 17, wherein the additional insulative material is a material selected from a list comprising: polymethyl methacrylate, polyvinylalcohol polyvinyl acetate, polyvinyl pyrrolidorie, polyvinylphenol, polyvinyl chloride, polystyrene, polyamide (eg. Nylon), poly(hydroxyether), polyurethane, polycarbonate, polysulfone, polyarylate, acrylonitrile butadiene styrene, 1-Methoxy-2-propyl acetate (SU-8), polyhydroxybenzyl silsesquioxane (HSQ), polyimide, benzocyclobutene (BCB).19. A FET in accordance with any one of claims 15 to 18, wherein: the gate comprises a semiconducting substrate; the FET further comprises a first insulative layer formed on said substrate; the body of additional insulative material comprises a second insulative layer formed on the first insulative layer; the distribution of charge is provided by a layer of further material formed on the ***. 25 second insulative layer; the insulative material separating said distribution of charge from said semiconductor material comprises a third layer of insulative material formed on the layer of further material; and * * the semiconductor material is arranged as a layer on said third layer of insulative *. S. : * . 30 material.S20. A method of manufacturing a field effect transistor, the method comprising: providing a source; providing a drain; providing semiconductor material arranged to provide an electrical conduction path between the source and the drain; providing a gate arranged such that an electrical conductivity of the conduction path can be modulated by application of a voltage to the gate; providing a substantially fixed distribution of charge arranged to produce anelectric field; andproviding insulative material separating said distribution of charge from said semiconductor material, the arrangement being such that the semiconductor material is exposed to said electric field and the electrical conductivity of the conduction path is determined at least in part by the voltage applied to the gate and by the charge distribution.21. A method in accordance with claim 20, wherein said providing of a substantially fixed distribution of charge comprises providing a body of a further material containing said distribution of charge.22. A method in accordance with claim 21, wherein said body of further material has a substantially fixed polarisation.23. A method in accordance with claim 21 or claim 22, wherein said body of further material is formed as a layer.24. A method in accordance with claim 23, wherein said layer is a self assembled monolayer. .s 2 * * **I.25. A method in accordance with claim 23 or claim 24, further comprising providing a body of insulative material having a surface, and wherein providing the body of further material comprises forming a layer of said further material on said surface.: 30 26. A method in accordance with claim 25, wherein forming said layer of further material on said surface comprises forming said layer using at least one technique selected from a list comprising: spin-coating or other solution processing deposition; vapour deposition; vacuum deposition.27. A method in accordance with claim 25 or claim 26, further comprising processing said surface before forming said layer on said surface.28. A method in accordance with claim 27, wherein said processing is arranged to improve adhesion of the further material to the surface.29. A method in accordance with claim 27 or claim 28, wherein said processing comprises exposing said surface to a plasma.30. A method in accordance with any one of claims 25 to 29, wherein providing said body of insulative material comprises forming a layer of insulative material on a substrate.31. A method in accordance with claim 30, wherein the layer of insulative material is formed using at least one technique selected from a list comprising: vacuum deposition; vapour deposition; sputter coating; sol-gel processing; sputter coating; doctor blade techniques; spin coating; printing, including screen printing and ink-jet printing; aqueous processing for inorganic oxides.32. A method in accordance with claim 30 or claim 31, wherein forming said layer of insulative material comprises spin coating the substrate with a solution containing the insulative material.33. A method in accordance with claim 32, further comprising selecting the concentration of said solution to determine the thickness of the layer of insulative * ** * * * material formed. * *. *SS. * S *S*34. A method in accordance with any one of claims 23 to 33, wherein said providing of insulative material separating said distribution of charge from said semiconductor material comprises forming a separating layer of insulative material on the layer of :., further material containing the distribution of charge. * 3035. A method in accordance with claim 34, wherein the forming of the separating layer comprises forming the separating layer of insulative material using at least one technique selected from a list comprising: vacuum deposition; vapour deposition; sputter coating; sol-gel processing; sputter coating; doctor blade techniques; spin coating; printing, including screen printing and ink-jet printing; aqueous processing for inorganic oxides.36. A method in accordance with claim 34 or claim 35, wherein the forming of the separating layer comprises spin coating the layer of material containing the distribution of charge with a solution containing insulative material.37. A method in accordance with any one of claims 34 to 36, wherein said providing of semiconductor material comprises forming a layer of said semiconductor material on the separating layer.38. A method in accordance with claim 37, wherein said forming of a layer of said semiconductor material comprises forming the layer of semiconductor material using a technique selected from a list comprising: spin coating, sputter-coating, sol-gel processing, atomic-layer deposition embossing of nanoparticle precursors, aqueous processing.39. A method in accordance with claim 37 or claim 38, wherein said forming of a layer of said semiconductor material comprises spin coating the separating layer with a solution containing said semiconducting material.40. A method in accordance with any one of claims 37 to 39, wherein said providing of a source and a drain comprises forming said source and said drain on the layer of semiconductor material.*. 41. An electronic device comprising: . 25 semiconductor material arranged to provide an electrical conduction path; * *..a substantially fixed distribution of charge arranged to produce an electric field; * * an insulative material arranged to separate the distribution of charge from the semiconductor material, *s *.: * * 30 the arrangement being such that semiconductor material is exposed to said electric field and said electric field affects the electrical conductivity of the conduction path.42. An electronic circuit comprising at least one FET or electronic device in accordance with any preceding claim.43. Apparatus comprising at least one FET, electronic device, or electronic circuit in accordance with any preceding claim.44. A method of manufacturing an electronic device, the method comprising: providing semiconductive material arranged to provide an electrical conduction path: providing a substantially fixed distribution of charge arranged to produce anelectric field; andproviding insulative material arranged to separate the distribution of charge from the semiconductive material, the arrangement being such that the semiconductive material is exposed to the electric field and the electric field affects the electrical conductivity of the conduction path.45. A FET, an electronic device, an electronic circuit, apparatus, a method of manufacturing a FET, or method of manufacturing an electronic device substantially as hereinbefore described with reference to the accompanying figures. * S. * S * *. * *S..... * S * * . *. *. * I *S IS.