JP2002299477A - Nonvolatile semiconductor memory and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable nonvolatile semiconductor memory, and its fabricating method, in which the rewritable number of times can be increased by reducing charge damage of a floating gate at the time of fabricating a split gate type flash memory cell. SOLUTION: A floating gate FG on a gate oxide film 11 is formed by patterning using the selectively oxidized part 12 of a polysilicon layer as a mask. A control gate CG is formed by patterning from above a part of the floating gate FG to the vicinity of one side part through a gate oxide film 14. The floating gate FG side where at least the upper part is not covered with the control gate CG is coated with a protective film 15 having an etch selectivity different from that of an oxide film 16 being formed latter by plasma etching thus suppressing charge damage due to plasma.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, which focuses on an improvement accompanied by an increase in the number of rewritable times (endurance) of a split gate type flash memory (Flash EEPROM) cell.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices have been integrated and scaled down on a large scale, and a low power supply voltage-boosted voltage operation has been generalized. In a split gate type flash memory, charge injection / release operations are performed through different gate insulating films due to their cell configurations.
This has the advantage that the quality of the oxide film involved in charge injection / release operations is not easily deteriorated.

FIG. 7 is a sectional view showing an example of a cell structure in a conventional split gate flash memory. Floating gate FG on gate oxide film 101
Is patterned using a portion (including a broken line) 102 obtained by selectively oxidizing the polysilicon layer as a mask. Thereby, the gate end 103 has a pointed form.

The control gate CG is formed by patterning from a portion of the floating gate FG to a portion adjacent to one side portion via the gate oxide film 104.
Generally, the formation of the control gate CG and the formation of the gate electrode of another MOS transistor (not shown) are performed in the same step. An oxide film 105 covering the control gate CG is formed.

To write data to the memory cell having the above configuration, a high voltage is applied to the control gate CG and the source S. Thereby, thermal electrons are injected into floating gate FG via gate oxide film 101 (data "0" state). Data erasing is performed by the source S and the drain D
Is released to apply a high voltage to the control gate CG.
As a result, electrons are extracted from the floating gate end 103 toward the control gate CG by the tunnel effect (data "1" state).

[0006] The tunnel current at the time of erasing can be easily generated from the sharp floating gate end 103.
Therefore, the thickness of the gate oxide film 104 can be set to be relatively large (about 20 nm). Also, the high voltage applied to the control gate CG can be set relatively low. As a result, the life of the oxide film involved in charge injection / release operations can be extended,
This is a configuration that contributes to an improvement in the number of data rewrites (endurance).

[0007]

It should be noted that in the memory cell having the above-described structure, the oxide film portion (10) on the floating gate FG which is not covered with the control gate CG.
5, 102), the manufacturing process proceeds while being partially etched as shown by the solid line.

FIG. 8 is a cross-sectional view showing a step of forming a sidewall (sidewall insulating film) in another MOS transistor region which causes the above-mentioned etching state. A gate electrode G is formed by the same process as the control gate CG, and an oxide film 105 for forming a sidewall is deposited on the way through necessary ion implantation (not shown), and is formed into a desired shape by anisotropic etching. The formation of the oxide film 105 is the oxide film 105 in the memory cell of FIG. 7, and forms an oxide film etched portion on the floating gate FG.

The etched portion of the oxide film on the floating gate FG is opposite to the point where the tunnel current is generated, and an oxide film (not shown) between layers is deposited later, so that there is no problem in appearance. . However, during the etching, the surface of the floating gate FG is exposed to an etching atmosphere (plasma).

According to the above configuration, the floating gate FG receives charge damage due to plasma during anisotropic etching (plasma etching) of the oxide film 105. Therefore, during the manufacturing process, electrons may collect in the tunnel current generating portion of the oxide film 104 and the quality of the film may be degraded, and there is a concern that the number of rewritable times (endurance) of the cell may be reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high reliability that reduces charge damage to a floating gate in manufacturing a split gate type flash memory cell and improves the number of rewritable times. An object is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0012]

A nonvolatile semiconductor memory device according to the present invention relates to a flash memory cell of a split gate type, comprising: a floating gate formed on a semiconductor substrate via a first gate oxide film; A control gate formed through a second gate oxide film from a part of the floating gate to a portion adjacent to one side portion, and at least an upper part is covered on the floating gate side not covered by the control gate And an insulating film to be formed later by etching and a protective film having a different etching selectivity.

Further, a method of manufacturing a nonvolatile semiconductor memory device according to the present invention relates to a split gate type flash memory cell, wherein a step of forming a floating gate on a semiconductor substrate via a first gate oxide film; Forming a control gate via a second gate oxide film from a portion of the floating gate to the vicinity of one side portion, and at least on a side of the floating gate where at least an upper portion is not covered by the control gate, Covering the insulating film to be formed by etching and a protective film having a different etching selectivity.

According to the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention, the floating gate
The protection film prevents exposure to an etching atmosphere (plasma). Thereby, charge damage is suppressed.
Preferably, the protective film is a nitride film, which also contributes to moisture prevention. In addition, the floating gate is formed by patterning using a portion where the polysilicon layer is selectively oxidized as a mask. The floating gate has a sharp edge, and a tunnel current generation path through the gate oxide film to the control gate. Is easily configured.

Further, the insulating film to be etched is formed by the same process as the plasma etching for the sidewall insulating film of the MOS transistor in other regions. That is, while the floating gate is protected by the protective film, the insulating film can be etched into a desired shape in another region.

[0016]

FIG. 1 is a sectional view showing a cell structure of a split gate type flash memory according to an embodiment of the present invention. The floating gate FG on the gate oxide film 11 on the silicon substrate 10 is formed by patterning using the portion 12 obtained by selectively oxidizing the polysilicon layer as a mask. Thus, the gate end 13 has a pointed form. With such an embodiment, the path of the tunnel current generation to the control gate CG via the gate oxide film 14 can easily become a narrow region, which contributes to the reduction of the defective rate.

The control gate CG is formed by patterning from a portion of the floating gate FG to a portion adjacent to one side portion via the gate oxide film 14. Generally, the formation of the control gate CG and the formation of the gate electrode of another MOS transistor (not shown) are performed in the same step.

In this embodiment, a protective film 15 having an etching selectivity different from that of an oxide film 16 to be formed later is covered on the side of the floating gate FG which is not covered by the control gate CG.

The oxide film 16 is formed in the same step as the sidewall insulating films (sidewalls) of the MOS transistors in other regions, and has a shape formed by anisotropic etching (plasma etching). That is, before the plasma etching step, the floating gate FG side that is not covered with the control gate CG is covered with the protective film 15 so that the floating gate FG is not directly exposed to plasma in the plasma etching after the oxide film 16 is deposited. did.

When writing data to the memory cell having the above-described structure, a high voltage is applied to the control gate CG and the source S. Thereby, thermal electrons are injected into floating gate FG via gate oxide film 11 (data “0”).
Status). To erase data, the source S and the drain D are released and a high voltage is applied to the control gate CG. As a result, electrons are extracted from the floating gate end 13 to the control gate CG side by the tunnel effect (data "1" state).

A tunnel current at the time of erasing can be easily generated from the sharp floating gate end portion 13. Therefore, the thickness of the gate oxide film 14 can be set to be relatively large (about 20 nm). Also, the high voltage applied to the control gate CG can be set relatively low. As a result, the life of the oxide film involved in the charge injection / release operation can be extended, and the configuration contributes to the improvement of the number of data rewrites (endurance).

The protective film 15 is made of, for example, a nitride film (silicon nitride film), and serves as an etching stopper film for the selectively oxidized portion 12 on the floating gate FG.
It also protects the side of the floating gate FG. This suppresses charge damage during plasma etching. Therefore, the number of times of rewriting of data is further improved and the reliability is high.

FIGS. 2 to 5 are cross-sectional views showing a main part of a method of manufacturing the split gate type flash memory cell of FIG. 1 according to the present invention in the order of steps. FIG.
The same parts as those described above are denoted by the same reference numerals and described. , FIG. 2
As shown in FIG. 5, a floating gate FG is formed on a gate oxide film 11 on a silicon substrate 10. The floating gate FG is formed by forming a resist pattern (not shown) on the polysilicon layer and using the selectively oxidized portion 12 as a mask. Thus, the gate end 13 has a pointed form.

Next, as shown in FIG. 3, a gate oxide film 14 is formed through the same oxide film forming process as that of another MOS transistor region (not shown), and one of the floating gates FG is formed thereon from one side. The control gate CG including the polysilicon layer is formed by patterning in the vicinity of the side portion adjacent to the above. The formation of the control gate CG and the formation of the gate electrode of another MOS transistor (not shown) are performed in the same step. Although not shown, the upper part of the control gate CG may be silicided.

Next, as shown in FIG. 4, the floating gate FG whose upper part is not covered by the control gate CG is
To protect the side, a nitride film (silicon nitride film) is covered as a protective film 15 over the entire cell structure. Protective film 15
May be about 10 to 15 nm for plasma protection.

Next, as shown in FIG. 5, an oxide film 16 is deposited on the entire cell structure. Then, oxide film 16 is anisotropically etched (plasma etched) to form a sidewall for another MOS transistor. At this time, the floating gate FG is formed of a protective film (nitride film) 15.
Avoids direct exposure to the plasma. Subsequent ion implantation of the source line and ion implantation of the drain region are performed via the protective film (nitride film) 15. That is, it is achieved by adjusting the ion implantation energy in consideration of the protective film (nitride film) 15.
Thereby, the configuration of the split gate type flash memory cell as shown in FIG. 1 can be realized.

FIGS. 6A and 6B show other MOs, respectively.
FIG. 4 is a cross-sectional view of a main part, showing the steps of forming an S transistor in order. The portions formed in the same steps as those in FIG.

As shown in FIG. 6A, in another MOS transistor, a gate electrode G is formed in the same step as the formation of the control gate CG in the cell structure of FIG. The gate oxide film 61 may be formed in any oxidation step of the cell structure of FIG. 1 and is formed through an oxidation step suitable for a designed film thickness.

Although not shown, a necessary ion implantation step (well, channel doping, etc.) into the substrate has been performed up to this configuration. And the floating gate FG
This is the formation of a protective film (nitride film) 15 for protection. The other MOS transistors are formed so as to cover the gate electrode G, and contribute to improvement in resistance to moisture and hydrogen.

Next, as shown in FIG.
After the deposition of No. 6 and anisotropic etching (plasma etching), sidewalls of the oxide film 16 are formed. Subsequent ion implantation of source / drain regions (not shown)
This is performed via a protective film (nitride film) 15. That is, it is achieved by adjusting the ion implantation energy in consideration of the protective film (nitride film) 15.

According to the method of the above embodiment, the floating gate FG of the cell is not exposed to the etching atmosphere (plasma) by the protective film 15 made of a nitride film, and the oxide film 16 is formed in a desired shape in other regions. Can be etched. Thereby, charge damage to the floating gate FG is suppressed. Therefore, the quality of the portion of the oxide film 14 where the tunnel current is generated is hardly degraded during the manufacturing process as in the prior art, and an improvement in the number of rewrites (endurance) of the cell can be expected. In addition, since the protective film 15 made of a nitride film covers the entire cell structure, moisture,
It contributes to the improvement of resistance to hydrogen and hot carrier resistance.

[0032]

As described above, according to the present invention,
At least the upper side of the floating gate that is not covered with the control gate is covered with a protective film having a different etching selectivity from an insulating film to be formed later. This prevents the floating gate from being exposed to the etching atmosphere (plasma) by the protective film.
As a result, it is possible to provide a highly reliable nonvolatile semiconductor memory device capable of reducing the charge damage of the floating gate at the time of manufacture in a split gate type flash memory cell and improving the number of rewritable times, and a method of manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a cell structure of a split gate flash memory according to an embodiment of the present invention.

2 is a first cross-sectional view showing a main part of a method of manufacturing the split gate type flash memory cell of FIG. 1 according to the present invention in the order of steps.

FIG. 3 is a second cross-sectional view following FIG. 2 showing a main portion of a method of manufacturing the split gate flash memory cell of FIG. 1 according to the present invention in the order of steps;

FIG. 4 is a third cross-sectional view following FIG. 3 showing a main portion of a method of manufacturing the split gate flash memory cell of FIG. 1 according to the present invention in the order of steps;

FIG. 5 is a fourth cross-sectional view following FIG. 4 showing a main portion of a method of manufacturing the split gate flash memory cell of FIG. 1 according to the present invention in the order of steps;

FIGS. 6A and 6B are cross-sectional views of essential parts sequentially showing steps of forming another MOS transistor.

FIG. 7 is a cross-sectional view showing an example of a cell structure in a conventional split gate flash memory.

8 is a cross-sectional view showing a step of forming a sidewall (sidewall insulating film) in another MOS transistor region that causes the configuration (etched state) of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 11, 14, 61, 101, 104 ... Gate oxide film 12, 102 ... Oxidized part 13, 103 ... Gate edge 15 ... Protective film 16, 105 ... Oxide film FG ... Floating gate CG ... Control gate G ... Gate electrode

Continued on the front page F-term (reference)

Claims (5)

[Claims] 1. A split gate type flash memory cell, comprising: a floating gate formed on a semiconductor substrate via a first gate oxide film; A control gate formed via the second gate oxide film, and a protection having an etching selectivity different from that of an insulating film to be formed later, which is covered at least on the floating gate side not covered by the control gate. And a film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said protection film is a nitride film. 3. A step of forming a floating gate on a semiconductor substrate via a first gate oxide film in a split gate type flash memory cell; Forming a control gate through a second gate oxide film over the floating gate, at least on the side of the floating gate which is not covered by the control gate, and a protective film having a different etching selectivity from an insulating film formed later by etching. A method of manufacturing a nonvolatile semiconductor memory device, comprising: 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein said floating gate is patterned by using a portion obtained by selectively oxidizing a polysilicon layer as a mask. 5. The nonvolatile semiconductor memory device according to claim 3, wherein said insulating film to be etched is formed by the same process as plasma etching for a sidewall insulating film of a MOS transistor in another region. Production method.