JP2002299449A - Semiconductor integrated circuit and method of designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of designing semiconductor integrated circuit by which a hierarchized layout can be designed by paying attention to wiring connected to another block, etc., in addition to a block so that no antenna effect may occur even in the wiring. SOLUTION: In the wired portions W112 and W113 of the signal lines of each block to the outside near the boundaries of the block, highest-order wiring layers are used regardless of the wired direction and lengths of the signal lines. Even when one of both ends connected by the wiring formed of the highest-order wiring layers is connected to the gate of a transistor, the other end is connected to the drain of another transistor. Consequently, the charges caused by plasma charges generated during the etching of the highest-order wiring layers leak to the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit in which a circuit to be incorporated is divided into blocks and the layout design is hierarchized. Also, the present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit that can easily design a wiring that does not cause an antenna effect.

[0002]

2. Description of the Related Art At the time of plasma etching during the manufacture of a semiconductor integrated circuit chip, a charge is given to a wiring pattern being etched by plasma charge, and when the wiring pattern is connected to the gate of a transistor,
An antenna effect is known in which a gate insulating film of a transistor is destroyed by an abnormal voltage generated by the charge. In recent years, LSI (Large Scale Integrated
With the miniaturization of the manufacturing process of the circuit, the gate insulating film of the transistor becomes thinner, the breakdown voltage of dielectric breakdown becomes lower, and such an antenna effect tends to occur easily.

The above-described plasma charge becomes stronger as the surface area of the wiring pattern in the exposed metal wiring layer being etched increases. In an internal circuit of a semiconductor integrated circuit, there is a value (upper limit) of the amount of charge that can be withstood at an input block pin (gate of a transistor used internally). Further, in an internal circuit of a semiconductor integrated circuit, there is a value of an amount of charge that can leak at an output block pin (drain of a transistor used internally). Since the value of the amount of charge that can be leaked is much larger than the value of the amount of charge that the gate can withstand, if the wiring pattern connected to the gate is connected to the drain, the amount of plasma charge through the drain is reduced. The charge leaks and no antenna effect occurs.

A block pin is a virtual pin in a layout design that is defined in a portion for inputting and outputting a signal to and from the outside of the block. The definition of this block pin is mainly based on CAD (Computer)
Aided Design) system.

Therefore, in a CAD wiring tool used for designing a layout of a semiconductor integrated circuit, the surface area of a wiring pattern formed of a single metal wiring layer connected to a gate of a transistor is equal to or larger than a predetermined reference value depending on the value of these charges. Is automatically calculated. If it exceeds a predetermined reference value, it is treated as an antenna error. In addition, when such an antenna error occurs, the antenna error is deleted by automatically allocating all or a part of the corresponding wiring pattern to the wiring pattern of the upper or lower metal wiring layer. . The wiring tool has automatic processing to deal with the problem of the antenna effect in this way.

For example, FIGS. 3 to 5 schematically show vertical cross sections of a semiconductor integrated circuit. In these figures,
Transistors T5 and T6 formed by a source and a drain formed on a semiconductor substrate and a gate provided above a channel region therebetween are schematically indicated by circuit symbols of the transistors. Further, regarding these transistors T5 and T6,
The wiring patterns, contacts and vias of the first to third metal wiring layers L1 to L3 are indicated by solid lines. Note that the bold line is a wiring during formation of a wiring pattern by etching.

As shown in FIGS. 3 to 5, when a wiring pattern is formed in the first metal wiring layer L1 to the third metal wiring layer L3 to manufacture a semiconductor integrated circuit, antenna errors include the following. deal with.

First, in the stage of FIG. 3, the first metal wiring layer L
In 1, a wiring pattern is formed. For example, the code W2
02, a wiring pattern of W203 is formed.

At this time, since the wiring W201 is connected to the gate of the transistor T5, in order to prevent damage to the gate insulating film, the surface area of the wiring W201 must be equal to or less than a predetermined reference value that causes an antenna error. There is a need to. The wiring W202 is not connected to any of the transistors, and the wiring W203 is connected to the drain of the transistor T6, so that charges due to plasma charge leak. Therefore, these wirings may cause an antenna error. There is no limit on the surface area for antenna errors. The wiring W20
The charge due to the plasma charge in FIG.
Is leaked before moving on to the process.

Next, at the stage of FIG. 4, the second metal wiring layer L
In 2, a wiring pattern is formed. For example, the code W2
11, W212, and W213 wiring patterns are formed.

At this time, since the wirings W211 and W212 are connected to the gate of the same transistor T5, the total surface area of the wirings W211 and W212 is reduced so as not to damage the gate insulating film. It is necessary to keep the antenna error below a predetermined reference value. The wiring W213 is connected to the drain of the transistor T6.
Since the charge is leaked due to the charge, there is no possibility of an antenna error, and there is no limit on the surface area of the antenna error.

Subsequently, at the stage of FIG. 5, a wiring pattern is formed in the second metal wiring layer L3. For example, the code W
217 wiring patterns are formed.

At this time, since the wiring W217 is connected to the drain of the transistor T6, the electric charge due to the plasma charge is leaked.
There is no risk of error and there is no limit on surface area for antenna errors.

In designing such wiring patterns with reference to FIGS. 3 to 5, if there is a possibility that an antenna error will occur if the surface area of the wiring pattern to be formed is large, as described above, the antenna effect is determined by the wiring tool. The problem is automatically addressed.

[0015]

Here, in the hierarchical layout design, a large-scale circuit to be laid out is designed.
The layout is designed so that it is divided into lower-layer blocks to a size that is easy to handle. In some cases, this block is further subdivided and further divided into lower-layer blocks, and the layout is designed. In the hierarchical layout design, the blocks divided in this way are separately designed between and within the blocks, and finally the layout of the entire semiconductor integrated circuit is assembled. In the hierarchical layout design, since the design is performed in such divided units, the data to be handled is also divided and reduced, and the design efficiency can be improved.

For example, when designing a semiconductor integrated circuit as shown in FIG. 6, the entire circuit is divided into a first circuit part and a second
Divide into circuit parts.

Further, the first circuit portion is divided into an A macro circuit, a B macro circuit, and a C macro circuit of a lower hierarchy. The second circuit portion is divided into a D macro circuit and an E macro circuit of a lower hierarchy.

In the layout design when the layers are hierarchized in this manner, for example, in the layout diagram of the semiconductor integrated circuit shown in FIG. 7, the first circuit portion and the second circuit portion are arranged as indicated by reference numerals 11 and 12, respectively. You. Further, in the first circuit portion 11, the A macro circuit, the B macro circuit, and the C macro circuit are arranged as denoted by reference numerals 21 to 23, respectively. In the second circuit portion 12, the D macro circuit and the E macro circuit are arranged as indicated by reference numerals 24 and 25, respectively. In FIG. 7, reference numeral 1 denotes an entire circuit in a semiconductor integrated circuit chip.

The automatic processing for the antenna effect by the wiring tool described above relates to a single-layer layout design in which no hierarchical layout design is adopted.

Even when the hierarchical layout design is adopted, the automatic processing can be performed for each layer from the lower layer to the uppermost layer when designing the hierarchical layout. However, for wiring that straddles different hierarchies or straddles different blocks in the same hierarchy,
When the automatic processing is performed for each layer as described above, the calculation of the surface area of the wiring by the metal wiring layer which is electrically connected and exposed during the etching may be divided into layers or divided into blocks. I get lost.

In a layout design, usually, on a plane parallel to the upper surface of a semiconductor substrate, it is determined which metal wiring layer is to be used for horizontal wiring and which metal wiring layer is to be used for vertical wiring.

For example, when there are first to sixth metal wiring layers from the substrate side of the semiconductor to the uppermost layer side, the horizontal wiring has the first, third and fifth layers. A case is considered in which a metal wiring layer is used and the second, fourth, and sixth metal wiring layers are used for vertical wiring. In this case, individual blocks designed by hierarchical layout design usually have
Block pins for inputting / outputting signals outside the block on the left and right sides of the block include a first layer, a third layer, and a fifth layer.
The second, fourth, and sixth metal wiring layers are used for block pins for inputting and outputting signals to and from the outside of the block on the upper side and the lower side of the block.

Here, consider wiring that extends over the outside and inside of a block, that is, between different layers or between different blocks even in the same layer, as follows.

That is, in a certain block, a wiring having a surface area that does not cause an antenna error due to the first metal wiring layer connected to the gate of the internal transistor is connected to a block pin formed by the first metal wiring layer. It is assumed that it is connected to Also, outside the block,
It is assumed that a wiring having a surface area that does not cause an antenna error by the first metal wiring layer is connected to the block pin. Further, it is assumed that the wiring outside the block is not connected to, for example, the drain of the transistor other than the block pin when the wiring is etched by the first metal wiring layer.

In such a wiring extending between layers or between blocks, the sum of the surface area of the wiring formed by the first metal wiring layer in the block and the surface area of the wiring formed by the first metal wiring layer outside the block is obtained. Larger values result in antenna errors.

However, such an antenna
If an automatic process for the above-described antenna effect is performed from the lower hierarchy to the uppermost hierarchy at the time of hierarchical layout design for each layer or block in an error, wiring between layers or blocks, an error is automatically generated for the antenna error. Can't cope. Because the automatic processing is performed for each layer or for each block, the first in the block
An antenna error is not caused by the surface area of the wiring formed by the first metal wiring layer, and an antenna error is not caused by the surface area of the wiring formed by the first metal wiring layer outside the block.
This is because the antenna error in the total area of these surface areas is not addressed.

In order to correctly deal with an antenna error in a wiring extending between the outside and the inside of the block, that is, between the layers or between the blocks, one of the wirings outside or inside the block is determined. Or the wiring of one of the two levels must be fixed. In addition, it is necessary to have the wiring tool perform complicated processing such as holding wiring information indicating a wiring path at a hierarchical boundary and performing wiring on the other side based on the information. Therefore, there is a problem that it is necessary not only to develop a complicated wiring tool program, but also a problem that the processing time of the program becomes longer and the efficiency of the operation using the wiring tool becomes worse.

The present invention has been made in order to solve the above-mentioned conventional problems. When a hierarchical layout design is performed, an antenna effect is generated even for another block or a wiring connected to another block outside the block. It is an object of the present invention to provide a semiconductor integrated circuit design method and a semiconductor integrated circuit that can easily perform a design in consideration of the absence.

[0029]

First, a semiconductor integrated circuit design method according to a first invention of the present application is a semiconductor integrated circuit design method in which a circuit to be incorporated is divided into blocks and a layout design is hierarchized. All block pins on the input / output part of the line to the outside of the block
By forming using the top wiring layer,
This has solved the above-mentioned problem.

Next, in the semiconductor integrated circuit according to the second aspect of the present invention, the pattern of the circuit to be incorporated is laid out in blocks, and the wiring of the signal lines crossing the boundaries of the blocks is independent of the wiring direction. The problem has been solved by using the uppermost wiring layer.

Hereinafter, the operation of the present invention will be briefly described.

In the present invention, at least a wiring portion of the signal line to the outside of each block near the block boundary portion is provided regardless of the wiring direction and the wiring length of the signal line.
The uppermost wiring layer is used exclusively. The signal line to the outside of each block is a signal line that crosses a block boundary.

Since the uppermost wiring layer is used for a signal line crossing the block boundary to the outside of such a block, the lower wiring is already formed at the time of forming the wiring pattern of the uppermost wiring layer. ing. Therefore, even if one of both ends connected by the wiring formed in the uppermost wiring layer is connected to the gate of the transistor,
The other is connected to the drain of another transistor.

Therefore, the charge due to the plasma charge generated during the etching of the uppermost wiring layer is leaked to the drain, so that no antenna error occurs.

As for the antenna error in the same layer, such as in each block, the problem of the antenna effect may be automatically dealt with by the wiring tool as described above as the related art. Further, when the present invention is applied, the uppermost wiring layer is used for the wiring of the signal line crossing the block boundary as described above, but may be used for the wiring in the same hierarchy such as in the same block. For these, the present invention is not specifically limited.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a vertical sectional view of a first embodiment of a semiconductor integrated circuit manufactured by a semiconductor integrated circuit designing method to which the present invention is applied.

In FIG. 1 and FIG.
The dashed line is the block boundary. The block pins are
It is shown as a dashed rectangle.

In this embodiment, the fifth metal wiring layer L5
Becomes the uppermost wiring layer. The wiring having block pins uses the fifth metal wiring layer L5 of the uppermost wiring layer.

Therefore, in the step of forming a wiring having a block pin, even if one of both ends connected by the wiring formed in the uppermost wiring layer is connected to the gate of the transistor, the other is connected. , Are connected to the drains of other transistors. For example, for the wiring W113 on the right side of the dashed line, the transistor T2
Connected to the drain of

Therefore, since the charge due to the plasma charge generated during the etching of the uppermost wiring layer is leaked to the drain, no antenna error occurs. And
The effect of plasma charge between blocks and between layers is substantially eliminated, such as the effect of plasma charge on wiring outside the block inside the block.

In this embodiment, the block pins provided at the input / output portion of the signal line with respect to the outside of the block are defined to be formed using the uppermost wiring layer.

If a block pin is defined to be formed using the uppermost wiring layer, wiring connected to the block pin, that is, a signal line extending between blocks or between hierarchies, is at least near the block boundary. Inevitably, the uppermost wiring layer will be used for the wiring portion.
Therefore, the present invention is necessarily applied.

As described above, in the present embodiment, the present invention can be effectively applied. Therefore, in a hierarchical layout design, it is possible to easily design a wiring that is connected to other blocks and the like outside the block so as not to cause an antenna effect.

FIG. 2 is a vertical sectional view of a semiconductor integrated circuit manufactured by a semiconductor integrated circuit designing method according to a second embodiment of the present invention.

In this embodiment, the sixth metal wiring layer L6
Becomes the uppermost wiring layer. The wiring having block pins uses the sixth metal wiring layer L6 of the uppermost wiring layer.

Therefore, in the step of forming a wiring having a block pin, even if one of both ends connected by the wiring formed in the uppermost wiring layer is connected to the gate of the transistor, the other is connected. , Are connected to the drains of other transistors. For example, regarding the wiring W123 on the right side of the dashed line, the transistor T4
Connected to the drain of

Therefore, the charge due to the plasma charge generated during the etching of the uppermost wiring layer is leaked to the drain, so that no antenna error occurs. In addition, there is substantially no influence between the blocks or between layers due to the plasma charge, such as the influence of the plasma charge on the wiring outside the block inside the block.

Also, as in the first embodiment, in this embodiment, the block pins provided at the input / output portion of the signal line with respect to the outside of the block, which are indicated by the dashed squares, It is defined to be formed using: Therefore, the wiring connected to the block pin, that is,
Regarding signal lines that extend between blocks and between layers, at least the wiring near the block boundary part
The uppermost wiring layer is used. Therefore, the present invention is necessarily applied.

As described above, in the present embodiment, the present invention can be effectively applied. Therefore, in a hierarchical layout design, it is possible to easily design a wiring that is connected to other blocks and the like outside the block so as not to cause an antenna effect.

It is to be noted that, on a chip of an actual semiconductor integrated circuit, the block boundary itself indicated by the dashed line is not clear. For example, a mark indicating a block boundary is rarely attached on a semiconductor substrate. However, when the present invention is applied, a wiring pattern peculiar to the present invention that the uppermost wiring layer is used irrespective of the wiring direction, crosses a block boundary, or crosses a place estimated to be a block boundary. , The wiring of the signal line is observed. Therefore, when observing the layout on the completed semiconductor integrated circuit chip, the existence of the block boundary and the effect obtained by applying the present invention are obtained by the wiring direction and distribution of the wiring using the uppermost wiring layer. It becomes clear whether or not.

[0052]

According to the present invention, at the time of hierarchical layout design, it is possible to easily design a wiring connected to the outside of a block with respect to another block so as not to cause an antenna effect. be able to.

[Brief description of the drawings]

FIG. 1 is a vertical sectional view of a first embodiment of a semiconductor integrated circuit manufactured by a semiconductor integrated circuit designing method to which the present invention is applied;

FIG. 2 is a vertical sectional view of a semiconductor integrated circuit manufactured by a semiconductor integrated circuit design method according to a second embodiment of the present invention;

FIG. 3 is a first vertical sectional view showing a conventional process of manufacturing a semiconductor integrated circuit;

FIG. 4 is a second vertical sectional view showing the manufacturing process.

FIG. 5 is a third vertical sectional view showing the manufacturing process.

FIG. 6 is a diagram showing a hierarchical example in a conventional hierarchical layout design of a semiconductor integrated circuit;

FIG. 7 is a layout diagram of a semiconductor integrated circuit showing a layout example of the above hierarchical example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 11 ... 1st circuit part 12 ... 2nd circuit part 21-25 ... Macro circuit L1-L6 ... Metal wiring layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 27/04 D 21/822 H F term (Reference) 5B046 AA08 BA06 5F033 QQ08 QQ12 UU04 XX00 XX03 XX31 5F038 BH11 CA17 CD05 CD20 EZ09 EZ15 EZ20 5F064 DD04 DD32 EE26 GG03 HH06

Claims (2)

[Claims] In a semiconductor integrated circuit design method in which a circuit to be incorporated is divided into blocks and a layout design is hierarchized, all block pins provided in an input / output portion of a signal line of each block with respect to the outside of the block are top-level. A method for designing a semiconductor integrated circuit, wherein the method is formed using a wiring layer. 2. The pattern of a circuit to be incorporated is laid out in blocks, and the uppermost wiring layer is used for wiring of signal lines crossing the boundaries of the blocks regardless of the wiring direction. Semiconductor integrated circuit.