JP2002296617A - Display device and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device and a liquid crystal display device capable of improving the display quality and lowering power consumption without complicating the structures. SOLUTION: The display device comprises a pixel array part 2, a signal line driving circuit 3 driving signal lines 11 and a scanning line driving circuit 4 driving scanning lines 12. The drain terminal of a pixel TFT 1 is connected to the signal line 11, whereas the source terminal is connected to a first auxiliary capacitor C1 that is also connected to an auxiliary capacitor line L1. A second auxiliary capacitor C2 is connected to the path between the source terminal of the pixel TFT 1 and the first auxiliary capacitor C1 through a capacitor controlling TFT 6. When the driving frequency of the pixel TFT 1 becomes a specified value or less, the capacitor controlling TFT 6 turns on and electric charge will be stored in the second auxiliary capacitor 2 in accordance with the signal line voltage. This prevents fluctuation of the voltage of a pixel electrode 5 when the charge stored in the first auxiliary capacitor C1 is discharged and results in the improvement of the display quality.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device and a liquid crystal display device which accumulate charges in an auxiliary capacitor via switching elements disposed near intersections of signal lines and scanning lines.

[0002]

2. Description of the Related Art A liquid crystal display device includes an array substrate on which signal lines and scanning lines are arranged, and an opposing substrate which is disposed opposite to the array substrate with a liquid crystal material interposed therebetween. As shown in FIG. 5, a pixel TFT 1 (Thin Film Transistor) is provided near each intersection of the signal line 11 and the scanning line 12 in the array substrate.
tor) is provided. The gate terminal of the pixel TFT 1 is connected to the scanning line 12, the drain terminal is connected to the signal line 11, and the storage capacitor C1 is connected between the source terminal and the storage capacitor line L1.

Each of the pixel TFTs 1 is sequentially driven at a predetermined frequency. When the pixel TFT 1 is turned on, an electric charge corresponding to the signal line voltage is accumulated in the auxiliary capacitor C1, and the luminance of the liquid crystal is adjusted according to the accumulated electric charge. Changes.

[0004]

Generally, the pixel TFT 1
Is driven at a frequency of about 60 Hz. However, once the pixel TFT 1 is driven, pixel display is performed by the electric charge accumulated in the auxiliary capacitor C1 until the next pixel TFT 1 is driven.

However, since the electric charge accumulated in the auxiliary capacitance C1 is gradually discharged, the lower the driving frequency is, the more the electric charge is accumulated.
The voltage of the connection path between the storage capacitor C1 and the pixel electrode is reduced, and color bleeding or the like occurs, thereby deteriorating the display quality.

On the other hand, in order to improve the display quality, the pixels T
When the driving frequency of the FT1 is increased, there is a problem that power consumption increases. In the case of an electronic device used in a mobile environment such as a mobile phone, it is necessary to extend the battery drive time as much as possible.

[0007] As a method of suppressing a decrease in display quality when the driving frequency of the pixel TFT 1 is reduced, a method of providing an SRAM for storing pixel information for each pixel has been proposed. If such an SRAM is provided, even if the storage charge of the auxiliary capacitor C1 is discharged, the pixel information can be continuously read from the SRAM, so that the display quality does not deteriorate. Since it becomes unnecessary, miniaturization becomes difficult, and the yield at the time of manufacturing deteriorates. In addition, there is a problem that it is difficult to realize gradation display in the SRAM.

[0008] The present invention has been made in view of such a point, and its object is to make the structure without complicating the structure.
An object of the present invention is to provide a display device and a liquid crystal display device that can improve display quality and reduce power consumption.

[0009]

In order to solve the above-mentioned problems, the present invention relates to a display device having a plurality of switching elements disposed near each intersection of a signal line and a scanning line. A first circuit that is connected on a current path passing through the element and stores a charge corresponding to a signal line voltage;
And a second capacitor element, and a switching circuit for switching whether or not to interrupt the current path between each end of the first and second capacitors.

In the present invention, a large-capacity second capacitor element is provided in addition to the first capacitor element which is a normal auxiliary capacitor. Therefore, even if the first capacitor element is discharged, the first capacitor element is discharged. Voltage drop at one end of the device can be suppressed, and display quality can be improved.

An array substrate having a plurality of switching elements disposed near each intersection of a signal line and a scanning line, and a counter substrate disposed to face the array substrate with a liquid crystal material interposed therebetween are provided. In a liquid crystal display device,
The array substrate is connected on a current path passing through the switching element, and stores first and second capacitor elements that accumulate charges according to a signal line voltage, and a case where a driving frequency of the switching element is higher than a predetermined frequency. Interrupts the current path between one ends of the first and second capacitor elements, and when the drive frequency is equal to or lower than the predetermined frequency, the current path is connected to one end of each of the first and second capacitor elements. And a switching circuit for conducting the current path therebetween.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device according to the present invention will be specifically described with reference to the drawings. Hereinafter, a polysilicon liquid crystal display device will be described as an example of the display device.

FIG. 1 is a diagram showing a circuit configuration around a pixel TFT in an array substrate constituting a liquid crystal display device, and FIG. 2 is a block diagram showing an entire configuration of the liquid crystal display device. As shown in FIG. 1, in the liquid crystal display device of the present embodiment, a signal line 11 and a scanning line 12 are arranged in a row, and a pixel TFT (switching element) 1 is arranged near an intersection of the signal line 11 and the scanning line 12. It includes a pixel array unit 2, a signal line driving circuit 3 for driving a signal line 11, and a scanning line driving circuit 4 for driving a scanning line 12. A signal line 11 is connected to the drain terminal of the pixel TFT1, and a first auxiliary capacitance (first capacitor element) C1 is connected between the source terminal and the auxiliary capacitance line L1. The first auxiliary capacitance C1 has the same capacitance value as the conventional auxiliary capacitance Cs.

Each of the pixel array section 2, the signal line driving circuit 3 and the scanning line driving circuit 4 in FIG. 1 is formed on a glass substrate by a TFT made of polysilicon.

In the present embodiment, a second storage capacitor (second connection) is connected to the connection path (connection path to the pixel electrode 5) between the source terminal of the pixel TFT 1 and the first storage capacitor C1 via the capacitance control TFT 6. It is characterized in that the capacitor element C2 is connected. The first storage capacitor C1 has a capacity similar to that of a conventional storage capacitor, while the second storage capacitor C2 has a larger capacity than the first storage capacitor C1.

The gate terminal of the capacitance control TFT 6 is connected to a capacitance control line (switching circuit) L2. A signal from, for example, a host device (not shown) is supplied to the capacitance control line L2. Alternatively, a signal for controlling the capacitance control TFT 6 may be generated in the array substrate.

According to the logic of the capacitance control line L2, the capacitance control T
The FT 6 is controlled to be turned on only when the driving frequency of the pixel TFT 1 is equal to or lower than a predetermined frequency (for example, 60 Hz).

When the capacitance control TFT 6 is off, that is, when the driving frequency of the pixel TFT 1 exceeds a predetermined frequency, charges corresponding to the signal line voltage are accumulated only in the first auxiliary capacitance C1. Further, while the capacitance control TFT 6 is on, that is, when the drive frequency of the pixel TFT 1 is equal to or lower than a predetermined frequency, electric charges corresponding to the signal line voltage are accumulated in the first and second auxiliary capacitances C1 and C2.

The second auxiliary capacitance C2 is equal to the first auxiliary capacitance C2.
Since the capacitance value is larger than 1, even if the driving frequency of the pixel TFT 1 is slow, there is no possibility that the electric charge accumulated in the second auxiliary capacitance C2 is completely discharged until the same pixel TFT 1 is driven next time. . Therefore, the voltage of the pixel electrode 5 does not fluctuate, and the display quality can be improved.

FIG. 3 is a plan layout view of the array substrate of the present embodiment. A portion surrounded by a thick solid line in FIG. 3 indicates the region 10 for one pixel. A signal line 11 is provided at a boundary position of the region 10 in the left-right direction in the figure, and an auxiliary capacitance line L1 is provided in a vertical direction in the figure.

The gate terminal of the pixel TFT 1 in one pixel region is connected to the scanning line 12, the drain terminal is connected to the signal line 11, and the source terminal is connected to one end of the first auxiliary capacitance C 1 and the drain terminal of the capacitance control TFT 6. Connected,
It is connected to the pixel electrode 5 via a contact hole (C / H) 13.

The source terminal of the capacitance control TFT 6 is connected to one end of the second auxiliary capacitance C2. First and second
The other ends of the auxiliary capacitances C1 and C2 are connected to the auxiliary capacitance line L1.
It is connected to the.

FIG. 4 is a plan layout diagram of a conventional array substrate having no capacitance control TFT and no second auxiliary capacitance. In the case of a conventional array substrate, the pixel electrodes 5 are arranged in almost all areas below the scanning lines 12 in one pixel area. In the present embodiment, since the capacitance control TFT 6 and the second auxiliary capacitance C2 are formed by using a part of the area where the pixel electrode 5 is conventionally arranged, the conventional technique can be used without changing the size of one pixel area. The same display resolution as described above can be obtained. Further, since the pixel TFT 1 and the first storage capacitor C1 are configured in the same manner as in the related art, the same manufacturing process technology as in the related art can be applied.

As described above, in this embodiment, in addition to the first auxiliary capacitor C1 having the same structure as the conventional one, the second auxiliary capacitor C2 having a large capacity is provided, and when the driving frequency of the pixel TFT 1 becomes lower than the predetermined frequency. Since the capacitance control TFT 6 is turned on to accumulate the electric charge corresponding to the signal line voltage also in the second auxiliary capacitance C2, even if the electric charge stored in the first auxiliary capacitance C1 is discharged, the pixel is not charged. The voltage of the electrode 5 stops fluctuating,
The display quality can be improved.

Further, since the second auxiliary capacitance C2 is formed in the region where the pixel electrode 5 is conventionally formed, the region for one pixel is the same as the conventional one and can be manufactured by the same manufacturing process as the conventional one. It is.

Further, as compared with a method in which an SRAM is provided in one pixel region to supplement the discharge of electric charge of the storage capacitor, the structure of one pixel region can be greatly simplified, so that the display resolution can be increased and SRAM can easily realize multi-gradation display which is technically difficult. Further, power consumption can be further reduced as compared with using an SRAM.

In the above-described embodiment, the size and location of the second storage capacitor C2 are not limited to the example shown in FIG. In the above-described embodiment, an example in which a polysilicon TFT is formed on a glass substrate has been described. However, the present invention is similarly applied to a TFT formed by another process (for example, an amorphous silicon TFT). It is possible.

[0028]

As described above in detail, according to the present invention, since the second capacitor element is provided in addition to the first capacitor element which is a normal auxiliary capacitance, the driving frequency of the switching element is low. Therefore, even if the first capacitor element is discharged, the voltage at one end of the first capacitor element does not decrease, and the display quality can be improved.

Further, according to the present invention, the structure can be simplified as compared with the case where an SRAM is provided in one pixel region to compensate for the electric discharge of the first capacitor element. Electric power can also be reduced. Also, multi-gradation display, which was technically difficult with SRAM, can be easily realized.

[Brief description of the drawings]

FIG. 1 shows a pixel T in an array substrate constituting a liquid crystal display device
FIG. 3 is a diagram illustrating a circuit configuration around an FT.

FIG. 2 is a block diagram illustrating an overall configuration of a liquid crystal display device.

FIG. 3 is a plan layout view of the array substrate of the embodiment.

FIG. 4 is a plan layout view of a conventional array substrate without a capacitance control TFT and a second auxiliary capacitance.

FIG. 5 is a diagram showing a circuit configuration around a pixel TFT of a conventional liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 1 pixel TFT 2 pixel array section 3 signal line drive circuit 4 scan line drive circuit 5 pixel electrode 6 capacity control TFT 11 signal line 12 scan line L1 auxiliary capacity line L2 capacity control line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/786 H01L 29/78 612Z 21/336 614 F Term (Reference) 2H092 GA12 JA24 JB42 JB62 JB67 JB69 NA01 NA26 2H093 NA16 NA51 NC34 NC35 NC40 NC90 ND06 ND39 ND60 NH16 5C006 AC25 AF51 BB16 BC02 BC03 BC06 FA18 FA26 FA36 FA47 FA54 FA56 5C080 AA10 BB05 DD01 DD26 FF12 JJ02 JJ03 JJ06 5F110 AA09 AA30 BB01 DD02 GG02 NN02

Claims (3)

[Claims] 1. A display device comprising a plurality of switching elements provided near each intersection of a signal line and a scanning line, wherein the charge is connected to a current path passing through the switching element and corresponds to a signal line voltage. And a switching circuit for switching whether or not to interrupt the current path between each end of each of the first and second capacitors. apparatus. 2. The switching circuit according to claim 1, wherein the switching circuit is turned on only when a driving frequency of the switching element is equal to or lower than a predetermined frequency, and stores a charge corresponding to a voltage of the signal line in the corresponding second capacitor element. The display device according to claim 1, wherein: 3. An array substrate having a plurality of switching elements disposed near each intersection of a signal line and a scanning line, and a counter substrate disposed to face the array substrate with a liquid crystal material interposed therebetween. In the liquid crystal display device, the array substrate is connected on a current path passing through the switching element, and first and second capacitor elements that accumulate charges according to a signal line voltage; and a driving frequency of the switching element is predetermined. When the driving frequency is lower than the predetermined frequency, the current path between one ends of the first and second capacitor elements is cut off. A switching circuit for conducting the current path between one ends of the elements.