JPH10228031A - Thin film transistor array substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the thin film transistor(TFT) array substrate which is reducible in the capacity formed by a drain electrode and a gate wire and therefore made small in hold capacity, and improved in aperture rate. SOLUTION: This TFT array substrate has a wire part, connecting a source electrode 9 of a TFT from a source wire 4, formed partially or entire on a gate wire 3, the source electrode 9 of the TFT is so formed as to form a channel shape together with part of the source wire 4, and the drain electrode 7 of the TFT is formed while surrounded with the source electrode 9; and the drain electrode 7 and a pixel electrode 6 are connected in the corresponding pixel and a space which is large enough to disconnect the drain electrode 7 and pixel electrode 6 by a laser is left at the periphery of the drain wire 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor array substrate used for a matrix type display device.

[0002]

2. Description of the Related Art Generally, a matrix type display device comprises a thin film transistor array substrate (hereinafter, referred to as a TFT array substrate) provided with thin film transistors (hereinafter, referred to as TFTs) and a counter substrate provided with a color filter, a black matrix, and the like. A display material such as a liquid crystal is sandwiched between two substrates, and a voltage is selectively applied to the display material. In the TFT array substrate, pixels are arranged in a matrix as shown in the equivalent circuit of FIG.

FIG. 2 is a diagram showing an equivalent circuit of a conventional TFT array substrate. In the figure, G1, G2, and G3 are scanning signal lines, S1, S2, and S3 are video signal lines, Cs1 and Cs.
s2 and Cs3 are Cs wirings for forming a storage capacitor. 1 denotes scanning signal lines G1, G2, G3 and video signal lines S1, S2,
The TFT 2 disposed at the intersection of S3 is a storage capacitor (hereinafter referred to as Cs capacitance) disposed between the TFT 1 and the Cs wirings Cs1, Cs2, Cs3. FIG. 3 shows a conventional TFT
FIG. 3 is a diagram showing pixels on an array substrate. In the figure, 3 is a gate wiring which is a scanning signal line, 4 is a source wiring which is a video signal line, 5 is a Cs wiring for forming a storage capacitor, 6 is a pixel electrode formed of a transparent electrode such as ITO, and 7 is a drain. electrode,
8 is amorphous silicon and 9 is a source electrode. A TFT is formed by the gate wiring 3, the amorphous silicon 8, the drain electrode 7, and the source electrode 9. Reference numeral 10 denotes a wiring connecting the source wiring 4 and the source electrode 9 of the TFT, and has a space for cutting with a laser.

In the conventional TFT array substrate configured as described above, the TFT 1 functions as a switching element to control charging and discharging of the pixel electrode 6. The TFT 1 is turned on and off by using the scanning signal lines G1 to G3 as gate electrodes.
carry out. The pixel electrode 6 is connected to the video signal lines S1 to S3 via the TFT1, and the amount of charge charged in the pixel electrode 6 changes depending on the level of the video signal, and the potential of the pixel electrode 6 is set. You. The amount of change in the liquid crystal changes according to the voltage between the pixel electrode 6 and the counter electrode, and the amount of light transmitted from the back surface changes. Therefore, by controlling the signal levels of the video signal lines S1 to S3, the optical signal change is controlled and displayed as a video. To improve the quality of the video,
It is necessary to minimize variations in pixel potential due to changes in signal levels of the video signal lines S1 to S3 and the like, and the total capacitance of pixels is increased by providing a Cs capacitor 2 in the pixel electrode. The Cs capacitance 2 is a Cs wiring Cs1 having the same potential as the counter electrode.
To Cs3 and a pixel electrode. In such a conventional TFT array substrate, when a leak source exists between the pixel electrode 6 and another wiring due to foreign matter or the like, the charged electric charge is lost, and the pixel characteristic is abnormal, the pixel electrode 6 is removed. The TFT portion is separated from the source wiring 8 using a laser. This cutting is performed, as shown in FIG. 3, in the adjacent pixels, the source wiring 4 and the source electrode 9 of the TFT.
Are provided, and a space for cutting by laser is provided.

[0005]

[Problems to be solved by the invention]

(1) In the conventional TFT array substrate, one pixel electrode 6
In the case where the pixel electrode 6 is separated from the source wiring 4 when the pixel electrode 6 is separated from the source wiring 4, a space for cutting is required in the adjacent pixel. Wiring 5 and pixel electrode 6
Will be laid out avoiding this space,
The Cs wiring 5 and the pixel electrode 6 were bent as shown in FIG. Therefore, the length of the Cs wiring 5 is longer than that of the straight line, which causes an increase in resistance. Also,
The pixel electrode 6 could not be laid out sufficiently close to the source wiring 4, which was one of the causes for lowering the aperture ratio.

(2) In the TFT portion, the source contact portion and the drain contact portion are arranged in parallel on the amorphous silicon 8 as shown in FIG. ,
The same length is required, which is a potential cause of an increase in the capacitance Cgd formed by the drain contact portion and the gate wiring 3. Due to the presence of the capacitance Cgd,
When the signal of the gate line 3 changes, the potential of the pixel electrode 6 changes due to the coupling by the capacitance Cgd. This fluctuation amount increases as the capacitance Cgd increases. To reduce the fluctuation amount, it is necessary to increase the Cs capacitance.
There is a problem that the s-wiring 5 must be increased, and therefore the aperture ratio decreases.

The present invention has been made to solve such a conventional problem, and provides a pixel pattern layout that reduces the resistance of a storage capacitor line and the capacitance formed by a gate line and a drain electrode. , High aperture ratio T
It is intended to obtain an FT array substrate.

[0008]

In a thin film transistor array substrate according to the present invention, a source electrode formed on a gate wiring and connected to a source wiring and having at least a portion parallel to the source wiring; A drain electrode which is disposed between a portion of the source electrode parallel to the source wiring and a part of which is formed on the gate wiring;
A drain wiring is provided which connects the drain electrode and the pixel electrode and has a part which can be cut.
The drain electrode is arranged in parallel with the source wiring. The drain electrode is surrounded by a source electrode and a source wiring arranged in parallel with the drain electrode and a source electrode connecting the source electrode and the source wiring.

Further, the width of the drain wiring is larger than the sum of the opposing intervals of the drain electrode, the source wiring parallel thereto and the source electrode. Further, no pixel electrode is arranged around the cuttable portion of the drain wiring. Further, a storage capacitor wiring is provided in parallel with the gate wiring and partially formed so as to overlap the pixel electrode via the insulating film. Furthermore, the storage capacitor wiring is formed linearly.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows Embodiment 1 of the present invention.
This will be described with reference to FIG. FIG. 1 is a diagram showing pixels on a TFT array substrate according to Embodiment 1 of the present invention. In the figure, reference numerals 3 to 9 are the same as those of the above-described conventional apparatus, and the description thereof is omitted. Reference numeral 11 denotes a drain wiring connecting the drain electrode 7 and the pixel electrode 6, and has a space that can be cut by laser. In FIG. 1, a part or the whole of a wiring part connecting the source wiring 4 and the source electrode 9 of the TFT is formed in a U-shape or a U-shape together with a part of the source wiring 4 on the gate wiring 3. The source electrode 9 of the TFT
To form The drain electrode 7 of the TFT is a source electrode 9
, And the drain electrode 7 and the pixel electrode 6 are connected by the drain wiring 11 arranged in the own pixel. The width of the drain wiring 11 is larger than the channel width of the TFT, that is, the sum of the drain electrode and the source wiring parallel to the drain electrode and the opposing intervals of the source electrode.
1 has a space where the drain electrode 7 and the pixel electrode 6 can be cut by laser.

In the TFT array substrate configured as described above, when a leak source exists between the pixel electrode 6 and another wiring due to a foreign substance or the like, the charged charge is lost, and the characteristics of the pixel are abnormal. Cuts the drain wiring 11 with a laser to separate the pixel. Further, the overlapping portion between the drain electrode 7 and the gate wiring 3 is small, and therefore, the capacitance Cgd formed by the drain contact part and the gate wiring 3 can be reduced. Therefore, the Cs capacitance may be reduced. The aperture ratio can be increased. Further, the Cs wiring 5 can be formed in a straight line, and the wiring width may be small in order to obtain the same wiring resistance as in the related art, so that the aperture ratio can be improved. Thus, T
Since the aperture ratio of the pixels in the FT array substrate can be improved, there is an effect that power consumption can be reduced in a matrix display device using the TFT array substrate.

[0012]

Since the present invention is configured as described above, it has the following effects. A source electrode formed over the gate wiring and connected to the source wiring and having at least a portion parallel to the source wiring, and disposed between the source wiring and a portion of the source electrode parallel to the source wiring, and part of the source electrode is parallel to the source wiring. A drain electrode formed on the gate wiring, a drain wiring connecting the drain electrode and the pixel electrode and partially having a cutable portion are provided, and the drain electrode is arranged between the source wiring and the source electrode. In addition, the channel width can be secured with a short drain electrode length, and the capacity formed by the drain electrode and the gate wiring can be reduced. Therefore, the storage capacity can be reduced, the aperture ratio can be improved, and a cuttable portion can be obtained. Further, since the drain electrode is arranged in parallel with the source wiring, the capacity formed by the drain electrode and the gate wiring can be further reduced, and the storage capacity can be reduced.

Further, the width of the drain wiring is sufficiently smaller than the sum of the opposing intervals of the drain electrode, the source wiring parallel to the drain electrode, and the source electrode, so that a cutting space can be secured. Further, since no pixel electrode is arranged around the cuttable portion of the drain wiring, a cutting space can be secured. Furthermore, the storage capacitor wiring is
Since it is formed in a straight line, the width of the storage capacitor wiring can be reduced, so that the aperture ratio can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing pixels on a TFT array substrate according to an embodiment of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a conventional TFT array substrate.

FIG. 3 is a diagram showing pixels on a conventional TFT array substrate.

[Explanation of symbols]

1 thin film transistor (TFT), 2 storage capacitor (Cs
Capacity), 3 gate wires, 4 source wires, 5 Cs wires, 6 pixel electrodes, 7 drain electrodes, 9 source electrodes, 11 drain wires.

Claims (7)

[Claims] A thin film transistor array substrate having thin film transistors disposed at intersections of a plurality of source wirings and a plurality of gate wirings, and a pixel electrode connected to the thin film transistors; A source electrode connected to the source wiring and having at least a portion parallel to the source wiring, a drain electrode disposed between the source wiring and the source electrode parallel to the source wiring and partially formed on the gate wiring; A thin-film transistor array substrate, comprising: a drain wiring connecting the drain electrode and the pixel electrode and having a part that can be cut. 2. The thin film transistor array substrate according to claim 1, wherein the drain electrode is arranged in parallel with the source wiring. 3. The thin film transistor array according to claim 1, wherein the drain electrode is surrounded by a source electrode and a source wiring disposed in parallel with the drain electrode and a source electrode connecting the source electrode and the source wiring. substrate. 4. The method according to claim 1, wherein the width of the drain wiring is larger than the sum of the distance between the drain electrode, the source wiring parallel to the drain electrode, and the facing electrode. Thin film transistor array substrate. 5. Around the cuttable portion of the drain wiring,
2. A pixel electrode is not arranged.
The thin film transistor array substrate according to claim 4. 6. The storage capacitor wiring according to claim 1, further comprising a storage capacitor wiring arranged in parallel with the gate wiring and partially formed so as to overlap the pixel electrode via an insulating film. 9. The thin film transistor array substrate according to claim 1. 7. The thin film transistor array substrate according to claim 6, wherein the storage capacitor wiring is formed in a straight line.