JP2002290921A - Signal processing system, signal output device, signal receiver, signal processing method, signal output method and signal receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reproduce audio data with high definition by flow control by performing flow control and to surely synchronize audio data and video data in the case of simultaneously processing at least encoded audio data and encoded video data. SOLUTION: According to a command for flow control from an amplifier 2 being a signal receiver, the host controller 25 of a disk player controls a PLL circuit 241 to change the frequencies of a counting clock signal to be supplied to an STC counter 242 and ACK(Audio Clock) being a clock signal to be supplied to the output circuit 83 of audio decoder 18. The output speed of the audio data is made to correspond to a request from the signal receiver with ACK, and the video data and the audio data are synchronized based on the count value of the STC counter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing system and a signal processing method for simultaneously processing an encoded digital audio signal and an encoded digital video signal so as to reproduce audio signals with high quality. The present invention relates to an output device, a signal receiving device, a signal processing method, a signal output method, and a signal receiving method.

[0002]

2. Description of the Related Art It has been considered to construct an in-home network system (home network system) by organically connecting audio equipment and audio / visual equipment (AV equipment) installed in a home. By forming a home network system in this way, each device can be integrated and managed, and a good listening environment for audio (voice) and a good viewing environment for audio (voice) and visual (video) can be obtained. Can be arranged in the home.

[0003] In this case, the audio equipment constituting the home network system is a CD (Compac).
t Disk) player, MD (Mini Disk)
There are various devices such as players, MD recording / reproducing devices, radio tuners, audio amplifiers, and the AV devices include television receivers (monitor receivers) and DVDs.
(Digital Versatile Disk) playback devices, recording and playback devices, digital television broadcast receivers, and personal computers.

[0004] When a home network system is constructed, it is necessary to transmit and receive control signals such as various commands in addition to a target main signal such as an audio signal between devices. As an interface for connecting each device, for example, IEEE (In)
state of Electric and
Electronics Engines) 139
Digital interfaces of four standards are attracting attention.

In this case, generally, an audio amplifier and
When a device such as a CD player is connected via a digital interface and an audio amplifier receives and reproduces a digital audio signal (digital audio data) from the device such as a CD player, the clock of the device such as a CD player as a transmitting device is used. Signal jitter,
In some cases, a jitter of a clock signal of an audio amplifier as a receiving device may be shifted, which causes deterioration of sound quality.

In order to solve this problem and reproduce audio signals with high quality, a method called flow control can be used in the above-mentioned digital interface of the IEEE 1394 standard. . FIG. 11 is a diagram for explaining the flow control, and schematically shows the flow control.

As shown in FIG. 11, a transmitting device 1 for transmitting a digital audio signal such as a CD player, for example,
00 and a receiving device 200 such as an audio amplifier for receiving a digital audio signal from the transmitting device 100.
Are connected by a digital interface of the IEEE1394 standard.

The receiving device 200 includes a buffer memory 201 for temporarily storing a digital audio signal from the transmitting device 100, and a signal processing unit 202 for reading out the digital audio signal stored in the buffer memory 201 and processing the digital audio signal. ing. The transmitting device 100 transmits a digital audio signal using the clock of the transmitting device itself.

The receiving device 200 writes the digital audio signal from the transmitting device 100 to the buffer 201 according to the clock signal from the transmitting device 100, but reads the digital audio signal from the buffer 201 according to the clock of the receiving device 200 itself. Use signals. In this case, the clock signal of the transmitting device 100 and the receiving device 200
If the clock signal is of exactly the same frequency,
The buffer 201 does not cause overflow or underflow. However, if they are different, buffer 2
01 will go to overflow or underflow.

For this reason, in the receiving device 200, the remaining amount of the buffer 201 is constantly monitored, and if it is close to the underflow state, the data transfer to the transmitting device 100 is performed 1% earlier than usual. Send a command requesting that it be performed. According to this command, the transmitting device 100 transfers the digital audio signal to the receiving device 200 at a speed 1% faster than usual.

[0011] The receiving device 200 is
When the buffer 201 becomes close to the overflow state due to the relationship between the clock signal and the clock signal between the receiving device 200 and the receiving device 200, the data transfer to the transmitting device 100 is performed at 1% of the normal state.
Send a command requesting a slower speed. In accordance with this command, the transmitting device 100 transmits the digital audio signal at a speed 1% slower than normal.
Transfer to 0.

In any case, when the storage amount of the digital audio signal in the buffer 201 becomes appropriate, the receiving device 200 instructs the transmitting device 100 to normally transfer data. Send the requested command. In response to this, the transmitting device 100 returns the output speed of the digital audio signal to normal.

In the receiving device 200, a signal processing unit 202 is used by using the clock signal of the receiving device 200.
Reads a digital audio signal from the buffer 201, processes the digital audio signal, and outputs the processed signal. As a result, the jitter can be removed, and the audio can be reproduced with high quality without interruption.

As described above, in the case of a digital audio signal, a jitterless reproduction for reproducing a high-quality audio signal by removing jitter of a clock signal between a transmitting device and a receiving device by performing so-called flow control. Have been able to.

[0015]

By the way, the above-mentioned flow control method is applied to a CDDA (CD dedicated to music).
This is an effective method for a recording medium in which a stream of only audio (sound) such as a DVD or MD is recorded without being multiplexed, and a disk medium in which only the audio needs to be reproduced.

However, as described above, the home network system includes a television receiver (monitor receiver), a DVD reproducing device and a recording / reproducing device, a digital television broadcasting receiver, and a personal computer. AV that processes signals (video data)
Equipment is also connected.

[0017] A reproduction device or a reception device for a stream in which an audio signal such as data recorded on a DVD-Video or a digital broadcast signal and a video signal are multiplexed, or an audio signal and a video signal are simultaneously synchronized and synchronized. In playback devices for playback, etc., the IEEE
The flow control method provided in the digital interface of the E1394 standard cannot be used.

That is, even if flow control is performed on an audio signal in order to reproduce the audio signal with high quality, no consideration is given to a video signal that needs to be reproduced in synchronization with the audio signal. The synchronization between the audio signal and the video signal is shifted.

Therefore, if flow control is performed on an audio signal when there is a video signal to be reproduced at the same time, the relationship between the audio signal and the video signal at the time of authoring is lost, and the reproduced sound by the audio signal and the reproduction by the video signal are lost. The image does not match,
It becomes unnatural reproduction.

However, in a home network system including AV equipment, for example, a television receiver and an audio amplifier are connected to a DVD reproduction apparatus, and a digital broadcast receiver is connected to a DVD reproduction apparatus. A case where a television receiver and an audio amplifier are connected may be considered.

In this case, an AV stream in which an audio signal and a video signal are multiplexed is supplied to a television receiver, and only an audio signal is supplied to an audio amplifier. The video by the video signal of the stream is reproduced, and the audio amplifier reproduces the audio by the audio signal with high quality.
In addition, it is considered that the case where it is desired to accurately synchronize the reproduction of the video signal and the audio signal with one another naturally occurs. Particularly, when software such as a movie is reproduced, such necessity is increased.

In view of the above, the present invention provides a flow control for an audio signal so that it can be reproduced with high quality when at least an encoded audio signal and an encoded video signal are simultaneously processed. An object of the present invention is to provide a signal processing system, a signal output device, a signal receiving device, a signal processing method, a signal output method, and a signal receiving method that can reliably synchronize an audio signal and a video signal. I do.

[0023]

According to a first aspect of the present invention, there is provided a signal processing system for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal. A signal processing system comprising: a signal output device; and a signal reception device that receives at least an audio signal output from the signal output device, wherein the signal reception device decodes at least the audio from the signal output device. Receiving means for receiving a signal, a memory for storing the audio signal received by the receiving means, and reading and processing the audio signal stored in the memory based on the clock signal of the own device. Audio signal processing means for monitoring the remaining capacity of the memory and outputting the audio signal in accordance with the remaining capacity. Instruction information forming means for forming instruction information related to, and transmitting means for transmitting the instruction information formed by the instruction information forming means to the signal output device, the signal output device, the signal output device from the signal receiving device Instruction information receiving means for receiving the instruction information relating to the output speed of the audio signal, and a clock signal generating means for generating a clock signal of a desired type at a frequency corresponding to the instruction information received through the instruction information receiving means; An audio signal decoding unit that decodes the encoded audio signal and that can change an output speed of the decoded audio signal according to an output clock signal generated by the clock signal generation unit according to the instruction information, Counting clock signal generated by the clock signal generating means according to the instruction information Based on,
Calculating means for calculating a count value for controlling a decoding process of the coded digital video signal; and means for decoding the coded digital video signal, and a decoding timing based on the count value from the calculating means. Controllable video signal decoding means, audio signal transmitting means for transmitting the audio signal decoded by the audio signal decoding means to the signal receiving device, and video for transmitting the video signal decoded by the video signal decoding means Signal transmission means.

According to the signal processing system of the first aspect of the present invention, the signal receiving device monitors the remaining amount of the memory for temporarily storing the audio signal from the signal output device, and when overflowing is likely to occur, Instruction information for reducing the output speed of the audio signal from the signal output device,
In addition, when underflow is likely to occur, instruction information for increasing the output speed of the audio signal from the signal output device is provided. When the remaining amount of the memory becomes appropriate, the signal from the signal output device is provided. Instruction information for setting the output speed of the audio signal to normal is formed and transmitted to the signal output device.

In the signal output device, at least an output clock signal and a count clock signal are generated by the clock signal generation means in accordance with the instruction information from the signal receiving device. And the audio signal decoding means,
The decoded audio signal is output at an output speed according to the output clock signal from the lock signal generating means, and is transmitted to the signal receiving device through the audio signal transmitting means. Therefore, the decoded audio signal is transmitted from the signal output device to the signal receiving device at an output speed according to the instruction from the signal receiving device.

On the other hand, the encoded video signal is decoded by the video signal decoding means by controlling its decoding timing by the count value counted based on the count clock signal. The count value provides a so-called reference time, and allows synchronization according to instructions from the signal receiving device so that the decoded audio signal is synchronized with the decoded video signal. To be.

Thus, for the audio signal,
The so-called flow control can be realized, and the synchronization between the audio signal and the video signal to be reproduced simultaneously with the audio signal can be surely synchronized. As a result, the flow control can be applied not only to audio equipment but also to audio-visual equipment.

According to a second aspect of the present invention, there is provided a signal processing apparatus for processing and outputting at least an encoded audio signal and an encoded video signal simultaneously, and an output from the signal output apparatus. A signal receiving system for receiving at least an audio signal, wherein the signal receiving device receives a decoded audio signal from the signal output device, and the receiving device A memory for storing the received audio signal, an audio signal processing means for reading out the audio signal stored in the memory based on a clock signal of the own device and processing the audio signal, and a remaining amount of the memory Instruction information forming means for monitoring the output signal and forming instruction information on the output speed of the audio signal according to the remaining amount; Transmitting means for transmitting the instruction information formed by the instruction information forming means to the signal output device, wherein the signal output device receives the instruction information on the output speed of the audio signal from the signal receiving device. Instruction information receiving means, a clock signal of a desired type, a clock signal generating means for generating a clock signal at a frequency corresponding to the instruction information received through the instruction receiving means, and the encoded audio signal is decoded and decoded. An audio signal decoding unit that can change an output speed of an audio signal according to the instruction information; and the encoded digital video signal based on a count clock signal generated by the clock signal generation unit according to the instruction information. Calculating means for calculating a count value for controlling a decoding process of the encoded digital data; Means for decoding a video signal, a video signal decoding means capable of controlling a decoding timing based on the count value from the calculation means, and an audio signal decoded by the audio signal decoding means to the signal receiving device. An audio signal transmitting means for transmitting, and a video signal transmitting means for transmitting a video signal decoded by the video signal decoding means are provided.

According to the signal processing system of the second aspect of the present invention, the signal receiving device monitors the remaining amount of the memory for temporarily storing the audio signal from the signal output device, and when overflowing is likely to occur, Instruction information for reducing the output speed of the audio signal from the signal output device,
In addition, when underflow is likely to occur, instruction information for increasing the output speed of the audio signal from the signal output device is provided. When the remaining amount of the memory becomes appropriate, the signal from the signal output device is provided. Instruction information for setting the output speed of the audio signal to normal is formed and transmitted to the signal output device.

In the signal output device, at least a count clock signal is generated by the clock signal generating means in accordance with the instruction information from the signal receiving device. Then, the audio signal decoding unit outputs the decoded audio signal at an output speed according to the instruction information from the signal receiving device, and this is transmitted to the signal receiving device through the audio signal transmitting unit. Therefore, the decoded audio signal is transmitted from the signal output device to the signal receiving device at an output speed according to the instruction from the signal receiving device.

On the other hand, the coded video signal is decoded by the video signal decoding means by controlling the decoding timing according to the count value counted based on the count clock signal. The count value provides a so-called reference time, and allows synchronization according to instructions from the signal receiving device so that the decoded audio signal is synchronized with the decoded video signal. To be.

Thus, for the audio signal,
The so-called flow control can be realized, and the synchronization between the audio signal and the video signal to be reproduced simultaneously with the audio signal can be surely synchronized. As a result, the flow control can be applied not only to audio equipment but also to audio-visual equipment.

A signal processing system according to a third aspect of the present invention is the signal processing system according to the first or second aspect, wherein the signal output device includes an encoded audio signal and an encoded video signal. Reading means for reading the multiplexed signal from a recording medium on which a multiplexed signal obtained by multiplexing the multiplexed signal is recorded, demodulating means for demodulating the multiplexed signal read by the reading means, and demodulation by the demodulating means. Separating the coded audio signal and the coded video signal from the multiplexed signal, supplying the coded audio signal to the audio signal decoding means, and converting the coded video signal into the video signal decoding means. And a signal separating means for supplying the signal to the signal generator.

According to the signal processing system of the third aspect of the present invention, the signal output device has a configuration as a reproducing device for a recording medium on which an encoded audio signal and an encoded video signal are recorded. Is done.

Thus, even in a reproducing apparatus for simultaneously processing and outputting an encoded audio signal and an encoded video signal, so-called flow control is performed on the audio signal so that high-quality reproduction can be performed. In addition, it is possible to reliably synchronize the audio signal with the video signal processed simultaneously with the audio signal.

A signal output device according to a fourth aspect of the present invention is the signal processing system according to the first or second aspect, wherein the signal output device includes an encoded audio signal and an encoded video signal. Receiving means for receiving a multiplexed signal obtained by multiplexing the signals, demodulating means for demodulating the multiplexed signal received by the receiving means, and encoding the coded audio signal from the multiplexed signal demodulated by the demodulating means. A signal separating unit that separates the encoded video signal from the encoded video signal, supplies the encoded audio signal to the audio signal decoding unit, and supplies the encoded video signal to the video signal decoding unit. Features.

According to the signal processing system of the fourth aspect of the present invention, the signal output device has a configuration as a receiving device for a digital broadcast signal having an encoded audio signal and an encoded video signal. Is done.

Thus, even in a receiving device that simultaneously processes and outputs an encoded audio signal and an encoded video signal, so-called flow control is performed on the audio signal so that high-quality reproduction can be performed. In addition, it is possible to reliably synchronize the audio signal with the video signal processed simultaneously with the audio signal.

A signal processing system according to a fifth aspect of the present invention is the signal processing system according to the first or second aspect, wherein, in the signal output device, the clock signal generating means is provided for: Generating a clock signal to be generated at a frequency that is originally required, a frequency that is several percent lower than the originally required frequency, and a frequency that is several percent higher than the originally required frequency, according to the instruction information. The audio decoding means and the calculating means have a processing capability at least several percent higher than the minimum required processing capability, and the processing speed can be changed within the range of the processing capability. There is a feature.

According to the signal processing system of the fifth aspect of the present invention, the clock signal generating means includes a clock signal having a frequency several% lower than the predetermined frequency, a clock signal having the predetermined frequency, A clock signal having a frequency several% higher than the determined frequency can be switched and generated according to instruction information from the signal receiving device.

In the audio decoding means, the output speed of the audio signal is changed within the range of its processing capability by the output clock signal generated by switching the frequency from the clock signal generation means. The calculating means calculates a count value for controlling the decoding timing of the encoded video signal based on the counting clock signal generated by switching the frequency from the clock signal generating means. Using this count value, the decoding timing of the video signal is controlled by the video signal decoding means, and the video signal is decoded.

As described above, within a predetermined range, the output speed of the decoded audio signal and the decoding timing of the video signal can be adjusted in accordance with the instruction information from the signal receiving device, so that the audio signal height can be adjusted. Quality reproduction,
Synchronization between the audio signal and the video signal can be reliably performed.

A signal processing system according to a sixth aspect of the present invention is the signal processing system according to the third aspect, wherein the signal output device includes:
The demodulation means and the signal separation means have a processing capacity at least several percent higher than the minimum required processing capacity, and the reading means, the demodulation means, and the signal separation means are provided with the clock signal. It is characterized in that the processing speed can be changed according to the clock signal from the generating means.

According to the signal processing system of the sixth aspect, when the signal output device has a function as a reproducing device, the means for realizing the function as the reproducing device also sets the processing speed to a signal. The control can be performed based on the instruction information from the receiving device.

Thus, even when the signal output device is a reproducing device, the output speed of the decoded audio signal and the decoding timing of the video signal can be adjusted according to the instruction information from the signal receiving device. High-quality reproduction of an audio signal and synchronization of an audio signal and a video signal can be reliably performed.

According to a seventh aspect of the present invention, in the signal processing system according to the fourth aspect, in the signal output device, the receiving unit, the demodulating unit, and the signal separating unit The means has a processing capacity at least several percent higher than the minimum required processing capacity, and the receiving means, the demodulating means, and the signal separating means respond to a clock signal from the clock signal generating means. hand,
The processing speed can be changed.

According to the signal processing system of the present invention, when the signal output device has a function as a receiving device for digital broadcasting or the like, the means for realizing the function as the receiving device is also provided. The processing speed can be controlled based on the instruction information from the signal receiving device.

Thus, even when the signal output device is a receiving device, the output speed of the decoded audio signal and the decoding timing of the video signal can be adjusted according to the instruction information from the signal receiving device. High-quality reproduction of an audio signal and synchronization of an audio signal and a video signal can be reliably performed.

An eighth aspect of the present invention is the signal processing system according to the fifth, sixth or seventh aspect of the present invention, wherein the signal processing system comprises several% of the frequency.
And the ratio of several percent of the processing capacity is approximately 1%.

According to the signal processing system of the present invention, the frequency range that can be changed is within a range of approximately ± 1% of the reference frequency, and the processing that can be changed is performed. The range of performance is approximately ±
It is made to be within the range of 1%.

Thus, high-quality reproduction of an audio signal and synchronization between an audio signal and a video signal can be reliably performed without imposing a load on both the signal output device and the signal receiving device. You.

The signal processing system according to the ninth aspect of the present invention provides the signal processing system according to the first, second, third, fourth, and fourth aspects.
9. The signal processing system according to claim 5, 6, 7, or 8, wherein a receiving unit and a transmitting unit of the signal receiving device, and an audio signal transmitting unit and a receiving unit of the signal output device. Are connected by a digital interface.

In the signal processing system according to the ninth aspect, a main signal such as an audio signal and a video signal, and control information such as instruction information are transmitted and received by a digital interface. As a result, the signal output device and the signal receiving device are reliably connected, and high-quality reproduction of the audio signal and synchronization of the audio signal and the video signal can be reliably performed.

A signal processing system according to a tenth aspect of the present invention is the signal processing system according to the ninth aspect, wherein the digital interface is an IEEE 139.
It is characterized by four standards.

According to the signal processing system of the tenth aspect of the present invention, the digital interface for connecting the signal output device and the signal receiving device conforms to the IEEE 1394 standard. By using the digital interface of the IEEE 1394 standard, even in the case of using an audio-visual device that also performs video signal processing, high-quality reproduction of an audio signal and synchronization between an audio signal and a video signal can be reliably and relatively achieved. It can be easily realized.

[0056]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a signal processing system, a signal output device, a signal receiving device, a signal processing method, a signal output method and a signal receiving method according to the present invention.

[Home Network System]
FIG. 1 illustrates an example of a home network system to which an embodiment of a signal processing system, a signal output device, a signal reception device, a signal processing method, a signal output method, and a signal reception method according to the present invention is applied. It is a block diagram.

As shown in FIG. 1, in the home network system according to this embodiment, a disk reproducing device 1 and an amplifier device 3 are connected by an IEEE 1394 standard digital bus (hereinafter, referred to as an IEEE 1394 bus) 2, and an amplifier is provided. The device 3 and the monitor receiver 5 are connected to the IEEE 1394 bus 4
It is formed by connecting with.

That is, in this embodiment, a home network system is constructed by connecting the disk reproducing device 1, the amplifier device 3, and the monitor receiver 5 by a so-called daisy chain method by an IEEE 1394 bus. I have. As shown in FIG. 1, the amplifier device 3 includes speakers SPL and SPL of two channels on the left and right.
PR is connected.

In this embodiment, the disc reproducing apparatus 1 is a reproducing apparatus for a DVD which is a disc recording medium, and has a DVD-Audio format, a DVD
-Video format, DVD-VR (Video
Recording audio data (encoded audio signal) and encoded video data (encoded video signal) recorded on a DVD of a recording (Recording) format or the like, and decoded, and output to a subsequent device. Is what you do. That is, the disc reproducing apparatus 1 is the one to which the signal output device and the signal output method according to the present invention are applied.

In this case, the disc reproducing apparatus 1 converts the decoded digital audio data and digital video data into streams of several formats according to the IEEE 1 standard.
The digital audio data can be transmitted to the amplifier device 3 and the monitor receiver 5 through the 394 bus, and the decoded digital audio data and digital video data can be converted into analog signals and output.

The analog video data from the disk reproducing device 1 is supplied to, for example, an analog television monitor or a VTR (video tape recorder) through the analog video interface 6. The analog audio data is supplied to the analog audio interface 7.
Through a speaker.

In this embodiment, the amplifier device 3 has a function as a so-called audio amplifier, receives digital audio data from the disk reproducing device 1, converts it into analog audio data, and Performs various adjustment processes such as sound quality and volume, and sends the adjusted analog audio data to the speaker S.
By supplying the signal to the PL and SPR, a sound corresponding to the digital audio data from the disk reproducing device 1 is emitted. That is, the amplifier device 3
Is a signal receiving apparatus and a signal receiving method according to this embodiment.

The digital video data and digital audio data from the disk reproducing device 1 can be supplied to the monitor receiver 5 via the amplifier device 3 and the IEEE1394 bus 4.

In the home network system according to this embodiment, the signal processing system and the signal processing method according to the present invention are realized by the disk reproducing device 1 and the amplifier device 3. In other words, in the home network system according to the present embodiment, between the disk reproducing device 1 and the amplifier device 3, the IEEE
A so-called flow control for digital audio data provided in a digital interface of the E1394 standard can be used.

Therefore, the amplifier device 3 is connected to the IEEE 1
The digital audio data output from the disc reproducing apparatus 1 via the 394 bus 2 is temporarily stored in its own buffer memory, and is read out and processed in accordance with the clock signal of the own apparatus, so that the digital audio data has a high level. High quality reproduction (jitterless reproduction) is realized.

In this case, the amplifier device 3 constantly monitors the remaining amount of the buffer memory in which the digital audio data is temporarily stored, and outputs the digital audio data from the disk reproducing device 1 at a speed corresponding to the remaining amount. Thus, the disc reproducing apparatus 1 can be controlled.

The disc reproducing apparatus 1 can adjust the output speed of the digital audio data from its own apparatus in accordance with the control signal from the amplifier apparatus 3. However, the disc reproducing apparatus 1 processes digital video data as well as digital video data, as described above.

Therefore, when the flow control is performed on the digital audio data, the digital audio data and the digital video data may be out of synchronization. Thus, even if the flow control is performed, the synchronization between the audio data and the video data can be surely synchronized.

As described above, in the signal processing system formed by the disk reproducing device 1 and the amplifier device 3,
It is possible to reproduce audio data with high quality, and also to reliably synchronize digital audio data and digital video data to be processed simultaneously.

[Regarding Disc Reproducing Apparatus 1] FIG.
FIG. 2 is a block diagram for explaining the disk reproducing device 1 shown in FIG. 1 in more detail. In FIG.
Is a DVD in which digital audio data and digital video data are multiplexed and recorded in the DVD-Video format, for example.

The optical pickup 11 includes a laser light source, a beam splitter, an objective lens, a light receiving element (photodiode), and the like. The optical pickup 11 is
The disk 10 is irradiated with laser light, the reflected light of the laser light from the disk 10 is received, converted into an electric signal, and supplied to the RF circuit 12. The light reflected from the disk 10 changes according to the data recorded on the disk 10.

The RF circuit 12 forms a reproduced RF signal from the signal from the optical pickup 11, performs waveform equalization and binarization processing to form reproduced data, and outputs the reproduced data to a front-end circuit (hereinafter referred to as FE). Circuit 13). Note that the RF circuit 12 also forms servo error signals such as a tracking error signal and a focus error signal.

Using these servo error signals, tracking error control, focus error control, and the like are performed, and a laser beam having a spot shape of an appropriate size is used to accurately track the data-recorded track on the disk 10. I can operate it.

In FIG. 2, for simplicity of description, a spindle motor for rotating the disk 10, a sled mechanism for moving the optical pickup 11 in the radial direction of the disk 10, and the position of the optical pickup 11 And in the direction perpendicular to
A description of a biaxial actuator for fine adjustment in the radial direction is omitted.

The FE circuit 13 performs processing such as demodulation and error correction of the reproduced data supplied thereto, and decrypts the processed reproduced data through the track buffer 14 into a decryption / data separation circuit (Decrypt & Demux) 1.
5 In this embodiment, the disk 1
0 is encoded digital audio data, encoded digital video data, and encoded sub-picture data (encoded sub-picture signal) are packetized and multiplexed. It is encrypted by the encryption method.

The decryption / data separation circuit 15 decrypts (decrypts) the encryption applied to the reproduced data supplied thereto, and converts it into various packets, that is, audio packets, video packets, and sub-picture packets. It separates and outputs the encoded data in each packet to each subsequent decoder.

That is, the encoded video data Vd in the video packet is supplied to the video decoder 16 and the encoded sub-picture data SP in the sub-picture packet is supplied.
Is supplied to a sub-picture decoder (hereinafter, referred to as an SP decoder) 17, and the encoded audio data Au in the audio packet is supplied to an audio decoder 18.

It should be noted that, when the multiplexed data is encoded by variable rate compression, the FE circuit 13
In some cases, the processing speed differs from that of the data separation circuit 15, but in order to absorb the difference in the processing speed, the FE circuit 1
3, a track buffer 14 is provided between the decryption circuit 3 and the decryption / data separation circuit 15.

As will be described later, the video decoder 16 temporarily stores the supplied video data in a video code buffer (Video Code Buffer), takes out the video data therefrom, performs a decoding process, and expands the decompressed video data. The data is supplied to a synthesis circuit (mixer) 19 at the subsequent stage.

The SP decoder 17 stores the supplied sub-picture data in a sub-picture code buffer (SubPicture Code), as described later.
Buffer), the sub-picture data is extracted therefrom, decoded, and the expanded SP signal is supplied to the synthesizing circuit 19. The sub-picture is used, for example, when displaying subtitles or displaying various messages in movie content.

The synthesizing circuit 19 synthesizes video data from the video decoder 16 and sub-picture data from the SP decoder 17 to form video data.
It is supplied to the encoder 21.

The NTSC encoder 20 has a synthesizing circuit 19
And converts it into an analog video signal (television signal) of the NTSC system or the PAL system. The analog video signal output from the NTSC encoder 20 is, as described above,
For example, the video signal is supplied to a television monitor, and is reproduced in the television monitor device, and an image corresponding to the analog video signal is displayed on a display screen of the monitor receiver.

On the other hand, the audio decoder 18 converts the supplied audio data into an audio code buffer (Audio Code Buf), as will be described later.
fer), audio data is taken out therefrom, and decoding processing is performed according to the audio format. The frequency of the expanded audio data is changed in accordance with, for example, an instruction from the host controller, and is supplied to the AV encoder 21, the D / A conversion circuit 22, and the digital I / F unit 13. You.

The AV encoder 21 re-encodes the video signal from the synthesizing circuit 19 and the audio data from the audio decoder 18 by MPEG-TS or the like, and forms AV data in which the video signal and audio data are multiplexed. I do. The formed AV data is supplied to a digital interface circuit (hereinafter, referred to as a digital I / F circuit) 23.

In the case of IEEE 1394, when an AV stream is not output and a stream of only audio data is supported, the AV encoder 21 is unnecessary. The digital I / F circuit 23 has an IE having a so-called link layer (Link layer) and a physical layer (PHY layer).
This is an EE1394 standard I / F circuit.

The digital I / F circuit 23 converts the audio data supplied from the audio decoder 18 into Aud
IEEE in the format of io & Music Protocol
E1394 Isochronous Packet (Isochr
(ie, isochronous packetization processing) such as an on-packet, and the like.
Send to 94 bus.

At the same time, the digital I / F circuit 23
The AV data supplied from the AV encoder 21 is
IEEE1394 in EG-TS Protocol format
Perform processing such as isochronous packet
Transmit to the IEEE 1394 bus.

Audio & Music Proto
The IEEE 1394 isochronous packet in the col format is, as shown in FIG.
And is reproduced by the amplifier device 3 as audio. Also, MPEG-TS Proto
The IEEE 1394 isochronous packet in the col format is received by the monitor receiver 5 connected to the IEEE 1394 bus, as shown in FIG. 1, and reproduced as video and audio.

The audio D / A converter 22
Converts the digital audio data from the audio decoder 18 into analog audio data and supplies it to a speaker, for example, so that it is reproduced as audio.

Further, the PLL / STC unit 24 includes a PLL (Phase Locked Loop) as described later.
p) Circuit and STC (System Time Clock)
k) a counter. The PLL circuit generates various clock signals to be supplied to each unit.
The C counter counts a reference time based on a clock signal from the PLL circuit. The reference time is used when adjusting the decoding timing of the encoded video data.

The host controller 25 controls each unit of the disc reproducing apparatus 1. Although not shown, a CPU (Central Processin) is used.
gUnit), ROM (Read Only Memo)
ry), RAM (Random Access Mem)
ory), EEPROM (Electrically
Erasable and Programmable
ROM) is a microcomputer formed by being connected via a CPU bus.

Although not shown, the host controller 25 has a key operation unit for receiving an instruction input from the user and an LCD (Liquid Crystals) for notifying various guidance messages and error messages.
tal Display) is connected.

[Regarding Amplifier Device 3] FIG. 3 is a block diagram for explaining the amplifier device 3 shown in FIG. 1 in more detail. As shown in FIG. 3, the amplifier device 3 includes a digital I / F circuit 31, a buffer memory 32, a signal processing circuit 33, a PLL circuit 34, a controller 35, and an operation unit 3.
6. A display unit 37 is provided.

The digital I / F circuit 31 is an IEEE13
Disc playback device 1 transmitted via 94 bus 2
Receive data from Then, the digital I / F circuit 31 converts the received data into the MPEG-TS Prot.
If the packet is an IEEE 1394 isochronous packet in the ocol format, the packet is transferred to the IEEE 1394 bus 4
The monitor is supplied to the monitor receiver 5 through.

The digital I / F circuit 31 converts the received data into Audio & Music Proto.
When the packet is an IEEE 1394 isochronous packet in the col format, the audio data included in the packet is supplied to the buffer memory 32, and the audio data is recorded in the buffer memory 32. in this case,
The recording of the audio data in the buffer memory 32 follows the clock of the disk reproducing device 1 which is the transmitting device.

As described above, the buffer memory 32 temporarily stores audio data from the disk reproducing device 1. Then, the signal processing circuit 33 transmits the P
Based on the clock signal from the LL circuit 34, the audio data temporarily stored in the buffer memory 32 is read out from the buffer memory 32, a predetermined signal processing is performed, and analog signals for driving the left and right two-channel speakers SPL and SPR are obtained. The audio data is formed and supplied to the corresponding speakers SPL and SPR. As a result, sound corresponding to the audio data from the disk reproducing device 1 is emitted from the speakers SPL and SPR.

Then, the controller 35 of the amplifier device 3 of this embodiment monitors the remaining amount of the buffer memory 32, and when the remaining amount of the buffer memory 32 becomes larger than a predetermined amount, stores the data in the buffer memory 32. Since the amount is in the overflow direction, instruction information (Slow command) for decreasing the output speed of the audio data is formed for the disc reproducing apparatus 1 and is transmitted to the digital I / F.
The circuit 31 transmits the data to the disk reproducing apparatus 1 through the IEEE1394 bus 2.

The controller 35 of the amplifier device 3
Monitors the remaining amount of the buffer memory 32, and when the remaining amount of the buffer memory 32 becomes smaller than a predetermined amount, the data storage amount of the buffer memory is moving in the underflow direction. On the other hand, instruction information (Fast command) for increasing the output speed of the audio data is formed, and this is transmitted to the digital I / F circuit 31, IE.
The data is transmitted to the disk reproducing device 1 through the EE1394 bus 2.

Further, the controller 35 of the amplifier device 3
Monitors the remaining amount of the buffer memory 32, and when the remaining amount of the buffer memory 32 reaches a predetermined amount, the data storage amount of the buffer memory becomes appropriate. Forming instruction information (Standard command) for setting the output speed of audio data to normal,
This is transmitted to the disk reproducing apparatus 1 through the digital I / F circuit 31 and the IEEE 1394 bus 2.

As described above, the amplifier device 3 of this embodiment temporarily fetches the audio data from the disk reproducing device 1 into its own buffer memory 32 and processes it in accordance with its own clock signal. In addition, the difference between the jitter of the clock signal of the disk reproducing device 1 and the jitter of the clock signal of the amplifier device 3 is removed, and high-quality reproduction of audio data is performed.

[Processing in Disc Reproducing Device During Flow Control] In the disc reproducing device 1, the audio decoder 18 is controlled based on instruction information (flow control command) transmitted from the amplifier device 3 via the IEEE1394 bus 2. The frequency of the clock signal supplied to the STC counter of the PLL / STC section is changed while changing the frequency of the clock signal for the output speed of the audio data supplied to the PLL.

By doing so, audio data is output from the disk reproducing device 1 at a speed according to the instruction from the amplifier device 3, and both overflow and underflow are stored in the buffer memory of the amplifier device 3. Appropriately perform flow control so that audio data is always taken in an appropriate amount without waking up.

Also, by changing the frequency of the clock signal supplied to the STC counter of the PLL / STC section, the synchronization between the audio data to be flow-controlled and the video data which must be processed simultaneously with the audio data is shifted. The decoding timing of the video data in the video decoder 16 to prevent the
The decoding timing of the SP signal in the P decoder 17 is also adjusted.

Hereinafter, the processing in the disk reproducing device 1 during the flow control will be described. FIG.
FIG. 3 is a block diagram for explaining the relationship and operation of a PLL / STC unit 24, video decoder 16, SP decoder 17, and audio decoder 18 of the digital playback device 1 shown in FIG. 2 when performing EE1394 flow control.

As shown in FIG. 4, the video decoder 16 of the disc player 1 includes a video code buffer 61,
A video decoder core 62;
SP decoder 17 includes an SP code buffer 71,
And a P decoder core 72.

As shown in FIG. 4, the audio decoder 18 of the disc reproducing apparatus 1 comprises an audio code buffer 81, an audio decoder core 82, and an output circuit 83.
The LL / STC unit 24 includes a PLL circuit 241 that generates various clock signals, and an STC counter 242 that counts a reference time.

The PLL circuit 241 constituting the PLL / STC section 24 receives a VMCK (Video Master) from a 27 MHz clock signal which is a system clock.
Clock), AMCK (Audio Master)
A clock signal such as an external clock (Clock), an ACK (Audio Clock), or a clock signal for counting is generated and supplied to each unit that requires the clock signal.

Here, VMCK is a master clock signal for operating the video decoder core 62 and the SP decoder core 72, and AMCK is a master clock signal for operating the audio decoder core 82. The ACK is a clock signal when the output circuit 83 of the audio decoder 18 outputs audio data to be D / A converted or a signal such as a digital output biphase. The counting clock signal is a 90 kHz clock signal used for counting the reference time in the STC counter 242.

As shown in FIG. 4, the 90-kHz counting clock signal from the PLL circuit 241 is supplied to the STC counter 242, which uses it for counting the reference time. The count value indicating the reference time counted by the STC counter 242 is the video decoder 16
, And the SP decoder core 72 of the SP decoder 17.

Also, the VMCK from the PLL circuit 241
Also, the video decoder core 62 of the video decoder 16
It is supplied to the SP decoder core 72 of the P decoder 17.
As a result, the video decoder core 62 of the video decoder 16 operates based on the VMCK from the PLL circuit 241, reads out the coded video data temporarily stored in the video code buffer 61, performs decoding processing on the coded video data, and performs decoding. The supplied video data is supplied to the synthesizing circuit 19.

At the time of this decoding processing, the video decoder core 62 sets the count value from the STC counter 242 and the video PTS (Prese
The decoding process is performed at a predetermined timing by comparing the data with a recording time stamp or a video DTS (Decoding Time Stamp).

Similarly, the SP decoder core 72 of the SP decoder 17 operates based on the VMCK from the PLL circuit 241, reads out the coded SP signal temporarily stored in the SP code buffer 71, and performs its decoding processing. hand,
The decoded SP signal is supplied to the synthesizing circuit 19.

Also in this case, the SP decoder core 7
2, the count value from the STC counter 242 and the SP · PTS (Present
ation time stamp), and the decoding process is appropriately performed at a predetermined timing.

The AMCK signal from the PLL circuit 241 is output.
Is supplied to the audio decoder core 82 of the audio decoder 18. The audio decoder core 82
It operates based on AMCK from the LL circuit 241, reads out the encoded audio data temporarily stored in the audio code buffer 81, performs decoding processing on the encoded audio data,
It is supplied to an output circuit 83 in the audio decoder 18.

The output circuit 83 includes a PLL circuit 2
ACK, which is a clock signal from the audio decoder core 41, is supplied to the audio sample data output from the audio decoder core 82 with an AMCK clock signal.
In place of the clock signal of the CK system, audio data and a synchronization signal such as LRCK are output to the subsequent stage.

[0117] The output circuit 83 instructs the audio decoder core 82 to start the next processing after outputting audio data for a predetermined number of audio samples determined for each audio format.
For example, in the case of a so-called AC3 stream, which is a digital audio signal compression scheme developed by Dolby Laboratories in the United States, after outputting 1536 samples corresponding to one audio frame, the audio decoder core 82 starts decoding the next audio frame. To be instructed.

The audio decoder core 82 is designed so that the decoding of the audio frame is completed within the time required for outputting the audio data of the number of samples corresponding to one audio frame. The number of audio samples determined for each audio format is not limited to the number of samples in the audio frame unit as described above, but may be another unit, for example, an audio block unit corresponding to 256 samples in the case of the above-described AC3 stream. .

Video decoder 1 of disc reproducing apparatus 1
6, SP decoder 17, audio decoder 18, PL
The basic operation of the L / STC unit 24 is as described above.
Then, the host controller 25 of the disk reproducing device 1
Is the IEEE 1394 bus 2, the digital I / F circuit 23
When receiving instruction information on flow control (command for flow control) from the amplifier device 3 through the CPU, the PLL / STC issues an instruction to change the frequency of the clock signal for counting and the frequency of ACK according to the instruction information. The signal is supplied to the PLL circuit 241 of the unit 24.

That is, the instruction information from the amplifier device 3 is:
In the case of the Fast command, the host controller 25 of the disk reproducing device 1
An instruction is issued to increase the frequency of the counting clock signal and ACK by + 1% from a predetermined frequency.

The instruction information from the amplifier device 3 is set to Sl
In the case of the ow command, the host controller 25 of the disk reproducing device 1 causes the PLL circuit 241 to make the frequency of the counting clock signal and the frequency of the ACK lower by -1% than a predetermined frequency. Give instructions.

The instruction information from the amplifier device 3 is St.
In the case of the standard command, the disc playback device 1
The host controller 25 instructs the PLL circuit 241 to set the frequency of the counting clock signal and the frequency of the ACK to 0% so as to be a predetermined frequency.

In this embodiment, the predetermined frequency of the count clock signal supplied to STC counter 242 is 90 kHz, and the predetermined frequency of ACK is 512 fs. Then, in response to an instruction from the host controller 25, the PLL circuit 241 changes the count clock signal of usually 90 kHz and the frequency of ACK of usually 512 fs to about the instructed value.

The output circuit 83 of the audio decoder 18 outputs an ACK, which is a clock signal supplied thereto.
Output audio data, etc.
The actual output speed of the audio data is almost equal to the speed specified by the amplifier device 2 as the receiving device. Since the output speed of the audio data is in accordance with the instruction from the amplifier device 3, the decoder start command sent to the audio decoder core 82 every time a predetermined amount of audio samples is output also becomes the instructed speed. That is, in the disc reproducing apparatus 1, audio data is continuously reproduced at the instructed speed.

The frequency change range described above is not exactly + 1% and -1%, but ± 0.1% as an error can be tolerated. That is, in this embodiment, + 1% is from + 1.1% to + 0.9%, and-
1% is from -1.1% to -0.9%. As described above, the change range of the count clock signal and ACK is approximately ± 1%.

In order to continuously reproduce audio data at a speed approximately 1% faster, the audio decoder 18 itself must be capable of always processing approximately 1% faster than the original processing speed. That is, the audio decoder 18 has a processing capability capable of processing about 1% faster than the original processing speed.

Each of the circuits before the audio decoder 18, ie, each of the RF circuit 12, the FE circuit 13, and the decryption / data separation unit 15, is approximately one time faster than the minimum processing speed required for the system. The processing can be performed at a speed faster by%. That is, R
F circuit 12, FE circuit 13, decryption / data separation unit 1
Each of No. 5 has a processing capability capable of processing about 1% faster than the original processing speed.

However, in a reproducing apparatus capable of reproducing a DVD such as a DVD-Video format, a DVD-Audio format, or a DVD-VR format, even if the reproducing apparatus does not perform flow control, it is not encrypted. The decryption / data separation unit
While it is sufficient to have a processing capacity of 10.08 Mbps, the FE circuit 13 and the circuit at the preceding stage thereof have a capacity of 11.08 Mbps.
Mbps processing capacity is required at a minimum.

Therefore, it is necessary to have a processing capability capable of processing approximately 1% faster than the minimum processing capability required for the conventional device that does not actually perform flow control. Only the decryption / data separation unit 15 and the audio decoder 18 are provided.

It is to be noted that the processing capacity of the decryption / data separation section 15 and the audio decoder 18 is set to have a processing capacity capable of increasing the processing speed by about 1% from the processing capacity conventionally required. However, for example, AMCK (Audio Master Cl)
It is not necessary to increase the frequency of the master clock signal (eg, ock).

That is, the frequency is adjusted by the STC
Only the count clock signal to the counter and ACK which is the clock signal to the output circuit 83 of the audio decoder 18 are included. By adjusting the frequency of the ACK, the output speed of the audio data from the output circuit 83 is adjusted, and the output circuit 8
3 also adjusts the timing of the decoder start instruction to the audio decoder core 82, and as a result, the time required for the audio data decoding process is also adjusted.

Further, when the flow control is not performed, or when the flow control is set to Standard or Slod.
When w is instructed, the audio decoder 18 only receives a decode start instruction from the output circuit 83 at intervals that are slower than its own processing capability.

That is, in this case, the audio decoder core 82 takes out the data from the audio code buffer 81 at a slow interval, so that the decryption / data separation unit 15 performs the processing slowly. Then, the processing speed of the decryption / data separation unit 15 and the FE
The difference between the processing speeds of the circuit sections preceding the circuit 13 is as follows.
It is absorbed by a track buffer 14 provided between the FE circuit 13 and the decryption / data separation unit 15.

Further, as described above, the frequency of the count clock signal to the STC counter 242 is also adjusted by the flow control command from the amplifier device 3. In other words, 90 kHz normally
The count clock signal of z is set to be higher by + 1% or lower by -1% by a command from the amplifier device 3.

Thus, in STC counter 242, the count value is incremented at the speed instructed by amplifier device 3, and the count value indicating the reference time is also counted late according to the flow control of the audio data. Or count faster, or count at a normal rate.

At this time, for example, in the video decoder 16 and the SP decoder 17 of the disc reproducing apparatus 1, the above-described PTS or DTS, which is time stamp information obtained from video data or sub-picture data, is used.
Is compared with the count value of the STC counter 242. If it is advanced, the decoding process is stopped by one picture (freeze by one picture), and if it is delayed, the decoding process is skipped by one picture. This makes it possible to reproduce video data that needs to be processed simultaneously with the audio data in synchronism with the audio data in response to the audio data whose output speed is changed by the flow control.

The frame rate in the case of the NTSC system is 29.97 Hz, and the frame rate in the case of the PAL system is 25 Hz. In the video decoder 16 and the SP decoder 17, the count from the STC counter is incremented by one picture. The values are compared with the video / PTS and SP / PTS, and the delay / advance is detected quickly and reliably so that the synchronization with the audio signal can be synchronized.

[0138] This AV synchronization processing is performed for DVD-Video.
Format and Vid used in DVD-Audio
This is particularly important when processing a stream in which audio data and video data are multiplexed, such as eo Object (VOB). This is because, in a multiplexed stream, if each decoder is not synchronized, an overflow or an underflow of the code buffer of each decoder occurs.

[0139] In the Audio Object (AOB) in the DVD-Audio format, video data is not multiplexed with audio data, and the video data is not multiplexed with ASV (Audio Still Video).
The video stream is supplied to a decoding unit such as a video decoder in advance as a separate stream called “deo). Also in this case, if the AV synchronization processing is not performed, the audio data and the video data are shifted more and more, and the reproduction intended by the creator when the disc is originally authored cannot be performed.

In addition, Audio Object (AO
B) shows that even if there is no video data,
l Time Information (RTI) is sometimes multiplexed with character information or the like. In such a case, when reproducing the RTI, the audio data and the RTI must be synchronized if the audio data and the RTI are not synchronized. Cause an overflow or underflow in the code buffer.

However, in the disk reproducing apparatus 1 of this embodiment, as described above, audio data, video data and sub-picture data, and
Synchronization with a TI or the like can be reliably established. Therefore, in the disc reproducing apparatus 1 of this embodiment, in each of the decoders 16, 17, and 18, no data overflow or underflow occurs in each of the code buffers 61, 71, 81.

Note that the audio data is stored in the IEEE 139
Audio D / A, not amplifier connected by 4
When the user listens to the reproduced audio only by using the output of the converter 22, or when the user listens to the reproduced audio and the reproduced video only with the television receiver connected to the IEEE1394, the instruction to the PLL circuit 241 of the disc reproducing apparatus 1 is issued. Stand
ard fixed.

[Processing in Disk Reproducing Apparatus 1 During Flow Control] Next, processing in the disk reproducing apparatus 1 as a signal output apparatus and processing in the amplifier apparatus 3 as a signal receiving apparatus when performing flow control. explain. First, a process at the time of flow control in the disk reproducing device 1 will be described.

FIG. 5 is a flowchart for explaining the processing performed in the disk reproducing apparatus 1 during flow control. The host controller 25 of the disk reproducing device 1 monitors a signal from the digital I / F circuit 23, and waits until a command for flow control is received (step S101).

When it is determined in step 101 that a command for flow control has been received, the host controller 25 determines the content of the command (step S102). That is, the determination processing in step S102 is that the received command is
ow command, Standard command, Fas
This is a process of determining whether the command is a t command.

When it is determined in the determination processing in step S 102 that the received command is a Slow command, the host controller 25 sets the PLL circuit 241
In contrast, the count clock signal and ACK are almost -1.
%, And the count clock signal and ACK are reduced by approximately -1% (step S10).
3).

When it is determined in the determination processing of step S102 that the received command is a standard command, the host controller 25
For the LL circuit 241, a count clock signal, A
An instruction to set CK to the normal frequency is issued, and the count clock signal and ACK are returned to the normal frequency (step S104).

If the host controller 25 determines that the received command is a Fast command in the determination processing of step S102, the host controller 25 raises the count clock signal and ACK to the PLL circuit 241 by approximately + 1%. To increase the count clock signal and ACK by approximately + 1% (step S10).
5).

Thus, the host controller 25
Adjusts the frequency of the clock signal for counting and the frequency of ACK based on a command from the amplifier device 3 which is a signal receiving device. Thereby, the output speed of the audio data from the output circuit 83 of the operating audio decoder 18 is adjusted by the ACK, and the frequency of the count clock signal is adjusted, whereby the count-up speed of the STC counter 242 is adjusted. Is done.

As a result, the output speed of the audio data from the disk reproducing device 1 becomes a speed according to the command from the amplifier device 3, and the flow control of the audio data is properly performed. Further, in this embodiment, the video decoder 16 and the SP decoder 17 of the disc player 1
By adjusting the decoding timing based on the count value from the TC counter 242, synchronization between audio data and video data is synchronized (AV synchronization processing).
I do it.

FIG. 6 is a flow chart for explaining the AV synchronization processing performed in the video decoder 16, and FIG. 7 is a flow chart for explaining the AV synchronization processing performed in the SP decoder 17.

First, the AV synchronization processing performed in the video decoder 16 will be described with reference to FIG.
The video decoder core 62 of the video decoder 16
The count value from the C counter 242 and the video PTS (D
TS) (step S201).
The content of the comparison process is determined (step S202).

In the determination processing of step S202, P
When it is determined that the count value (STC), which is the reference time from the STC counter 242, is larger than TS + th slow and the decoding of the video data is delayed,
The video decoder core 62 skips the decoding of the video data by one picture (step S20).
3) Synchronize the video data with the audio data, and then repeat the processing from step S201.

In the discrimination processing of step S202, S
When the count value (STC) as the reference time from the TC counter 242 is equal to or greater than PTS-th fast and the count value (STC) as the reference time from the STC counter 242 is equal to or less than PTS + th slow, It is determined that the data has been properly decoded, and the processing from step S201 is repeated.

In the determination processing of step S202, P
When it is determined that the count value (STC), which is the reference time from the STC counter 242, is smaller than TS-th fast and the decoding of the video data is in progress,
The video decoder core 62 stops (freezes) the decoding (decoding) of the video data for one picture (step S204), synchronizes the video data with the audio data, and thereafter repeats the processing from step S201.

In FIG. 6, th slow
Is an allowable amount of delay of the video data with respect to the audio data, and th fast is an allowable amount of advance of the video data with respect to the audio data.

Next, the SP decoder 1 will be described with reference to FIG.
7 will be described. The AV synchronization process performed in the SP decode 17 is as follows.
The processing is almost the same as the processing performed in the video decoder 16 shown in FIG.

That is, the SP decoder core 72 of the SP decoder 17 performs a process of comparing the count value from the STC counter 242 with SP / PTS which is time stamp information obtained from sub-picture data (step S301). The content of the comparison process is determined (step S302).

In the determination processing of step S302, P
When it is determined that the count value (STC), which is the reference time from the STC counter 242, is larger than TS + th slow and the decoding of the sub-picture data is delayed, the SP decoder core 72 performs decoding (decoding) of the sub-picture data. One picture is skipped (step S303), the sub-picture data and the audio data are synchronized, and then, step S30
The process from 1 is repeated.

In the determination processing of step S302, S
When the count value (STC) as the reference time from the TC counter 242 is equal to or greater than PTS-th fast and the count value (STC) as the reference time from the STC counter 242 is equal to or less than PTS + th slow, It is determined that the decoding of the picture data has been properly performed, and the processing from step S301 is repeated.

In the determination processing of step S302, P
When the count value (STC), which is the reference time from the STC counter 242, is smaller than TS-th fast and it is determined that decoding of the sub-picture data is in progress, the SP decoder core 72 decodes the sub-picture data. ) Is stopped (frozen) by one picture (step S304), the sub-picture data is synchronized with the audio data, and then the processing from step S301 is repeated.

In FIG. 7, th slow
Is an allowable amount of delay of the sub-picture data with respect to the audio data, and th fast is an allowable amount of advance of the sub-picture data with respect to the audio data.

As described above, the processing in FIG. 6 is performed in the video decoder 16 and the processing in FIG. 7 is performed in the SP decoder 17, so that the flow-controlled decoded audio data and the decoded video data are processed. The data can be output in synchronization with the data.

[Processing in Amplifier Device 3 During Flow Control] Next, the operation of the amplifier device 3 that performs flow control of the above-described disc reproducing device 1 during flow control will be described with reference to FIGS. 8 and 9.
As described above, the controller 35 of the amplifier device 3
Monitors the remaining amount of the buffer memory 32 for temporarily storing audio data from the disk reproducing device 1 and, in accordance with the remaining amount, instructs the disk reproducing device 1 on the output speed of the audio data for flow control. Send a command.

The amplifier device 3 of this embodiment sets some thresholds (thresholds) for the amount of audio data stored in the buffer memory 32, and forms and transmits a flow control command in accordance with the thresholds. I am trying to do it. FIG. 8 is a diagram for explaining a process of forming a command for flow control in the amplifier device 3 of this embodiment. In FIG.
The vertical axis indicates the amount of audio data stored in the buffer memory 32 as a percentage, and the vertical axis indicates time.

FIG. 8A is a diagram for explaining generation of a flow control command when the change in the amount of audio data stored in the buffer memory 32 is in the underflow direction, and FIG. It is a figure for explaining generation of the command for flow control when the change of the storage amount of 32 audio data is in the overflow direction.

As shown in FIGS. 8A and 8B, in the amplifier device 3 of this embodiment, four thresholds th1, th2, th3 and th4 are provided for the storage amount of audio data in the buffer memory 32. . These four thresholds th1, th2, th3, th
Each of 4 can be set on the manufacturer side so as not to cause overflow and underflow.

For example, for each of the four thresholds, th1 = 20%, th2 = 45%, th3
= 55%, th4 = 80%, or th1
= 17.5%, th2 = 42.5%, th3 = 57.5
%, Th4 = 82.5%. Further, considering the efficiency of processing, the denominator is set to be a power of 2, and for example, th1 = 25% (2/2 /
8), th2 = 37.5% (3/8), th3 = 62.
5% (5/8) and th4 = 75% (6/8) can also be set.

As shown in FIG. 8A, the storage amount of the audio data in the buffer memory 32 starts to decrease, and the output speed of the audio data to the disc reproducing device 1 is kept as long as the storage amount of the audio data exceeds the threshold th1. Is transmitted as a normal command.

Thereafter, the storage amount of the buffer memory 32 becomes
If the threshold value th1 is less than the threshold th1, the controller 35 of the amplifier device 3 sends the output speed of the audio data to the disc playback device 1 as normal (Stan).
fast), which indicates that it is 1% earlier than
Send a command.

Then, the storage amount of the audio data in the buffer memory 32 becomes equal to or more than the threshold th1,
Until the threshold th2 or more, the disc reproducing apparatus 1 as a transmitting device maintains a state corresponding to the Fast command for outputting audio data 1% earlier than usual.

Thereafter, when the storage amount of the audio data in the buffer memory 32 becomes equal to or larger than the threshold th2, the controller 35 of the amplifier device 3 outputs the audio data to the disk reproducing device 1. A standard command for instructing the speed to be normal is transmitted.

As described above, the controller 35 of the amplifier device 3 determines that the storage amount of the audio data in the buffer memory 32 is smaller than the threshold th1 and is smaller than the threshold th2 by one.
By controlling the output speed of the audio data from the disc reproducing apparatus 1 so that the digital data is sent out% earlier, so-called underflow, in which the audio data to be processed in the buffer memory 32 is lost, does not occur. Can be.

As shown in FIG. 8B, while the storage amount of the audio data in the buffer memory 32 starts to increase and is smaller than the threshold th4, the output speed of the audio data to the disc reproducing apparatus 1 is reduced. A Standard command instructing normal operation is transmitted.

Thereafter, the storage amount of the buffer memory 32 becomes
When the threshold th4 or more is reached, the controller 35 of the amplifier device 3 sends the output speed of the audio data to the disc playback device 1 as normal (Standard).
Send a Slow command instructing to make 1% later than rd).

Then, until the storage amount of the audio data in the buffer memory 32 becomes smaller than the threshold th4 and becomes equal to or smaller than the threshold th3, the disk reproducing device 1 as the transmitting device is 1% slower than usual. The state according to the Slow command for outputting data is maintained.

Thereafter, when the storage amount of the audio data in the buffer memory 32 becomes equal to or smaller than the threshold th3, the controller 35 of the amplifier device 3 outputs the audio data to the disc reproducing device 1. A standard command for instructing the speed to be normal is transmitted.

As described above, the controller 35 of the amplifier device 3 determines that the storage amount of the audio data in the buffer memory 32 becomes 1% or more than usual until the storage amount of the audio data becomes equal to or more than the threshold th4 and is restored to the threshold th3 or less. By controlling the output speed of the audio data from the disc reproducing apparatus 1 so that the digital data is sent out later, it is possible to prevent the buffer memory 32 from overflowing.

As described above, the controller 35 of the amplifier device 3 of this embodiment monitors the amount of audio data stored in its own buffer memory 32. It is the same as monitoring the remaining amount. If the remaining amount exceeds a predetermined amount, a Fast command is generated and transmitted to prevent an underflow, and the remaining amount becomes smaller than the predetermined amount. In this case, a Slow command is generated and transmitted to prevent overflow.

FIG. 9 is a flow chart for explaining the process at the time of the flow control of the amplifier device 3 described with reference to FIG. As shown in FIG. 9, at the time of the flow control, the amplifier device 3 checks the storage amount (buffer capacity) of the audio data in its own buffer memory 32, and determines the buffer capacity F and four predetermined thresholds. A comparison process is performed with the thresholds th1, th2, th3, and th4 (step S401).

If it is determined in step S401 that the buffer capacity F is smaller than the threshold th1, the controller 35 of the amplifier device 3
An ast command is generated and transmitted to the disc reproducing apparatus 1 as a transmitting device (step S402), and the processing from step S401 is repeated.

In step S401, the buffer capacity F is equal to or larger than the threshold th1, and
When it is determined that the buffer capacity F is smaller than the threshold th2, it is determined whether or not the buffer capacity F has decreased from the previous time (step S403).

If it is determined in step S403 that the buffer capacity F has decreased from the previous time, the controller 35 of the amplifier device 3 generates a Standard command and transmits it to the disk reproducing device 1 as a transmitting device. (Step S404), Step S40
The process from 1 is repeated.

If it is determined in step S403 that the buffer capacity F has not decreased from the previous time, the controller 35 of the amplifier device 3 maintains the state of the flow controller, and proceeds to step S401.
Is repeated.

In step S401, when it is determined that the buffer capacity F is equal to or larger than the threshold th2 and smaller than the threshold th3, the controller 35 of the amplifier device 3 generates a Standard command and sends it to the transmitting device. The data is transmitted to a certain disk reproducing apparatus 1 (step S405), and the processing from step S401 is repeated.

In step S401, the buffer capacity F is equal to or larger than the threshold th3, and
When it is determined that the buffer capacity F is smaller than the threshold th4, it is determined whether or not the buffer capacity F has increased from the previous time (step S406).

[0187] If it is determined in step S406 that the buffer capacity F has increased from the previous time, the controller 35 of the amplifier device 3 generates a Standard command and transmits it to the disk reproducing device 1 as a transmitting device. (Step S407), Step S40
The process from 1 is repeated.

If it is determined in step S406 that the buffer capacity F has not increased from the previous time, the controller 35 of the amplifier device 3 maintains the state of the flow controller, and proceeds to step S401.
Is repeated.

If it is determined in step S401 that the buffer capacity F is equal to or larger than the threshold th4, the controller 35 of the amplifier device 3
An ow command is generated and transmitted to the disc reproducing apparatus 1 as a transmission device (step S408), and the processing from step S401 is repeated.

As described above, the amplifier device 3 controls the output speed of the audio data from the disk reproducing device 1 for outputting the audio data in accordance with the remaining amount of the buffer memory of the amplifier device 3 so that the buffer memory 32 overflows. Without underflow, flow control can be performed, and digital audio data from the disk reproducing device 1 can be processed using the clock signal of the amplifier device 3 and reproduced with high quality.

In addition, as described above, in the disc reproducing apparatus 1, audio data and video data to be reproduced simultaneously with the audio data may be properly reproduced without synchronization with the audio data. it can.

[Another Example of Disc Reproducing Apparatus] In the above-described embodiment, the PLL circuit 241 uses the ST
By changing a count clock signal supplied to the C counter 242 and an ACK which is a clock signal supplied to the output circuit 83 of the audio decoder 18 based on a flow control command from the amplifier device 3, audio data can be obtained. The flow control is appropriately performed, and the audio data and the video data to be reproduced simultaneously with the audio data are reproduced without being out of synchronization.

However, without changing the ACK supplied to the output circuit of the audio decoder 18, the flow control is performed on the audio data, and the audio data and the video data are reproduced so as not to be out of synchronization. It is also possible to

FIG. 10 is a diagram for explaining a disk reproducing apparatus in which ACK supplied to an output circuit of an audio decoder is invariable to perform flow control. FIG. 10 shows a disc reproducing apparatus,
FIG. 4 is a diagram showing each part of a video decoder 16, an SP decoder 17, an audio decoder 18, a PLL / STC unit 24, and a host control 25, which are important parts when performing flow control. The other parts are configured in the same manner as the disc reproducing apparatus shown in FIG.

In the disc reproducing apparatus shown in FIG. 10, the output circuit 84 of the audio decoder 18 is different from the output circuit 83 of the audio decoder of the disc reproducing apparatus 1 shown in FIG. Output circuit 84 of audio decoder 18 of this example
ACK, which is a clock signal supplied from the PLL circuit 241, is unchanged.

Further, the output circuit 84 in the example shown in FIG. 10 is supplied with instruction information about an output speed in accordance with a flow control command from the amplifier device 3. Output circuit 84
Can change the output speed of the audio data based on the instruction information from the host controller 25. Each block other than the output circuit 84 has the same configuration as each corresponding block of the disc reproducing apparatus 1 shown in FIG.

As described above, by allowing the output circuit 84 of the audio decoder 18 to change the output speed of the audio data in accordance with the instruction information from the host controller 25, the flow of the audio data can be properly performed. You can take control.

Also, in the case of the example shown in FIG.
As in the case of the STC counter 242 of the disk reproducing apparatus 1 described above with reference to FIG.
90 kHz in the case of the Standard command, Fa
In the case of the st command, the frequency is + 1% higher than 90 kHz. In the case of the Slow command, the frequency is -1% higher than 90 kHz.
A low-frequency counting clock signal is supplied. Thus, the video data reproduced at the same time as the audio data is not out of synchronization with the audio data reproduced at the same time.

Further, the audio decoder 18 of this example
By providing a frame rate converter in the output circuit 84, audio data whose output speed is adjusted in response to a flow control command from the amplifier device 3, and further converting the audio data into a standard by the frame rate converter It is also possible to output two systems of audio data, ie, audio data having the speed.

The audio data whose output speed is adjusted in accordance with the flow control command from the amplifier device 3 is directly converted to a digital I / F.
The audio data supplied to the circuit 23 and set to the standard speed by the frame rate converter is
It is supplied to the AV encoder 21 and the D / A converter 22.

By doing so, the IEEE1
The AV stream of 394 is output in the same state as in the case where the flow control is not performed, and the stream of only the audio data of IEEE 1394 is subjected to the flow control so that the amplifier device 3 performs the high-quality reproduction of the audio data. can do.

In the above-described embodiment, the sub-picture data to be combined with the video data is also synchronized with the audio data. In this manner, various display data to be synthesized with the video data can also be synthesized without synchronizing with the video data by synchronizing with the audio data. Therefore, data that can be synchronized with audio data also includes various display data such as video data and sub-picture data, which are reproduced simultaneously with audio data.

Further, in the above-described embodiment, the disk reproducing device, the amplifier device, and the monitor
It has been described that a home network system is constructed by being connected by a digital bus of the E1394 standard.
It is not limited to the EE1394 standard. For example,
USB (Universal Serial Bus)
For example, a digital interface of another standard may be used.

Therefore, the present invention relates to the IEEE 139
The present invention is not limited to the flow control in the digital interface of the four standards, but is also effective when performing the flow control using other protocols.

In the disk reproducing apparatus according to the above-described embodiment, the video decoder core 62 of the video decoder 16 and the SP decoder core 72 of the SP decoder 17 carry out the count value from the STC counter 242 and the video / PTS or SP. A comparison with the PTS is performed, and based on the result, skipping of video data or SP data in units of one picture or temporary stop (freeze) of decoder processing is performed. However, it is not limited to this.

For example, the count value from the STC counter 242 and the video decoder core 6 of the video decoder 16
2 and the SP / PTS from the SP decoder core 72 of the SP decoder 17 are supplied to the host controller 25.
The host controller 25 may be configured to control the video decoder core 62 of the video decoder 16 and the SP decoder core 72 of the SP decoder 17 by determining the delay / advance of the decoding of the video data with respect to the audio data. .

In the disc reproducing apparatus 1 as shown in FIG. 2, the video decoder 16, the SP decoder 17, the audio decoder 18, the PLL / STC section, or the decryption / data separation section 15 are added to them. In many cases, such a part is configured as an AV decoder (audio / visual decoder) of an integrated circuit. In such a case, the video decoder 16 and the SP decoder 17 may be configured to determine the delay / advance of the decoder and to perform self-control according to the determination result, thereby imposing a load on the host controller. Nor.

In the above-described embodiment, the decryption / data separation unit 15,
The processing capability of the audio decoder 18 has been described as being approximately 1% higher than the normally required processing capability, but the present invention is not limited to this. With a margin, the processing capacity may be several percent higher than usual, such as 2% or 3%.

In the above-described embodiment, the processing capability of the RF circuit 12 and the FE circuit 13 of the disk reproducing apparatus may be increased by approximately 1% or several%. Good.

[0210] In the above-described embodiment, the disc reproducing apparatus is described as using a DVD as a recording medium. However, the present invention is not limited to this. For example, a video CD or SVCD (Super Video CD)
The signal output device and the signal output method according to the present invention can be applied to a reproduction device of various recording media handling digital audio data and video data, such as a reproduction device of the present invention.

[0211] Recently, digital television broadcasting and the like have also been performed. Also in the case of digital television broadcasting, encoded audio data and encoded video data must be processed simultaneously.
For example, STB (Se) that simultaneously processes such encoded audio data and encoded video data.
t-Top Box), IRD (Integrated)
The signal output device according to the present invention can also be applied to a digital broadcast receiving device called a ReceiverDecoder or the like.

In this case, in the disk reproducing apparatus 1 shown in FIG. 2, a tuner section for receiving and selecting a digital broadcast is provided instead of the optical pickup 11 and the RF circuit 12. In the case of digital broadcasting, audio data and video data of a plurality of broadcast programs,
PG (Electronic Program Gui)
de) Data and the like are multiplexed.

For this reason, for example, the decryption / data separation unit 15 is configured to be able to extract audio data, video data, other related data, and the like of a target program in response to an instruction from the user. Department and
This can be achieved by separately providing a data separation unit (demultiplexer). But,
Even in the case of receiving equipment, including the PLL / STC part,
The decoder section for audio data and video data can be configured in the same manner as the above-described disc reproducing apparatus.

[0214]

As described above, according to the present invention, when coded audio data and coded video data are simultaneously processed and reproduced, flow control is performed on the audio data. In addition to high-quality reproduction, audio data and video data can be reproduced in synchronization.

[0215] Also, in the case of performing conventional reproduction without using a digital bus such as IEEE 1394, it is also possible to perform the conventional reproduction without performing flow control.

In addition to outputting conventional audio data and video data without performing flow control, simultaneously, audio data for which flow control is performed and video data synchronized with the audio data are output. It can also be output.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a home network system to which an embodiment of a signal processing system according to the present invention is applied.

FIG. 2 is a block diagram illustrating a disc reproducing apparatus to which an embodiment of a signal output device according to the present invention is applied;

FIG. 3 is a block diagram illustrating an amplifier device to which an embodiment of the signal receiving device according to the present invention is applied;

FIG. 4 is a block diagram for explaining each decoder part of the disc reproducing apparatus shown in FIG. 2;

FIG. 5 is a flowchart for explaining processing at the time of flow control performed by host control of the disk reproducing apparatus shown in FIG. 2;

FIG. 6 is a flowchart for explaining processing at the time of flow control executed in the video decoder of the disc reproducing apparatus shown in FIG. 2;

FIG. 7 is a flowchart for explaining a process at the time of flow control executed in the SP decoder of the disc reproducing apparatus shown in FIG. 2;

FIG. 8 is a diagram for explaining a process at the time of flow control in the amplifier device as the signal receiving device shown in FIG. 3;

FIG. 9 is a flowchart illustrating a process at the time of flow control in the amplifier device serving as the signal receiving device illustrated in FIG. 3;

FIG. 10 is a block diagram for explaining a disc reproducing apparatus to which another embodiment of the signal output device according to the present invention is applied.

FIG. 11 is a diagram illustrating a flow control for audio data.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Disc reproducing apparatus, 10 ... Disk, 11 ... Optical pickup, 12 ... RF circuit, 13 ... FE circuit, 14 ... Track buffer, 15 ... Decryption / data separation part, 16
... Video decoder, 17 ... SP decoder, 18 ... Audio decoder, 19 ... Synthesis circuit, 20 ... NTSC encoder, 21 ... AV encoder, 22 ... Audio D / A
Converter, 23 ... Digital interface circuit, 2
4: PLL / STC unit, 25: Host controller, 6
1 ... buffer memory, 62 ... video decoder core, 71
... Buffer memory, 72 ... SP decoder core, 81 ... Buffer memory, 82 ... Audio decoder core, 83,
84 output circuit, 241 PLL circuit, 242
... STC counter, 31 ... Digital interface circuit, 32 ... Buffer memory, 33 ... Signal processing circuit, 34
... PLL circuit, 35 ... controller, 36 ... operation unit, 3
7 Display unit

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[Procedure amendment]

[Submission date] May 25, 2001 (2001.5.2)
5)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 43

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0100

[Correction method] Change

[Correction contents]

Further, the controller 35 of the amplifier device 3
Is, the forceps the remaining capacity of the buffer memory 32, buffer memory
When the remaining amount of the memory 32 becomes a predetermined amount, the data storage amount of the buffer memory becomes appropriate, and the disc player 1 is instructed to output the audio data at a normal output speed (Standard command). ), Which are connected to the digital I / F circuit 31 and the IEEE 1394 bus 2
To the disc reproducing apparatus 1 through

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0103

[Correction method] Change

[Correction contents]

By doing so, audio data is output from the disk reproducing device 1 at a speed corresponding to the instruction from the amplifier device 3, and both overflow and underflow are stored in the buffer memory of the amplifier device 3. Appropriately perform flow control so that audio data is always taken in an appropriate amount without waking up.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0166

[Correction method] Change

[Correction contents]

FIG. 8A is a diagram for explaining generation of a flow control command when the change in the amount of audio data stored in the buffer memory 32 is in the underflow direction, and FIG. 32 stores the amount of change of the audio data of o - bar
FIG. 11 is a diagram for describing generation of a command for flow control when the command is in the flow direction.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

As shown in FIGS. 8A and 8B, in the amplifier device 3 of this embodiment, four thresholds th1, th2, th3 and th4 are provided for the storage amount of audio data in the buffer memory 32. . These four thresholds th1, th2, th3, th
Each of 4 can be set on the manufacturer side so as not to cause overflow and underflow.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0208

[Correction method] Change

[Correction contents]

In the above-described embodiment, the decryption / data separation unit 15,
The processing capability of the audio decoder 18 has been described as being approximately 1% higher than the normally required processing capability, but the present invention is not limited to this. Look at the margin, 2%, that 3%
As described above, the processing capacity may be several percent higher than usual.

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Claims (46)

[Claims] 1. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, and a signal receiving device for receiving at least the audio signal output from the signal output device. A signal processing system comprising: a signal receiving device, a receiving unit that receives at least an audio signal decoded from the signal output device; a memory that stores the audio signal received by the receiving unit; An audio signal processing unit that reads the audio signal stored in the memory based on a clock signal of the own device and processes the audio signal; monitors a remaining amount of the memory; and outputs an audio signal in accordance with the remaining amount. Command information forming means for forming command information relating to the output speed of the electronic device; Transmitting means for transmitting the instruction information to the signal output device, wherein the signal output device receives the instruction information on the output speed of the audio signal from the signal receiving device; and Clock signal generating means for generating a clock signal of a type to be generated at a frequency corresponding to the instruction information received through the instruction information receiving means, decoding the encoded audio signal, and outputting the output speed of the decoded audio signal. An audio signal decoding unit that can be changed according to an output clock signal generated by the clock signal generation unit in response to the instruction information; and a count clock signal generated by the clock signal generation unit in response to the instruction information Count for controlling a decoding process of the encoded digital video signal based on A calculating means for calculating a value; a means for decoding the encoded digital video signal; a video signal decoding means capable of controlling a decoding timing based on the count value from the calculating means; and the audio signal decoding means. 1. A signal processing system comprising: an audio signal transmitting unit that transmits an audio signal decoded by a video signal to the signal receiving device; and a video signal transmitting unit that transmits a video signal decoded by the video signal decoding unit. 2. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, and a signal receiving device for receiving at least the audio signal output from the signal output device. A signal processing system comprising: a signal receiving device, a receiving unit that receives at least an audio signal decoded from the signal output device; a memory that stores the audio signal received by the receiving unit; An audio signal processing unit that reads the audio signal stored in the memory based on a clock signal of the own device and processes the audio signal; monitors a remaining amount of the memory; and outputs an audio signal in accordance with the remaining amount. Command information forming means for forming command information relating to the output speed of the electronic device; Transmitting means for transmitting the instruction information to the signal output device, wherein the signal output device receives the instruction information on the output speed of the audio signal from the signal receiving device; and Clock signal generating means for generating a clock signal of a type at a frequency corresponding to the instruction information received through the instruction information receiving means, decoding the encoded audio signal, and setting the output speed of the decoded audio signal to An audio signal decoding unit that can be changed according to the instruction information; and a decoding processing of the encoded digital video signal based on a count clock signal generated by the clock signal generation unit according to the instruction information. Calculating means for calculating the count value of; and means for decoding the encoded digital video signal. A video signal decoding unit whose decoding timing can be controlled based on the count value from the calculation unit; an audio signal transmission unit that transmits an audio signal decoded by the audio signal decoding unit to the signal receiving device; And a video signal transmitting means for transmitting a video signal decoded by the video signal decoding means. 3. The signal processing system according to claim 1, wherein the signal output device records a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal. Reading means for reading the multiplexed signal from a recording medium; demodulating means for demodulating the multiplexed signal read by the reading means; and the encoded audio signal from the multiplexed signal demodulated by the demodulating means. A signal separating unit that separates the encoded video signal and supplies the encoded audio signal to the audio signal decoding unit and supplies the encoded video signal to the video signal decoding unit. Signal processing system. 4. The signal processing system according to claim 1, wherein the signal output device receives a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal. Means, demodulating means for demodulating the multiplexed signal received by the receiving means, separating the encoded audio signal and the encoded video signal from the multiplexed signal demodulated by the demodulating means, A signal processing system, comprising: a signal separation unit that supplies an encoded audio signal to the audio signal decoding unit and supplies the encoded video signal to the video signal decoding unit. 5. The signal processing system according to claim 1, wherein in the signal output device, the clock signal generation means converts a target clock signal according to the instruction information. The frequency you need,
The audio decoding means and the calculation means can be generated at any one of a frequency several% lower than the originally required frequency and a frequency several% higher than the originally required frequency. A signal processing system having a processing capability that is at least several percent higher than a minimum required processing capability, and a processing speed can be changed within the range of the processing capability. 6. The signal processing system according to claim 3, wherein in the signal output device, the readout unit, the demodulation unit, and the signal separation unit have at least a minimum required processing capability. It has a several percent higher processing capability, and the readout unit, the demodulation unit, and the signal separation unit can change the processing speed according to the clock signal from the clock signal generation unit. And a signal processing system. 7. The signal processing system according to claim 4, wherein in the signal output device, the receiving unit, the demodulating unit, and the signal separating unit have at least a minimum required processing capability. The receiving means, the demodulating means, and the signal separating means can change the processing speed in accordance with a clock signal from the clock signal generating means. And a signal processing system. 8. The signal processing system according to claim 5, wherein a ratio of several percent for the frequency and a ratio of several percent for the processing capability are substantially one. %. A signal processing system comprising: 9. The signal processing system according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, claim 7, or claim 8, wherein the signal receiving apparatus The signal processing system according to claim 1, wherein the receiving means and the transmitting means, and the audio signal transmitting means and the receiving means of the signal output device are connected by a digital interface. 10. The signal processing system according to claim 9, wherein the digital interface conforms to the IEEE 1394 standard. 11. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, wherein the signal output device relates to at least an output speed of the audio signal from a receiving device that receives the audio signal. Instruction information receiving means for receiving the instruction information; a clock signal generating means for generating a clock signal of a desired type at a frequency corresponding to the instruction information received through the instruction receiving means; and An audio signal decoding unit that can change the output speed of the decoded audio signal in response to the output clock signal generated by the clock signal generation unit in accordance with the instruction information; and Based on the count clock signal generated by the clock signal generation means, Calculating means for calculating a count value for controlling a decoding process of the encoded digital video signal; andmeans for decoding the encoded digital video signal, and a decoding timing based on the count value from the calculating means. Controllable video signal decoding means, audio signal transmission means for transmitting the audio signal decoded by the audio signal decoding means to the signal receiving device, and video for transmitting the video signal decoded by the video signal decoding means A signal output device comprising: signal transmission means. 12. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, wherein the signal output device relates to at least an output speed of the audio signal from a receiving device that receives the audio signal. Instruction information receiving means for receiving the instruction information; a clock signal generating means for generating a target type of clock signal at a frequency corresponding to the instruction information received through the instruction information receiving means; and the encoded audio signal. And an audio signal decoding unit that can change an output speed of the decoded audio signal according to the instruction information according to an output clock signal generated by the clock signal generation unit. Based on a counting clock signal generated by the clock signal generating means. Calculating means for calculating a count value for controlling a decoding process of the encoded digital video signal; andmeans for decoding the encoded digital video signal, based on the count value from the calculating means. A video signal decoding unit whose decoding timing is controllable; an audio signal transmission unit for transmitting an audio signal decoded by the audio signal decoding unit to the signal receiving device; and a video signal decoded by the video signal decoding unit. And a video signal transmitting means. 13. The signal output device according to claim 11, wherein the multiplexed signal is obtained from a recording medium on which a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal is recorded. Reading means for reading a signal; demodulating means for demodulating the multiplexed signal read by the reading means; and the encoded audio signal and the encoded video signal from the multiplexed signal demodulated by the demodulating means. And a signal output unit that supplies the encoded audio signal to the audio signal decoding unit and supplies the encoded video signal to the video signal decoding unit. 14. A signal output apparatus according to claim 11, wherein said receiving means receives a multiplexed signal in which an encoded audio signal and an encoded video signal are multiplexed, and said receiving means. Demodulating means for demodulating the multiplexed signal received by, and separating the encoded audio signal and the encoded video signal from the multiplexed signal demodulated by the demodulation means, A signal output device comprising: a signal separation unit that supplies the encoded video signal to the video signal decoding unit while supplying the encoded video signal to the audio signal decoding unit. 15. The signal output device according to claim 11, wherein the clock signal generating means converts a target clock signal into a frequency originally required according to the instruction information,
The audio decoding means and the calculation means can be generated at any one of a frequency several% lower than the originally required frequency and a frequency several% higher than the originally required frequency. A signal output device having a processing capability at least several percent higher than the minimum required processing capability. 16. The signal output device according to claim 13, wherein said reading means, said demodulating means, and said signal separating means have a processing capacity at least several% higher than a minimum required processing capacity. A signal output device, wherein the reading unit, the demodulating unit, and the signal separating unit can change the processing speed according to a clock signal from the clock signal generating unit. 17. The signal output device according to claim 14, wherein said receiving means, said demodulating means, and said signal separating means have a processing capability at least several% higher than a minimum required processing capability. A signal output device, wherein the reception unit, the demodulation unit, and the signal separation unit can change a processing speed according to a clock signal from the clock signal generation unit. 18. The method according to claim 15, 16 or 1.
8. The signal output device according to claim 7, wherein a ratio of several% for the frequency and a ratio of several% for the processing capability are approximately 1%. 19. The method of claim 11, claim 12, claim 13,
19. The signal output device according to claim 14, 15, 16, 17, or 18, wherein the audio signal transmitting unit and the receiving unit are connected to a digital interface. Signal output device. 20. The signal output device according to claim 19, wherein the digital interface conforms to the IEEE 1394 standard. 21. A signal receiving device for receiving at least an audio signal from a signal output device configured to simultaneously process and output at least an encoded audio signal and an encoded video signal, the signal receiving device comprising: A receiving unit that receives at least the decoded audio signal; a memory that stores the audio signal received by the receiving unit; and an audio signal stored in the memory based on a clock signal of the own device. Audio signal processing means for reading and processing the same; instruction information forming means for monitoring the remaining amount of the memory and forming instruction information relating to the output speed of the audio signal according to the remaining amount; and the instruction information forming means Transmitting means for transmitting the instruction information formed by the above to the signal output device. Signal receiving apparatus. 22. The signal receiving apparatus according to claim 21, wherein said receiving means and said transmitting means are connected to a digital interface. 23. The signal receiving apparatus according to claim 22, wherein the digital interface conforms to the IEEE 1394 standard. 24. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, and a signal receiving device for receiving at least the audio signal output from the signal output device. A signal processing method performed, wherein the signal receiving device receives a decoded audio signal from the signal output device, and stores the received audio signal in a memory; and An audio signal processing step of reading out the stored audio signal based on its own clock signal and processing the same, monitoring the remaining amount of the memory, and instructing information on an output speed of the audio signal according to the remaining amount. And transmitting the signal to the signal output device. Instruction information receiving step of receiving the instruction information relating to the output speed of the audio signal from the signal receiving apparatus, and a clock signal for generating a target type of clock signal at a frequency corresponding to the instruction information received in the receiving step A generation step; an audio signal decoding step of decoding the encoded audio signal and outputting the decoded audio signal at an output speed corresponding to an output clock signal generated in the clock signal generation step in accordance with the instruction information; A calculating step of calculating a count value for controlling a decoding process of the encoded digital video signal based on the counting clock signal generated in the clock signal generating step in accordance with Controlling the decoding timing based on the value of the coded digital video signal. A video signal decoding step of decoding the audio signal, an audio signal transmission step of transmitting the audio signal decoded in the audio signal decoding step to the signal receiving apparatus, and a video signal transmission step of transmitting the video signal decoded in the video signal decoding step. A signal processing method comprising: 25. A signal output device for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, and a signal receiving device for receiving at least the audio signal output from the signal output device. A signal processing method performed, wherein the signal receiving device receives a decoded audio signal from the signal output device, and stores the received audio signal in a memory; and Reading the captured audio signal based on its own clock signal,
An audio signal processing step of processing this, and a transmission step of monitoring the remaining amount of the memory, forming instruction information on an output speed of the audio signal according to the remaining amount, and transmitting this to the signal output device. In the signal output device, an instruction information receiving step of receiving the instruction information relating to an output speed of an audio signal from the signal receiving device, and a clock signal of a target type received in the receiving step A clock signal generating step of generating at a frequency according to the instruction information; an audio signal decoding step of decoding the encoded audio signal and outputting the encoded audio signal at an output speed according to the instruction information; Decoding the encoded digital video signal based on the count clock signal generated in the clock signal generation step A calculating step of calculating a count value for controlling; a video signal decoding step of controlling a decoding timing based on the count value calculated in the calculating step to decode the encoded digital video signal; and the audio signal decoding A signal processing method, comprising: an audio signal transmitting step of transmitting an audio signal decoded in the step to the signal receiving apparatus; and a video signal transmitting step of transmitting a video signal decoded in the video signal decoding step. 26. The signal processing method according to claim 24, wherein the signal output device records a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal. A reading step of reading the multiplexed signal from the recorded recording medium; a demodulating step of demodulating the multiplexed signal read in the reading step; and the encoded audio signal and the code from the multiplexed signal demodulated in the demodulating step. And a signal separation step of separating the signal from the encoded video signal. 27. The signal processing method according to claim 24, wherein the signal output device receives a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal. A receiving step; a demodulating step of demodulating the multiplexed signal received in the receiving step; and a signal separating step of separating the encoded audio signal and the encoded video signal from the multiplexed signal demodulated in the demodulating step. A signal processing method comprising: 28. The signal processing method according to claim 24, wherein the clock signal generating step of the signal output device requires a target clock signal in accordance with the instruction information. , A frequency that is several percent lower than the originally required frequency, and a frequency that is several percent higher than the originally required frequency. The signal processing, wherein the audio decoding step and the calculating step have a processing capability at least several percent higher than the minimum required processing capability, and the processing speed can be changed within the range of the processing capability. Method. 29. The signal processing method according to claim 26, wherein the readout step, the demodulation step, and the signal separation step of the signal output device are at least several times more than a minimum required processing capability. % Of the readout step, the demodulation step, and the signal separation step of the signal output device change the processing speed in accordance with a clock signal from the clock signal generation step. A signal processing method characterized by the following. 30. The signal processing method according to claim 27, wherein the receiving step of the signal output device, the demodulating step,
The signal separation step has a processing capability at least several percent higher than the minimum required processing capability. The reception step, the demodulation step, and the signal separation step include a clock from the clock signal generation step. A signal processing method wherein the processing speed can be changed according to a signal. (31) The method according to the above (28), (29) or (3).
0. The signal processing method according to claim 1, wherein a ratio of several% for the frequency and a ratio of several% for the processing capability are substantially 1%. 32. Claim 24, Claim 25, Claim 26,
32. The signal processing method according to claim 27, claim 28, claim 29, claim 30, or claim 31, wherein a receiving step and a transmitting step of the signal receiving apparatus and an audio signal transmitting step of the signal output apparatus. And a receiving step of transmitting or receiving a signal through a digital interface. 33. The signal processing method according to claim 32, wherein the digital interface conforms to the IEEE 1394 standard. 34. A signal output method for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, wherein the method relates to at least the output speed of the audio signal from a receiving device that receives the audio signal. An instruction information receiving step of receiving the instruction information; a clock signal generating step of generating a target type of clock signal at a frequency corresponding to the instruction information received in the instruction information receiving step; And an audio signal decoding step of outputting the same at an output speed according to an output clock signal generated in the clock signal generation step according to the instruction information, and the clock signal generation step according to the instruction information. The encoded digital video signal is generated based on the counting clock signal generated. A calculating step of calculating a count value for controlling a decoding process of a signal, a video signal decoding step of controlling a decoding timing based on the count value calculated in the calculating step, and decoding the encoded digital video signal. An audio signal transmitting step of transmitting an audio signal decoded in the audio signal decoding step to the signal receiving apparatus; and a video signal transmitting step of transmitting a video signal decoded in the video signal decoding step. Signal output method. 35. A signal output method for simultaneously processing and outputting at least an encoded audio signal and an encoded video signal, wherein the method relates to at least an output speed of the audio signal from a receiving device that receives the audio signal. An instruction information receiving step of receiving the instruction information; a clock signal generating step of generating a target type of clock signal at a frequency corresponding to the instruction information received in the instruction information receiving step; And an audio signal decoding step of outputting the same at an output speed according to the instruction information, and the encoded digital signal based on a count clock signal generated in the clock signal generation step according to the instruction information. A calculating step of calculating a count value for controlling a video signal decoding process; A video signal decoding step of controlling the decoding timing based on the count value calculated in the calculation step to decode the encoded digital video signal; and transmitting the audio signal decoded in the audio signal decoding step to the signal receiving device. A signal output method comprising: an audio signal transmitting step; and a video signal transmitting step of transmitting a video signal decoded in the video signal decoding step. 36. The signal output method according to claim 34 or 35, wherein the multiplexing is performed from a recording medium on which a multiplexed signal obtained by multiplexing an encoded audio signal and an encoded video signal is recorded. A reading step of reading a signal; a demodulating step of demodulating the multiplexed signal read in the reading step; and separating the encoded audio signal and the encoded video signal from the multiplexed signal demodulated in the demodulating step. A signal output method, comprising: a signal separation step. 37. The signal output method according to claim 34 or claim 35, wherein: a receiving step of receiving a multiplexed signal in which an encoded audio signal and an encoded video signal are multiplexed; A demodulating step of demodulating the multiplexed signal received in, and a signal separating step of separating the encoded audio signal and the encoded video signal from the multiplexed signal demodulated in the demodulating step. Signal output method. 38. The signal output method according to claim 34 or claim 35, wherein the clock signal generating step comprises: converting a target clock signal to a frequency originally required according to the instruction information;
It can be generated at any one of a frequency several% lower than the originally required frequency and a frequency several% higher than the originally required frequency. In the audio decoding step and the calculation step, ,
A signal output method having a processing capability at least several percent higher than a minimum required processing capability, and wherein a processing speed can be changed within a range of the processing capability. 39. The signal processing method according to claim 36, wherein the readout step, the demodulation step, and the signal separation step have a processing capability at least several% higher than a minimum required processing capability. A signal output method, wherein the readout step, the demodulation step, and the signal separation step can change a processing speed according to a clock signal from the clock signal generation step. 40. The signal output method according to claim 37, wherein said receiving step, said demodulating step, and said signal separating step have a processing capability at least several% higher than a minimum required processing capability. A signal output method, wherein the reception step, the demodulation step, and the signal separation step can change the processing speed according to a clock signal from the clock signal generation step. (41) The method according to the above (38), (39) or (4).
0. The signal output method according to claim 0, wherein a ratio of several% for the frequency and a ratio of several% for the processing capability are substantially 1%. 42. Claim 34, Claim 35, Claim 36,
42. The signal output method according to claim 37, claim 38, claim 39, claim 40 or claim 41, wherein the audio signal transmitting step and the receiving step include transmitting or receiving a signal through a digital interface. A signal output method. 43. The signal output method according to claim 429, wherein said digital interface conforms to the IEEE 1394 standard. 44. A signal receiving method for receiving at least an audio signal from a signal output device configured to simultaneously process and output at least an encoded audio signal and an encoded video signal, the method comprising: Receiving the decoded audio signal, storing the same in a memory, and reading the audio signal captured in the memory in the receiving step based on the clock signal of the own device,
An audio signal processing step of processing this, and a transmission step of monitoring the remaining amount of the memory, forming instruction information on an output speed of the audio signal according to the remaining amount, and transmitting this to the signal output device. A signal receiving method comprising: 45. The signal receiving method according to claim 44, wherein in the receiving step and the transmitting step, a signal is received or transmitted through a digital interface. 46. The signal receiving method according to claim 45, wherein the digital interface conforms to the IEEE 1394 standard.