JP2002290500A - Clock control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that electric power is consumed wastefully by clock signals supplied under a situation where communication queuing time is caused to a slave circuit owing to circumstances of internal operation of a master circuit when the master circuit 10 and the slave circuit 11 communicate in handshake system. SOLUTION: This clock control circuit has a communication monitor circuit 12 which recognizes the communication state by two signals for handshake, RQST and RDY, clock signals for the master circuit and the slave circuit, CLKM and CLKS, respectively, and a clock selection circuit 13 which selects a clock for the slave circuit to be used in the next communication depending on the communication state. This circuit controls clock frequency of the slave circuit to the necessary minimum level by supplying a high frequency clock when the queuing time of the master circuit is long, and a low frequency clock when the queuing time of the slave circuit is long.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit, and more particularly to a clock control circuit for controlling a clock of a digital circuit performing communication by a handshake method.

[0002]

2. Description of the Related Art In a digital circuit, when communication is performed between two circuits, a method of controlling communication by a handshake method is mainly used in order to notify a partner of the state of each other.

FIG. 6 is a block diagram showing a configuration of a digital circuit for performing data communication by a handshake method.
In FIG. 6, reference numeral 60 denotes a main circuit, and 61 denotes a sub-circuit that performs processing in response to a processing request from the main circuit 60. Main circuit 60
Operate in synchronization with the clock signal CLKM, and
Operate in synchronization with the clock signal CLKS. These two
The two circuits are connected by a RQST signal and an RDY signal in order to communicate a mutual state, in addition to a data line (not shown) for original data communication. The RQST signal is for transmitting a processing request from the main circuit 60 to the sub circuit 61, and the RDY signal is for transmitting the processing completion of the sub circuit 61 to the main circuit 60.

FIG. 7 is a timing chart showing an operation state of the digital circuit shown in FIG. The RQST signal is
The state changes to the valid state “1” in synchronization with the rise of the CLKM signal in response to the processing request of the main circuit 60. In the slave circuit 61, the first CLKS after the RQST signal becomes "1"
When the signal rises, it recognizes a processing request from the main circuit 60 and starts processing. When the processing in the slave circuit 61 is completed, the RDY signal changes to the valid state “1” in synchronization with the next rise of the CLKS signal. The main circuit 60 returns the RQST signal to the invalid state “0” when it becomes possible to receive the processing result from the slave circuit 61. Slave circuit 61
Recognizes that the reception of the main circuit 60 has been completed when the RQST signal becomes "0", returns the RDY signal to the invalid state "0", and completes one communication.

As described above, the period from when the RQST signal becomes “1” to when the RDY signal becomes “1” (hereinafter referred to as period A) is as follows. A period corresponding to the “period”. Also, RDY
The period from when the signal becomes “1” to when the RQST signal becomes “0” (hereinafter referred to as period B) is a period corresponding to “a period during which the slave circuit waits for the completion of reception of the main circuit”. Is shown.

[0006]

The operation of communication control by the conventional handshake method is as described above, and one circuit can know the state of the other circuit.
For example, at a stage where the slave circuit has not finished processing the data, the main circuit transmits the data, and such a problem that the data is lost in an unprocessed state cannot occur. However, in the operation shown in FIG. 7, when the period B is long, it is presumed that the processing in the main circuit was not affected even when the processing in the slave circuit took time. In such a case, since the clock signal supplied to the slave circuit during the period B is not necessary for processing, power consumed by inputting the clock signal CLKS to the slave circuit during this period is wasted. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and optimally controls the frequency of a clock signal supplied to a slave circuit used in the next communication according to the past communication state. It is another object of the present invention to provide a clock control circuit capable of reducing power consumed by a clock line of a slave circuit without affecting processing performance of a main circuit.

[0008]

According to a first aspect of the present invention, there is provided a clock control circuit for controlling a clock of a digital circuit having a main circuit and a slave circuit for performing communication by a handshake method. A processing request signal (hereinafter abbreviated as RQST signal) output from the main circuit, a processing completion signal (hereinafter abbreviated as RDY signal) output from the slave circuit, Clock signal (hereinafter abbreviated as CLKM) and the clock signal for the sub-circuit (hereinafter abbreviated as CLKS), and the communication state between the main circuit and the sub-circuit is determined by these signals. A communication monitoring circuit for monitoring and outputting a control signal according to the communication state; and a clock signal for the slave circuit in response to a control signal output from the communication monitoring circuit.
A clock selection circuit that outputs the S signal as it is, outputs a clock signal having a frequency different from that of the CLKS signal, or stops outputting the clock signal to the slave circuit.

The clock control circuit according to a second aspect of the present invention is the clock control circuit according to the first aspect,
The communication monitoring circuit includes a first counter circuit that counts the number of changes of the CLKM during a period in which the RQST signal is in an effective state, and a first counter circuit that compares an output value of the first counter circuit with a preset value. And the above RD
A first register circuit that captures an output of the first comparison circuit when the Y signal changes from an invalid state to a valid state;
A second counter circuit that counts the number of changes of the CLKS during a period in which the RDY signal is in a valid state, a second comparator circuit that compares an output value of the second counter circuit with a preset value, A second register circuit that captures the output of the second comparison circuit when the RQST signal changes from a valid state to an invalid state; and a first register circuit that captures the first signal when the RDY signal changes from a valid state to an invalid state. A state transition circuit that transitions to the next state by the output of the register circuit and the output of the second register circuit, and at the same time, determines an output signal to the clock selection circuit.

The clock control circuit according to a third aspect of the present invention is the clock control circuit according to the second aspect,
A plurality of register circuits connected in series at a subsequent stage of the first register circuit so as to capture the output of the preceding register circuit at the same time as capturing the output of the first register circuit; It is provided with a first register circuit and a first majority circuit that receives outputs of the plurality of register circuits as inputs and determines an output signal to the state transition circuit.

The clock control circuit according to claim 4 of the present invention is the clock control circuit according to claim 2,
A plurality of register circuits connected in series at a subsequent stage of the second register circuit so as to capture the output of the preceding register circuit at the same time as capturing the output of the second register circuit; A second register circuit; and a second majority circuit that receives outputs of the plurality of register circuits as inputs and determines an output signal to the state transition circuit.

The clock control circuit according to a fifth aspect of the present invention is the clock control circuit according to the second aspect,
The clock selection circuit is configured to determine whether to stop the clock signal output to the slave circuit based on the past communication state of the state transition circuit.

The clock control circuit according to claim 6 of the present invention is the clock control circuit according to claim 2,
The communication monitoring circuit includes a mode setting register for stopping a communication monitoring function, and all the circuit operations are stopped by the mode setting register so that all output signals are set to a specific state. The clock control circuit according to claim 7 of the present invention is the clock control circuit according to claim 3 or claim 4.
In the clock control circuit described above, the number of the register circuits added after the first or the second register circuit can be changed according to the number of communication histories of the main circuit and the slave circuit. It was made.

[0014]

Embodiments of the present invention will be described below. (Embodiment 1) A clock control circuit according to a first embodiment of the present invention, which corresponds to claims 1, 2, and 5, will be described with reference to the drawings. FIG. 1 shows the first embodiment.
FIG. 2 is a block diagram showing a configuration of a clock control circuit according to the first embodiment.

The clock control circuit 100 according to the first embodiment
Comprises a communication monitoring circuit 12 and a clock selection circuit 13. Since communication is performed by the handshake method, an RQST signal and an RDY signal are provided between two circuits of the main circuit 10 and the sub circuit 11 in addition to an original data line (not shown).
The signal is connected. The communication monitoring circuit 12 is a circuit added according to the present invention, and receives, in addition to the RQST signal and the RDY signal, a clock signal CLKM input to the main circuit and a clock signal CLKS input to the sub circuit. This clock signal CLKS has been directly input to the slave circuit in the conventional example. This communication monitoring circuit 12
Outputs a SEL signal for selecting one of a plurality of clocks having different frequencies and a DEN signal for stopping CLKD during a period other than the communication period to the clock selection circuit 13 as control signals. The clock selection circuit 13 also
A circuit added according to the present invention, the clock signal CL
The KS signal, the DEN signal, and the SEL signal are input, and the clock signal CLKD for the slave circuit is output to the slave circuit 11.

FIG. 2 is a block diagram showing the configuration of the communication monitoring circuit in the clock control circuit according to the first embodiment. The communication monitoring circuit in the clock control circuit according to the first embodiment is composed of a first counter circuit. 20, a first comparison circuit 21, a first register circuit 22, a second counter circuit 23, a second comparison circuit 24, a second register circuit 25, an up-down counter circuit 26, Inverter circuits 27 and 28 and combination circuits 29 and 2
A, 2B.

Next, the operation of the communication monitoring circuit in the clock control circuit will be described. First counter circuit 2
0 is the clock signal CLK while the RQST signal is “1”.
The number of M clocks is counted and reset at the rising edge of the RDY signal. The first comparison circuit 21 compares the output S20 of the first counter circuit 20 with the set value M, and when the output S20 of the counter circuit 20 is large, the output S21
Is output, and otherwise, "0" is output to its output S21. The first register circuit 22 has the RDY
The output S21 of the first comparison circuit 21 is taken in at the rise of the signal. The second counter circuit 23 outputs RD
An inverter circuit 2 that counts the number of clocks of the clock signal CLKS while the Y signal is “1” and inverts the RQST signal
7 is reset at the rise of the output S27. The second comparison circuit 24 outputs the output S23 of the second counter circuit 23.
Is compared with the set value S. If S23 of the counter circuit 23 is large, "1" is output to its output S24, otherwise, "0" is output to its output S24. The second register circuit 25 takes in the output S24 of the second comparison circuit 24 at the rise of the output S27 of the inverter 27. As the state transition circuit, an up / down counter circuit 26 is used. When the output S22 of the first register circuit 22 is “1”, the up / down counter circuit 26 counts up, and
In step 9, when the output S29 generated by the logical product of the output S25 of the register circuit 25 and the inverted signal of the output S22 of the first register circuit is "1", the countdown is performed. The SEL signal and S26 output from the up / down counter circuit 26 are signals determined by decoding the state of the counter circuit 26. Two combination circuits 2A and 2B
Is one output S26 of the up / down counter circuit 26.
Is an additional circuit for outputting "1" to the DEN signal when both the RQST signal and the RDY signal are "0" (in a state of no communication). The communication monitoring circuit 12 and a clock selection circuit 13 described later realize a “configuration in which a clock signal supplied to a slave circuit is stopped according to the state of the state transition circuit”.

Hereinafter, the operation of the communication monitoring circuit of FIG. 2 will be described in more detail. The output S20 of the first counter circuit 20 becomes RD after the RQST signal becomes “1”.
The number of clocks input to the clock signal CLKM line during the period until the Y signal becomes “1” (the period A described above) is counted, and the number of the output S21 of the first comparison circuit 21 is set. Indicates whether it was greater than the value. The state of the up / down counter circuit 26 corresponds to executing a control for increasing the clock frequency of the slave circuit 11 when the count value is larger by the clock selection circuit 13 described later. When the output S22 of the first register circuit 22 is "1", it means that the waiting time of the main circuit 10 is long, so that the next communication is controlled so that the clock frequency of the slave circuit 11 is increased by one step. You. This is presumed to be effective for improving the communication efficiency in the next communication. Output S of second count circuit 23
Reference numeral 23 denotes a clock signal C during a period (period B) from when the RDY signal becomes “1” to when the RQST signal becomes “0”.
The number of clocks input to the LKS line is counted, and the output S24 of the second comparison circuit 24 indicates whether or not the number is greater than a set value. Second
When the output S25 of the register circuit 25 is "1", the up / down counter circuit 26 is counted down. Since "1" appearing in the output S25 of the register circuit 25 means that the waiting time of the slave circuit 11 is long, even if the clock frequency of the slave circuit 11 is lowered by one step in the next communication, the communication efficiency is affected. It is assumed that it is small. In this case, it is expected that the power consumed by the clock line of the slave circuit 11 will surely decrease. However, even when the output S25 of the register circuit 25 is "1", if the output S22 of the register circuit 22 is "1", the request from the main circuit 10 (communication efficiency) is obtained by the combination circuit 29.
, And the up / down counter circuit 26 is controlled to count up.

Next, a clock selection circuit in a clock control circuit according to claim 1 or 5 of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the clock selection circuit in the clock control circuit according to the first embodiment. The clock selection circuit in the clock control circuit according to the first embodiment includes register circuits 50, 5
1, 52, 53, 54, 55 and 56 and combination circuits 57, 58, 59, 5A, 5B, 5C, 5D, 5E, 5
F, 5G, 5H, 5I, 5J, 5K, 5L, 5M, 5N
And 5O.

The operation of the clock selection circuit shown in FIG. 5 will be described below. The register circuits 50 to 56 include the slave circuit 1
The clock CLKS for one is connected so as to divide the frequency of the clock CLKS by two in succession to form a ripple counter circuit. The combination circuits 57 to 5E are connected to each other so as to decode the 3-bit SEL signal and output “1” to any one of the eight output S57 to S5E signals, thereby forming a decoder circuit. The combination circuits 5F to 5M and the combination circuit 50 output the output S
A selection circuit is configured to select a clock signal in accordance with the signal which becomes "1" among the signals 57 to S5E, and to guide the selected signal to the clock signal CLKD line. Further, the combination circuit 5N is configured to fix the clock signal CLKD line to “0” when the DEN signal is “1”. The RST signal serves as an initial reset signal for setting an initial state of the ripple counter circuit. With this clock selection circuit, it is possible to control the CLDK signal corresponding to the output signal DEN signal and the SEL signal from the communication monitoring circuit 12 described above.

As described above, according to the clock control circuit of the first embodiment, the up-down counter circuit 26
State corresponds to control for increasing the clock frequency of the slave circuit 11 when the count value is larger by the clock selection circuit,
When the output S22 of the first register circuit 22 is "1", it means that the waiting time of the main circuit 10 is long, so that the next communication is controlled so that the clock frequency of the slave circuit 11 is increased by one step. You. Thereby, the communication efficiency in the next communication can be improved. The output S23 of the second counter circuit 23 is a period (period B) from when the RDY signal becomes "1" to when the RQST signal becomes "0".
The number of clocks input to the clock signal CLKS line is counted, and the output S24 of the second comparison circuit 24 indicates whether or not the number is greater than a set value. The output S25 of the second register circuit 25 is "1"
In this case, the up / down counter circuit 26 counts down. Since "1" appearing in the output S25 of the second register circuit 25 means that the waiting time of the slave circuit 11 is long, the communication efficiency is reduced in the next communication even if the clock frequency of the slave circuit 11 is lowered by one step. Has little effect. Thus, the power consumed by the clock line of the slave circuit 11 can be reliably reduced.

That is, by controlling the clock frequency of the slave circuit to the optimum state in response to the past communication state, the master circuit 10 and the slave circuit 11 that perform communication by the handshake method are controlled. The power consumed by the clock line of the slave circuit 11 can be reduced without affecting the processing performance.

(Embodiment 2) Next, a clock control circuit according to a second embodiment of the present invention corresponding to claims 1, 2, 3, 4, and 7 of the present invention will be described. FIG. 3 is a block diagram showing a configuration of the communication monitoring circuit 12 in the clock control circuit 100 according to the second embodiment.
Has first and second majority circuits 3C and 3F and register circuits 3A, 3B, 3D and 3E, and the signals on the respective outputs S30 to S39 are output from the respective output S20 in FIG.
This is equivalent to the signals on lines S29 to S29. Other configurations are the same as those of the communication monitoring circuit according to the first embodiment, and a description thereof will not be repeated.

Next, the operation will be described. The register circuit 3A and the register circuit 3B newly added to the subsequent stage of the register circuit 22 provide an output S3A of the register circuit 3A.
And the output S3B of the register circuit 3B holds a state corresponding to the length of the period A in the communication two times before and two times before. The first majority circuit 3C outputs the outputs S32, S3A, S3B of the register circuits 22, 3A, 3B.
Any two or more of the three signals obtained from
If so, "1" is output to the output S3C, and otherwise, "0" is output to the output S3C.

A register circuit 3D and a register circuit 3E are newly added at the subsequent stage of the register circuit 25. With this configuration, the output S3D of the register circuit 3D and the output S3E of the register circuit 3E are respectively provided two times before and two times before. The state corresponding to the length of the period B in the communication is maintained. The second majority circuit 3F includes a register circuit 3
If any two or more of the three signals obtained from the outputs S35, S3D, S3F of 5, 3D, 3F are "1", "1" is output to the output S3F, otherwise, the output is output. "0" is output to S3F. The number of register circuits added after the register 22 and the register circuit 25 can be changed according to the number of communication histories of the main circuit 10 and the slave circuit 11.

As described above, according to the communication monitoring circuit in the clock control circuit of the second embodiment, the state of the up / down counter circuit 26 is not changed by only the immediately preceding communication state, but is changed by the past. It is possible to determine whether to change the clock frequency in consideration of the three communication states. When the state of the up / down counter circuit 26 is changed by the output S3G of the combinational circuit 3G having the output S3C of the first majority circuit 3C and the output S3F of the second majority circuit 3F as inputs, the register circuits 22, 3
A, 3B, 25, 3D, 3E will be reset. This corresponds to the fact that when the clock frequency of the slave circuit is changed, the communication history acquired in the communication state performed at the clock frequency before the change becomes meaningless.

In the description of the communication monitoring circuit in the clock control circuit according to the second embodiment, the number of times that the past communication state is considered is set to three times for the waiting time (period A) of the main circuit.
The number of times of the past communication history is changed by changing the number of additional register circuits according to the number of communication histories to be considered. Can be changed, and if the number of additional register circuits is increased, the past communication history can be referred to more deeply, and hysteresis can be provided for clock selection.

(Third Embodiment) Next, a clock control circuit according to a third embodiment of the present invention, which corresponds to claims 1, 2, and 6, will be described. FIG. 4 is a block diagram showing a configuration of the communication monitoring circuit 12 in the clock control circuit 100 according to the third embodiment. The communication monitoring circuit 12 according to the third embodiment includes a register circuit 4A for setting a mode, Combination circuits 4C, 4D, 4E, 4
F and 4H, and the signal of each output line S40 to S49 is equivalent to the signal of each output line S20 to S29 in FIG. Other configurations are the same as those of the communication monitoring circuit according to the first embodiment, and a description thereof will not be repeated.

Next, the operation will be described. When "0" is set in the register circuit 4A, the outputs S4C, S4 of the combinational circuits 4C, 4D, 4E, 4F through the output S4A.
The D, S4E, and S4F signals are all fixed at "0", and the circuits subsequent to these stop all operations.
The DEN signal is fixed at "0" by the combination circuit 4G, and the SEL signal is fixed at "1" by the combination circuit 4H. By these settings, the clock signal supplied under the control of the clock selection circuit described later is fixed to the same state as in the conventional example, and the main circuit 10 and the sub circuit 11
Communication between them is performed in the same manner as in the conventional example. In this mode,
In the communication monitoring circuit 12, the combinational circuits 4C, 4D, 4E,
Since the output S4C, S4D, S4E, and S4F signals of the 4F are fixed, they are added to the communication monitoring circuit, so that no extra power is consumed.

As described above, according to the communication monitoring circuit in the clock control circuit of the third embodiment, the clock signal supplied to the slave circuit is fixed to the state before the present invention is implemented, and the main circuit and the slave circuit are fixed. Is performed in the same manner as in the prior art. In this mode, the communication monitoring circuit uses S4C / S4D
Since the S4E and S4F are fixed, no extra power is consumed by a circuit newly added to the communication monitoring circuit.

[0031]

As described above, according to the clock control circuit of the present invention, the clock frequency of the slave circuit is adjusted for the main circuit and the slave circuit that perform communication by the handshake method according to the past communication state. By controlling to an optimal state, it is possible to reduce the power consumed by the clock line of the slave circuit without affecting the processing performance of the master circuit.

When communication is performed such that the period B becomes longer, the frequency of the clock signal input to the slave circuit is reduced, thereby reducing the power consumed by the clock line of the slave circuit. After that, if the communication in which the period A becomes longer due to the operation state of the main circuit occurs and it is recognized that the processing in the sub-circuit is required to be completed quickly, the clock frequency of the sub-circuit is changed. By returning to a higher frequency, the processing performance of the main circuit can be prevented from being affected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock control circuit according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a communication monitoring circuit in the clock control circuit according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a communication monitoring circuit in the clock control circuit according to the second embodiment.

FIG. 4 is a block diagram showing a configuration of a communication monitoring circuit in the clock control circuit according to the third embodiment.

FIG. 5 is a block diagram showing a configuration of a clock selection circuit in the clock control circuit according to the first embodiment.

FIG. 6 is a block diagram illustrating a configuration of a digital circuit that performs communication by a handshake method.

7 is a timing chart showing an operation state when the digital circuit shown in FIG. 6 is clock-controlled using a conventional clock control circuit.

[Explanation of symbols]

10, 60 main circuit 11, 61 slave circuit 12 communication monitoring circuit 13 clock selection circuit 20 first counter circuit 21 first comparison circuit 22 first register circuit 23 second counter circuit 24 second comparison circuit 25th 2 register circuit 26 up / down counter circuit 27, 28 inverter circuit 29, 2A, 2B, 37, 38, 39, 3G, 47, 4
8, 49, 4B, 4C, 4D, 4E, 4F, 4G, 4
H, 57, 58, 59, 5A, 5B, 5C, 5D, 5
E, 5F, 5G, 5H, 5I, 5J, 5K, 5L, 5
M, 5N, 50 combination circuit 3C first majority circuit 3F second majority circuit 3A, 3B, 3D, 3E, 4A, 50, 51, 52, 5
3, 54, 55, 56 register circuit 100 clock control circuit

Claims (7)

[Claims] A clock control circuit for controlling a clock of a digital circuit including a main circuit and a slave circuit for performing communication by a handshake method, comprising: a processing request signal (hereinafter referred to as RQS) output from the main circuit.
T signal), a processing completion signal (hereinafter abbreviated as RDY signal) output from the slave circuit, a clock signal for the main circuit (hereinafter abbreviated as CLKM), and a clock signal for the slave circuit. (Hereinafter, abbreviated as CLKS), a communication monitoring circuit that monitors a communication state between the main circuit and the sub-circuit based on these signals, and outputs a control signal according to the communication state. According to a control signal output by the communication monitoring circuit, the CLKS signal is output to the slave circuit as it is, a clock signal having a frequency different from the CLKS signal is output, or a clock signal is output to the slave circuit. And a clock selection circuit for stopping the operation of the clock control circuit. 2. The clock control circuit according to claim 1, wherein the communication monitoring circuit is configured to control the CLKM signal while the RQST signal is in a valid state.
A first counter circuit for counting the number of changes of the first counter circuit, a first comparator circuit for comparing an output value of the first counter circuit with a preset value, and when the RDY signal changes from an invalid state to a valid state. A first register circuit that captures the output of the first comparison circuit; a second counter circuit that counts the number of changes in CLKS while the RDY signal is in a valid state; A second comparison circuit that compares the output value with a preset value; a second register circuit that captures an output of the second comparison circuit when the RQST signal changes from a valid state to an invalid state; When the RDY signal changes from a valid state to an invalid state, a transition is made to the next state by the output of the first register circuit and the output of the second register circuit. And a state transition circuit for determining an output signal to the selection circuit, wherein the clock control circuit. 3. The clock control circuit according to claim 2, wherein said communication monitoring circuit outputs an output of a preceding register circuit to a subsequent stage of said first register circuit at the same time as receiving an output of said first register circuit. A plurality of register circuits connected in series so as to take in, a first majority circuit that receives the outputs of the first register circuit and the plurality of register circuits as inputs, and determines an output signal to the state transition circuit; A clock control circuit, further comprising: 4. The clock control circuit according to claim 2, wherein said communication monitoring circuit outputs an output of a preceding register circuit to a subsequent stage of said second register circuit at the same time as receiving an output of said second register circuit. A plurality of register circuits connected in series so as to take in, a second majority circuit which receives the outputs of the second register circuit and the plurality of register circuits as inputs, and determines an output signal to the state transition circuit; A clock control circuit, further comprising: 5. The clock control circuit according to claim 2, wherein the clock selection circuit determines whether or not to stop a clock signal output to the slave circuit from a past communication state of the state transition circuit. A clock control circuit, characterized in that: 6. The clock control circuit according to claim 1, wherein the communication monitoring circuit includes a mode setting register for stopping a communication monitoring function, and the mode setting data set in the mode setting register. A clock control circuit, which stops all circuit operations and sets all output signals to a specific state. 7. The clock control circuit according to claim 3, wherein the number of said register circuits added after said first or second register circuit is equal to each of said main circuit and said sub-circuit. A clock control circuit, which can be changed according to the number of communication histories.