JP2003046596A - Network interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a network interface for decreasing power consumption. SOLUTION: This invention provides the network interface, in which it has an active mode and at least one of a disconnect mode and a suspend mode, and performs a predetermined, process, when a setting condition and a release condition of the disconnect mode or the suspend mode are satisfied. The network interface includes a drive control circuit for stopping at least a part of drive clock generation circuits included in the network interface, until the release condition of the disconnect mode or the suspend mode is satisfied, starting from the time when the disconnect mode or the suspend mode is established, where the drive control circuit operates irrespective of the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network interface having at least one of a disconnect mode and a suspend mode in addition to an active mode.

[0002]

2. Description of the Related Art IEEE139 as a high-speed bus system
The 4-bus system is standardized. IEEE 1394
The bus system is a serial bus system, and IEEE1394. An electronic device including an interface board (hereinafter, simply referred to as an IEEE board) conforming to the standard a is connected by a standard cable (hereinafter, simply referred to as an IEEE cable) conforming to the IEEE 1394 standard. The IEEE cable adopts a twisted pair cable including two sets of two twisted wires through which a differential signal flows.

In addition to the active mode, the IEEE board defines a disconnect mode and a suspend mode. The active mode is a mode set when exchanging information such as packet data with the opposite node. The disconnect mode is a mode set when the opposing node is not connected. The suspend mode is a mode set when opposing nodes are connected but packet data is not exchanged between electronic devices connected to each other.

The setting of the active mode and the suspend mode is executed in the PHY chip of the IEEE board. The PHY chip is roughly divided into a cable I / F and a digital control unit that processes a signal output from the cable I / F.

Cable I / F provided on the IEEE board
In addition to the transmission / reception data, a connection detection signal that becomes an asserted state (Low) when the opposite node is connected, and an asserted state (High level) when exchanging packet data.
Various signals including the Bias_detection signal of h) are output to the digital control unit.

The digital control unit sets the disconnect mode, the suspend mode, and the active mode according to the values of the connect detection signal and the Bias_detection signal. Specifically, when the connect detection signal is in the negated state, the disconnect mode is set, and the functions other than the function of executing the mode changing process in response to the change of the connect detection signal are stopped.

Further, the digital control unit sets the suspend mode when the Bias_detection signal remains negated and the connect detect signal switches to the asserted state, and changes the connect detect signal and the Bias_detector signal. The functions other than the function that executes the mode change process are stopped. If the connect detection signal is switched to the negate state when the suspend mode is set, the disconnect mode is entered. On the other hand, when the Bias_detection signal switches to the asserted state, it shifts to the active mode and operates all the functions other than the function of processing the connect detection signal.

[0008]

[Problems to be Solved by the Invention]
4. The suspend mode provided in the interface board conforming to the standard a is for reducing the power wasted by each IEEE board when information such as packet data is not exchanged between electronic devices connected by the IEEE cable. It is a mode provided in.

However, even when the suspend mode is set, the clock signal generator in the IEEE board, especially in the PHY chip, continues to operate. Inside the PHY chip, high-speed data processing up to 400 Mbps is performed. Correspondingly, the clock signal generation circuit generates a clock signal with a very high frequency, but generation of the clock signal with a high frequency involves a lot of power consumption.

To save power, the clock signal generator may be stopped. However, if the clock signal generator also stops when the suspend mode is set, all the signal processing functions in the PHY chip including the processing of the connect detection signal detected in the cable I / F will stop. For example, even when the electronic device is detached from the IEEE cable, the transition process from the suspend mode to the disconnect mode cannot be executed. Further, even if information such as packet data is transmitted from the opposing electronic device, it cannot be detected, and there is a problem that the active mode cannot be entered.
The same problem occurs even if the clock signal generator is stopped when the disconnect mode is set.

The present invention provides an interface board typified by an IEEE board, in particular, which provides a network interface having a function of more effectively reducing power consumption at the time of setting a disconnect mode or a suspend mode. To aim.

[0012]

A first network interface according to the present invention has at least one of a disconnect mode and a suspend mode in addition to an active mode, and has a setting condition for the disconnect mode or the suspend mode. A network interface that executes processing according to a planned protocol when the release condition is satisfied, operates without depending on the clock signal, and satisfies the release condition of the mode from the setting of the disconnect mode or the suspend mode. Until then, a drive control circuit for stopping at least a part of the drive clock generation circuit included in the network interface is provided.

A second network interface of the present invention is the above-mentioned first network interface, wherein the drive control circuit changes a state with an opposite node (node connection, disconnection, start of packet data exchange, etc.). Event detection circuit that detects the occurrence of an event, and at least a part of the drive clock provided in the network interface from the setting of the disconnect mode or the suspend mode until the event detection circuit detects the occurrence of the event. And a clock control circuit for stopping the circuit.

A third network interface of the present invention is the second network interface, wherein the event detection circuit outputs a state change with the opposite node or a state change of a predetermined signal inside the network interface. Is detected as occurrence of.

A fourth network interface of the present invention is the same as the second network interface according to the IEEE 1394. According to the standard a, the event detection circuit detects a connection detection signal detected by a connection detection circuit included in the cable I / F, and a B detected by a Bias detection circuit included in the cable I / F.
detecting the occurrence of an event based on a change in at least one of the ias signals.

According to a fifth network interface of the present invention, in the fourth network interface, the event detection circuit includes a connection detection signal detected by a connection detection circuit included in the cable I / F, and the cable I / F. An event is detected based on a change in at least one of the Bias signal detected by the Bias detection circuit and the LPS signal output from the LINK chip.

The computer of the present invention has at least one of a disconnect mode and a suspend mode in addition to the active mode, and is planned when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A computer equipped with a network interface that executes processing according to a protocol, operates independently of a clock signal, and operates from the setting of the disconnect mode or suspend mode until the condition for canceling the mode is satisfied. A drive control circuit for stopping at least a part of the drive clock generation circuit included in the interface is provided.

The printer of the present invention has at least one of a disconnect mode and a suspend mode in addition to the active mode, and is planned when the setting condition and the cancel condition of the disconnect mode or the suspend mode are satisfied. A printer having a network interface that executes processing in accordance with a protocol, operates without depending on a clock signal, and operates from the setting of the disconnect mode or suspend mode until the condition for releasing the mode is satisfied. A drive control circuit for stopping at least a part of the drive clock generation circuit included in the interface is provided.

The storage device of the present invention has at least one of a disconnect mode and a suspend mode in addition to the active mode, and is planned when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A storage device equipped with a network interface that executes processing according to the protocol of 1, operating independently of a clock signal, until the condition for releasing the disconnect mode or suspend mode to the mode is satisfied.
A drive control circuit for stopping at least a part of the drive clock generation circuit included in the network interface is provided.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION (1) Outline of the Invention The network interface of the present invention has at least one of a disconnect mode and a suspend mode in addition to the active mode, and a condition for canceling the disconnect mode or the suspend mode. Is satisfied, a network interface that executes a boot process according to a predetermined protocol, for example, IEEE1394. a network interface compliant with the standard a, which operates independently of a clock signal, and stops at least a part of the drive clock generation circuit provided in the network interface according to the setting of the disconnect mode or the suspend mode, A drive control circuit is provided for reactivating the stopped clock generation circuit when a condition for canceling the disconnect mode or the suspend mode is satisfied.

By adopting the above configuration, it is possible to reduce the waste of power in the clock signal generation circuit and effectively reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

Hereinafter, the network interface of the present invention having the above characteristics will be referred to as IEEE1394. An embodiment applied to the bus system a) will be described with reference to the accompanying drawings.

(2) Embodiment FIG. 1 shows an embodiment of a network interface of the present invention, IEEE1394. Interface board compliant with a (hereinafter simply referred to as IEEE board) 1
A host computer 100 including a printer and a printer 500 equipped with the same or different IEEE boards.
E1394. Standard cable conforming to a (hereinafter referred to as IEEE
It is called E cable. ) Is a diagram showing a configuration of a network connected by 150).

When the power of the computer 100 and the printer 200 is turned on, each IEEE board is
394. The network recognition processing is executed according to the protocol standardized in a.

In this figure, the IEEE board 1 is described as connecting the computer 100 and the printer 500, but the interface board can be applied to other devices such as a storage device and a digital video camera. it can. For example, a storage device including the interface board 1 can be connected to the computer 100. The storage device may be, for example, a hard disk or a CD.
/ DVD drive and MO drive.

<2-1> IEEE Board The IEEE board 1 included in the computer 100 will be described below. FIG. 2 is a configuration diagram showing a part of the internal circuit of the computer 100, particularly a part relating to the IEEE board 1 which is an embodiment of the interface of the present invention. The IEEE board 1 is connected to the PCI bus 6. The PCI bus 6 is connected to the computer 1 via a chip set (motherboard) 7 in addition to the IEEE board 1.
A central processing unit (CPU) 8 of the main unit 00 is connected.

The IEEE board 1 is a PHY chip 2, L
INK chip 3, OHCI (OpenHost Controller Inte
abbreviation of rface) PCI I / that operates according to Version 1.1
It is composed of an F control circuit 4 and a PCI register 5.

The IEEE board 1 defines a disconnect mode and a suspend mode in addition to the active mode which is set when exchanging information such as packet data with the printer 500. The disconnect mode is a mode set when the printer 500 is not connected to the IEEE cable 150. What is suspend mode? IEEE cable 1
This is a mode set when the printer 500 is connected to the printer 50 but packet data is not exchanged.

In the suspend mode, the CPU 8
Chipset 7, PCI bus 6, PCI I /
The control signal input to the PHY chip 2 via the DMA 4a of the F control circuit 4 and the LINK chip 3, specifically, the D3 state setting output by the driver for power saving control conforming to the PCI Power management standard. It is also set according to the signal.

In the above PCI Power management standard, D
The recovery time specified for the three states is 10 ms. As will be described in detail below, the IEEE board 1 is in the suspend mode, but it takes time to recover.
It is possible to set the sleep mode in which the power saving effect is maximized by completely stopping the clock generation mechanism including the PLL circuit. However, even when the sleep mode is selected, the time required to stably operate the clock generation mechanism again is about several hundred μs to several ms.
The suspend mode release processing can be completed within the above-specified recovery time. Like this, IEEE board 1
Secures high versatility by eliminating the need to define a special protocol when using it.

The active mode, disconnect mode, and suspend mode are set in the PHY chip 2 of the IEEE board 1. The PHY chip 2 is roughly composed of a cable I / F 11 and a digital control unit 20 that processes a signal output from the cable I / F 11.

The cable I / F 11 is in the assert state (High) when exchanging the transmission / reception data, the connect detection signal which becomes the assert state (Low) when the printer 500 which is the opposite node is connected, and the packet data.
And outputs various signals including the Bias_detection signal to the digital control unit 20.

The digital control unit 20 sets the disconnect mode, the suspend mode, and the active mode according to the values of the connect detection signal and the Bias_detection signal. FIG. 3 is a diagram for explaining the transition of modes. When the connect detection signal detected by the cable I / F 11 is in the negate state, the digital control unit 20 sets the disconnect mode. If the Bias_detection signal remains negated and the connect detection signal switches to the asserted state, the suspend mode is set. When the Bias_detection signal is switched to the asserted state when the suspend mode is set, the mode shifts to the active mode. On the contrary, if the Bias_detection signal switches to the negated state when the active mode is set, the suspend mode is set. If the connect detection signal switches to the negate state during the setting of the suspend mode, the disconnect mode is set.

The IEEE board 1 will be described with reference to FIG. 2 again. The IEEE board 1 has two suspend modes selectable by the BIOS 7a included in the chipset 7. The two suspend modes are a dose mode and a sleep mode.

In the dose mode, the PHY chip of the IEEE board 1 is set to IEEE1394. In addition to setting the disconnect mode or the suspend mode conforming to the standard a, the clock generating mechanism in the PHY chip is partially stopped so that unnecessary power is not consumed in the clock generating mechanism when the mode other than the active mode is set. It is a mode that reduces consumption, and is inferior in power saving efficiency to the sleep mode described below, but is characterized by quick restart. For example, time to return (several hundred μs to several m
By stopping / restarting the clock generation mechanism other than the PLL circuit requiring s), the restart processing can be set to be completed within the recovery time (200 μs) of the D2 state conforming to the PCI Power management standard. .

In the sleep mode, the IEEE board 1 is used.
PHY chip of IEEE1394. This is a mode in which the clock generation mechanism inside the PHY chip is completely stopped at the same time as setting to the disconnect mode or the suspend mode conforming to the standard a. It is the most useless power consumption when the mode other than the active mode is set. The feature is that it can be suppressed. However, for the convenience of completely stopping the clock generation mechanism, for example, a fixed time (several hundred μs to several m) is required to generate a clock signal with a stable frequency.
s) is required.

A computer 10 is provided in the chipset 7.
BIOS that defines the contents of the initial settings to be executed when 0 is started
7a is provided, and by selecting the data in the BIOS 7a, it is possible to set which of the sleep mode and the doze mode is used as the suspend mode when the computer 100 is started up. The setting is made by the PCI I / F when the computer 100 is started.
It is stored as a 2-bit suspend mode setting signal in the PCI register 5 via the control circuit 4.

The PCI register 5 outputs the lower 1 bit of the stored 2-bit suspend mode setting signal to the PHY chip 2 as the sleep mode setting signal and the upper 1 bit as the dose mode setting signal PHY.
Output to chip 2. These two signals have exclusive values, and when one is "H" (meaning setting), the other is set to "L" (meaning canceling). That is, when the sleep mode is executed as the suspend mode, the sleep mode setting signal is set to "1" and the dose mode setting signal is set to "0". When setting the doze mode, the sleep mode setting signal is set to "0" and the doze mode setting signal is set to "1".

<2-2> PHY Chip FIG. 4 is a diagram showing a detailed configuration of the PHY chip 2.
The PHY chip 2 is roughly divided into an analog block 1
0, digital controller 20, and clock generator 30
Composed of.

The analog block 10 is a cable I / F.
11, a reference voltage / current source 12 for driving the cable I / F 11, a PLL circuit 13, and a reference clock transmission source 14.

The reference clock source 14 is a so-called oscillator, and has a low frequency reference clock signal XCLK.
To occur. The PLL circuit 13 uses the clock signal XC
LK is multiplied to generate a clock signal PLLCLK having a high frequency (usually 400 MHz). Clock generation unit 30
Divides the clock signal PLLCLK to generate several types of drive clock signals CLK used in the digital control unit 20. Digital control unit 20
Operates on the basis of the several types of drive clocks CLK, and stops its operation when the input of the various types of drive clock signals CLK is stopped. The clock generation unit 30 operates when the CLKENB signal from the digital control circuit 20 is “L”, and stops the operation when the CLKENB signal is “H”. The PLL circuit 13 is the digital control circuit 2
It operates when the PLLENB signal from 0 is "L", and stops the operation when the PLLENB signal is "H".

The digital control section 20 comprises an event detection circuit 21, a dose mode control circuit 22, a sleep mode control circuit 23, an OR gate 24, and an arbitration / encoding / decoding section 25.

The event detection circuit 21 outputs an "H" event signal when the state (mode) of the IEEE board 1 changes. The event detection circuit 21 will be described later in detail.

The dose mode control circuit 22 uses the BIOS 7
It operates when the doze mode is set as the suspend mode by the setting of a, and when the suspend mode is set, the CLKENB signal is switched from "L" to "H" to stop the operation of the clock generation unit 30. When the suspend mode release condition is satisfied, that is, the event signal output from the event detection circuit 21 and the LPS (Link Power) output from the LINK chip 3 are satisfied.
ER Status) signal, the CLKENB signal is returned from “H” to “L” and the clock generation unit 30 is operated again. The LPS signal is a signal indicating whether or not the LINK chip 3 is in the normal operating state, and is set to "H" when the LINK chip 3 is operating. The dose mode control circuit 22 will be described later in detail.

The sleep mode control circuit 23 uses the BIOS.
When the sleep mode is set as the suspend mode by the setting of 7a, C operates to output to the clock generation unit 30 when the suspend mode is set.
LKENB signal and PL output to the PLL circuit 13
The LENB signals are both switched from "L" to "H" to stop the operations of the clock generation unit 30 and the PLL circuit 13. On the other hand, when the suspend mode is released, that is, the event signal output from the event detection circuit 21 and the LIN
According to the change of the LPS signal output from the K chip 3, the CLKENB signal and the PLLENB signal are changed from “H” to “H”.
The clock generator 30 and the PLL circuit 1 are returned to L ″.
3 is operated again. The sleep mode control circuit 23
Will be described in detail later.

The OR gate 24 is a gate for adjusting the CLKENB signal output from the dose mode control circuit 22 and the sleep mode control circuit 23, and outputs the output from the control circuit in an effective mode. CLK
The ENB signal is output to the clock generation unit 30. In addition, the sleep mode control circuit 23 keeps the PLL circuit which is “L” with respect to the PLL circuit 13 when the dose mode is set.
Output the ENB signal.

The arbitration / encoding / decoding section 25 operates based on several kinds of drive clock signals prepared by the clock generating section 30, and the IEEE 139
4. Cable I / of analog block 10 according to a
The transmission / reception data output from F11 is processed, and the processed data is output to the LINK chip 3.

<2-3> Cable I / F FIG. 5 shows the basic configuration of the cable I / F 11, the IEEE cable 150 composed of twisted pair lines, and the cable I / F of the printer 500 which is the opposite node.
It is a figure which shows 510. The cable I / F 11 is roughly divided into a connection detection circuit 111, a Bias_ detection circuit 112, a TpBias detection circuit, and a transmission / reception circuit.

The connect detection circuit 111 is connected to the printer 50.
0 is connected to or detached from the IEEE cable 150. TPA and TPA * of the IEEE cable 150.
The connection detection signal is output based on the change in the potential difference between the twisted lines. That is, the "L" connect detection signal is output when the printer 500 is connected to the IEEE cable 150, and the "H" connect detection signal is output when the printer 500 is removed from the IEEE cable 150.

Further, the Bias_detection circuit 112 outputs a Bias_detection signal of "H" when it detects a Bias signal applied to the cable when exchanging information such as packet data, and outputs the Bias_detection signal. When no signal is output ”
The Lias Bias_detection signal is output. The configuration of the cable I / F 11 complies with the IEEE 1394.a standard, and a detailed description thereof will be omitted.

<2-4> Event Detection Circuit FIG. 6 is a diagram showing the configuration of the event detection circuit 21.
The event detection circuit 21 has three 2-input AND gates 2.
11 to 213 and one 3-input OR gate 214. A connect detection signal is input to one input terminal of the AND gate 211 via an inverter,
A disconnect signal which is set to "H" when the disconnect mode is set is input to the other input terminal. The connection detection signal is input to one input terminal of the AND gate 212, and the suspend signal set to "H" when the suspend mode is set is input to the other input terminal. The suspend signal is input to one signal input terminal of the AND gate 213, and the Bias_detection signal is input to the other input terminal. The output terminals of the AND gates 211 to 213 are all OR gates 21.
4 is connected to the input terminal.

In the event detecting circuit 21 having the above-mentioned configuration, when the disconnect mode and the suspend mode are set in the digital controller 20, the event signal of "L" is output. When setting the disconnect mode,
When the printer 500, which is an opposite note, is connected, that is, when the connect detection signal is switched from “H” to “L”, the event signal is switched from “L” to “H”. Further, when the printer 500 is detached when the suspend mode is set, that is, when the connect detection signal is switched from “L” to “H”, or information such as packet data is exchanged with the printer 500. When the exchange is started, that is, when the Bias_detection signal switches from “L” to “H”, the event signal switches from “L” to “H”.

When the IEEE board 1 has a plurality of ports, that is, when a plurality of cable I / Fs are included, the event detection circuits 21 are provided in a one-to-one correspondence with these cable I / Fs, and AND that finds the logical product of all event signals output from the event detection circuit
A configuration may be adopted in which a gate is provided and the output of the AND gate is output as a final event detection signal. In addition, the AND gate may be configured to obtain the logical product of a part of the event signals output from each event detection circuit, depending on design convenience and need.

<2-5> Dose Mode Control Circuit The dose mode control circuit 22 functions effectively when the dose mode setting signal is “H”, and is accompanied by the setting of the disconnect mode or the suspend mode, that is, LP
When both the S signal and the event signal become "L", the CLKENB signal is switched from "L" to "H" to stop the clock generation unit 30. On the other hand, when either the LPS signal or the event signal is switched from "L" to "H", the CLKENB signal is switched from "H" to "L" to restart the clock generation unit 30. .

FIG. 7 is a diagram showing the configuration of the dose mode control circuit 22. In addition, FIG. 8 shows C in accordance with the mode change from the setting of the disconnect mode or the suspend mode.
It is a time chart showing the change of the signal state until the switching of the LKENB signal. The dose mode control circuit 22 is
It is composed of a 2-input 1-output OR gate 221, a latch 222, and an AND gate 223. OR gate 22
The LPS signal output from the LINK chip 3 is input to one input terminal of 1, and the event signal output from the event detection circuit 21 is input to the remaining input terminals. The OR gate 221 is "" when either the LPS signal or the event signal is switched to "H".
The H "signal is output to the enable terminal E of the latch 222. The reset mode RB of the latch 222 receives the dose mode setting signal, and the data input terminal D receives the signal" H ".
An H "level signal is input.

As shown in the time chart of FIG. 8, when the LINK chip 3 is not functioning and the disconnect mode or the suspend mode is set, that is, the LPS signal and the event signal are both "
In case of L ”, the RSMB signal of“ H ”is output from the latch 222. In this case, the AND gate 223
Outputs an "H" CLKENB signal.

When the exchange of data in the link is started and the LPS signal is switched from "L" to "H", or when the opposite node is connected / disconnected and the exchange of packet data is started, an event signal is transmitted. "L" to "H"
When switched to (in the case of FIG. 8), the RSMB signal output from the data output terminal QB of the latch 222 is "H".
To "L". Along with this, the CLKENB signal switches from “H” to “L” and restarts the clock generation unit 30.

<2-6> Sleep Mode Control Circuit The sleep mode control circuit 23 functions effectively when the sleep mode setting signal is “H”, and in connection with the setting of the disconnect mode or the suspend mode, that is, LP
When both the S signal and the event signal are "L", the CLKENB signal and the PLLENB signal are set to "L".
The clock generator 30 and the PL are switched from L "to" H ".
The L circuit 13 is stopped. On the other hand, when either the LPS signal or the event signal is switched from "L" to "H", first, after starting, a PLL circuit which takes time to output a clock signal of a stable frequency PLLENB signal for 13 is switched from "H" to "L"
After restarting the circuit 13, wait for the above-mentioned time required for starting the PLL circuit 13 by the timer, and then start CLKEN.
The clock generator 3 switches the B signal from "H" to "L".
Restart 0.

FIG. 9 is a diagram showing the configuration of the sleep mode control circuit 23. The sleep mode control circuit 23 includes a count circuit 231, which functions as a timer for a predetermined time.
It is composed of a flip-flop 232, a latch 235, AND gates 233 and 236, and OR gates 234 and 237.

The count circuit 231 has a plurality of flip-flops connected in series, and receives the clock signal XCLK output from the reference clock source 14 as a clock signal (enable signal). The RSM signal output from the output terminal Q of the latch 235 is input to the reset terminal RB of the count circuit 231. The count circuit 23 is connected to the clock terminal CK of the flip-flop 232.
The output QB of 1 is input, and the signal from the data output terminal D of the latch 235 is input to the reset terminal RB. A "H" signal is input to the data input terminal D. Data output terminal QB of flip-flop 232
Is connected to one input terminal of the 2-input AND gate 233. A sleep mode setting signal is input to the remaining input terminals of the AND gate 233. AND
The CLKENB signal is output from the output terminal of the gate 233.

The LPS signal is input to one input terminal of the 2-input OR gate 234, and the event signal is input to the remaining input terminals. The output terminal of the OR gate 234 is
It is input to the clock terminal CK of the latch 235. A sleep mode setting signal is input to the reset terminal RB of the latch 235, and a “H” signal is input to the data input terminal D. RSMB from the output terminal QB of the latch 235
The signal is output. The RSMB signal is input to one input terminal of the 2-input AND gate 236, and the sleep mode setting signal is input to the remaining input terminals. Two
One of the input terminals of the input OR gate 237 has the above-mentioned AN
The output terminal of the D gate 236 is connected, and the dose mode setting signal is input to the remaining input terminals. OR gate 2
The PLLENB signal is output from the output terminal of 37.

FIG. 10 shows the CLKEN according to the mode change from the setting of the disconnect mode or the suspend mode.
6 is a time chart showing changes in signal states until switching between the B signal and the PLLENB signal. When the sleep mode setting signal is set to "H", no data is exchanged in the link, and the disconnect mode or the suspend mode is set, that is, the LPS signal And event signal are both "L"
In the case of, "L" is output from the data output terminal Q of the latch 235.
RSM signal is output from the data output terminal QB
The RSMB signal of H "is output. In this case,
The "H" CLKENB signal is output from the AND gate 233, and the "H" PLLEN signal is output from the OR gate 237.
The B signal is output.

When the data exchange in the link is started and the LPS signal is switched from "L" to "H", or when the opposing node is connected / disconnected and the packet data exchange is started, the event signal is transmitted. "L" to "H"
When switched to (in the case of FIG. 10), the RSMB signal output from the data output terminal QB of the latch 235 is "
Switching from "H" to "L." Accordingly, the PLLENB signal switches from "H" to "L", and the PLL circuit 13 is restarted.

The RSM signal output from the data output terminal Q of the latch 235 switches from "L" to "H" and starts the counting circuit 231. Counting circuit 23
After the clock signals are cycled by the number of flip-flops included in 1, the CLKENB signal output from the AND gate 233 is switched from “H” to “L”, and the clock generation unit 30 is restarted. In this way, the count circuit 231 functions as a timer. The number of flip-flops included in the count circuit 231 is PL
The switching timing of CLKENB is delayed by the time required for the L circuit 13 to be activated and stable PLLCLK output to be possible.

In the IEEE board 1 described above, B
The doze mode or the sleep mode is selected as the suspend mode according to the setting of the IOS 7a. Further, a configuration is adopted in which any one of the selected modes is set in accordance with a D3 state setting signal that complies with the PCI Power management standard. However, regardless of which mode is set as the suspend mode by the BIOS 7a, the sleep mode is set according to the D3 state setting signal conforming to the PCI Power management standard, and the doze mode is set according to the D2 state setting signal. You may employ the structure which does.

[0066]

According to the first network interface of the present invention, at least a part of the clock generating circuit of the network interface is stopped when the disconnect mode or the suspend mode is set. Since the drive control circuit operates independently of the clock signal, the drive control circuit continues to operate regardless of the stop of the clock generation circuit and restarts the clock generation circuit when the mode release condition is satisfied. By adopting this configuration, it is possible to significantly reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

In the second network interface of the present invention, until the event detection circuit detects a change in the relationship with the opposing node (connection / disconnection of node, start of packet data exchange, etc.) as occurrence of an event. The clock generation circuit of at least a part of the network interface is stopped. Since the drive control circuit operates independently of the clock signal, it continues to operate regardless of the stop of the clock generation circuit, and when the event detection circuit detects a change in the relationship with the opposing node, it generates the clock. Restart the circuit. By adopting this configuration, it is possible to significantly reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

In the third network interface of the present invention, not only a change in the relationship with the opposing node (connection / disconnection of node, start of packet data exchange, etc.) due to the event detection circuit, but also a change in a predetermined internal signal causes an event. The clock generation circuit of at least a part of the network interface is stopped until it is detected as the occurrence of the above. Since the drive control circuit operates independently of the clock signal, it continues to operate regardless of the stop of the clock generation circuit, and when the event detection circuit detects a change in the relationship with the opposing node, it generates the clock. Restart the circuit. By adopting this configuration, it is possible to significantly reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

The fourth network interface of the present invention is IEEE1394. A clock that is in compliance with the standard of a and uses a circuit that is not driven by a clock signal such as a connect detection circuit provided in the cable I / F to detect that the mode release condition has been satisfied, and has stopped the clock. Restart the generator circuit. By adopting this configuration, it is possible to significantly reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

The fifth network interface of the present invention is stopped in the fourth network interface when it is judged that the mode release condition is satisfied when the LPS signal output from the LINK chip changes. Restart the clock generation circuit. By adopting this configuration, it is possible to significantly reduce the power consumption of the interface when the disconnect mode and the suspend mode are set.

The computer, printer, and storage device of the present invention are equipped with the first interface board described above, so that the power consumption of the interface when the disconnect mode and the suspend mode are set can be greatly reduced.

[Brief description of drawings]

FIG. 1 shows the IEEE 1394. It is a figure which shows an example of the network which used the bus system of a.

FIG. 2 is a diagram showing a configuration in a computer centering on an IEEE board.

FIG. 3 is a diagram for explaining mode switching.

FIG. 4 is a diagram showing a configuration of a PHY chip.

FIG. 5 is a diagram showing a configuration of a cable I / F.

FIG. 6 is a diagram showing a configuration of an event detection circuit.

FIG. 7 is a diagram showing a configuration of a dose mode control circuit.

FIG. 8 is a time chart showing signals in the dose mode control circuit.

FIG. 9 is a diagram showing a configuration of a sleep mode control circuit.

FIG. 10 is a time chart showing signals in the sleep mode control circuit.

[Explanation of symbols]

1 IEEE board, 2 PHY chips, 3 LINK
Chip, 4 PCI I / F control circuit, 4a DMA,
5 PCI registers, 6 PCI bus, 7 chipsets, 7a BIOS, 8 CPU, 11 cable I /
F, 13 PLL circuit, 14 Reference clock source, 2
0 digital control circuit, 21 event detection circuit, 2
2 dose mode control circuit, 23 sleep mode control circuit, 24 OR gate, 30 clock generation unit, 10
0 computer, 500 printers.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hironori Nakayama             1-3-3 Nakamagome, Ota-ku, Tokyo Stocks             Company Ricoh F-term (reference) 5K033 DB11 DB16                 5K034 AA15 DD03 FF12 FF19 GG06

Claims (8)

[Claims] 1. In addition to the active mode, at least one of a disconnect mode and a suspend mode is provided, and a process according to a planned protocol is performed when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A network interface to be executed, which operates independently of a clock signal, and drives at least a part of the network interface from the setting of the disconnect mode or suspend mode until the condition for releasing the mode is satisfied. A network interface comprising a drive control circuit for stopping a clock generation circuit. 2. The network interface according to claim 1, wherein the drive control circuit detects an event detection of a state change with the opposite node, and the disconnect mode or the suspend mode is set. To a clock control circuit for stopping at least a part of the drive clock generating circuit included in the network interface from the time until the occurrence of an event is detected by the event detecting circuit. 3. The network interface according to claim 2, wherein the event detection circuit detects a state change with the opposite node or a state change of a predetermined signal inside the network interface as occurrence of an event. A network interface characterized by. 4. The network interface according to claim 2, wherein the IEEE 1394. According to the standard a, the event detection circuit includes a connection detection signal detected by a connection detection circuit included in the cable I / F, and a cable I / F.
Bias detected by the Bias detection circuit provided in F
A network interface that detects the occurrence of an event based on a change in at least one of the signals. 5. The network interface according to claim 4, wherein the event detection circuit includes a connection detection signal detected by a connection detection circuit included in the cable I / F and a Bias detection circuit included in the cable I / F. A network interface, which detects an event based on a change in at least one of the detected Bias signal and the LPS signal output from the LINK chip. 6. In addition to the active mode, at least one of a disconnect mode and a suspend mode is provided, and a process according to a scheduled protocol is performed when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A computer having a network interface for executing, which operates independently of a clock signal, and which is provided at least by the network interface from the setting of the disconnect mode or the suspend mode until the condition for canceling the mode is satisfied. A computer having a network interface, comprising a drive control circuit for stopping a part of the drive clock generation circuit. 7. In addition to the active mode, at least one of a disconnect mode and a suspend mode is provided, and a process according to a planned protocol is performed when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A printer having a network interface to execute, which operates independently of a clock signal, and which is provided at least in the network interface from the setting of the disconnect mode or the suspend mode until the condition for canceling the mode is satisfied. A printer having a network interface, comprising a drive control circuit for stopping a part of the drive clock generation circuit. 8. In addition to the active mode, at least one of a disconnect mode and a suspend mode is provided, and a process according to a planned protocol is performed when the setting condition and the releasing condition of the disconnect mode or the suspend mode are satisfied. A storage device having a network interface that executes, operates independently of a clock signal, and is provided by the network interface from the setting of the disconnect mode or suspend mode until the condition for releasing the mode is satisfied. A storage device having a network interface, comprising a drive control circuit for stopping at least a part of a drive clock generation circuit.