JP2002289838A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device suppressing diffusion of the impurities of a source/drain region, in the semicon ductor device having an LDD-type structure. SOLUTION: In this manufacturing method of the semiconductor device, boron and arsenic are ion-implanted simultaneously in a silicon substrate, and heat treatment is conducted thereafter. The enlargement of the boron can be suppressed, and the excessive diffusion of the source/drain region can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for suppressing diffusion of a source / drain region and reducing a short channel effect of a field effect transistor.

[0002]

2. Description of the Related Art Fine MOS for logic LSI
In the FET, L is applied to alleviate the electric field concentration at the drain end of the channel and suppress the generation of hot carriers.
A DD (Lightly doped drain) structure is used. FIG. 1 shows a part of a manufacturing process of a semiconductor device having a conventional LDD structure.
It is shown in FIG.

[0003] As shown in FIG.
An element isolation oxide film (not shown), an oxide film 101
To form Next, polysilicon is deposited on the entire surface by a CVD method, and a gate electrode 102 is formed by a photolithography technique and a dry etching technique (FIG. 16).
(B)). Next, ion implantation is performed on the entire surface of the semiconductor substrate 100 using the gate electrode 102 as a mask to form an LDD region 103 (impurity concentration of 10 ¹⁸ to 10 ²⁰ cm ⁻³ ) that becomes part of the source and the drain (FIG. 16C). )reference). Subsequently, an oxide film is formed on the semiconductor substrate 10 by CVD.
0 is deposited on the entire surface, and a sidewall 104 is formed by leaving the oxide film only on the side wall of the gate electrode 102 by a dry etching technique (see FIG. 16D). next,
By implanting impurity ions using the gate electrode 102 and the sidewalls 104 as a mask, the source / drain regions 105 (impurity concentration: 10 ¹⁸ to 10 ²⁰ cm ⁻³ )
Is formed (see FIG. 16E). Thereafter, heat treatment (activation annealing) is performed to activate the implanted ions and recover the crystallinity of the semiconductor substrate 100 (see FIG. 16F).

The above steps complete the LDD structure of the MOSFET. With this structure, since the LDD region 103 has a portion overlapping the gate electrode 102 with the oxide film 101 interposed therebetween, it is possible to prevent the MOSFET from being an offset transistor and to prevent the MOSFET from becoming an offset transistor. However, by forming the oxide film 101 so as not to overlap with the gate electrode 102 with the oxide film 101 interposed therebetween, generation of hot carriers is suppressed.

Furthermore, in the LDD structure, the junction between the source-side LDD region and the channel portion is connected to the drain-side LDD region.
Since the effective channel region is formed up to the junction between the DD region and the channel portion, the channel length is smaller than the width of the gate electrode.

In order to miniaturize the above-described MOSFET having the LDD structure, it is necessary to reduce the gate length, reduce the impurity region (shallow), reduce the thickness of the gate insulating film, and reduce the width of the sidewall. But the fine MOSFE
To suppress the short channel effect that occurs at T,
MOSFE while keeping the effective channel length as long as possible
The entire T must be reduced, creating a need for a shorter lateral width of the LDD region.

However, according to the above-described method, the LDD
In the case of forming a structure, there is a problem that diffusion of impurities occurs by performing activation annealing.

Therefore, in order to suppress the diffusion of impurities by reducing the thermal load in the activation annealing process, and to obtain the effects of crystallinity recovery and impurity activation, RTA (Rapid Thermal Anneal) or spike annealing is used. (For example, at a temperature of about 1000 ° C. for about 1 to 30 seconds).

However, due to point defects (interstitial silicon and vacancies) due to impurity ion implantation, TED (Tran
sient Enhanced Diffusion)
Even if a short-time heat treatment method such as a TA (Rapid Thermal Anneal) method or a spike annealing method is used, the problem of impurity diffusion has not been solved.

[0010] Furthermore, as the concentration of the implanted impurities becomes higher, the amount of point defects increases and the TED phenomenon becomes more remarkable. Therefore, the impurity diffusion is most remarkable in the activation annealing treatment after the source / drain implantation. Becomes

That is, when the width of the sidewall is very small and the protrusion width of the LDD region 106 with respect to the source / drain region 105 is short, the impurity in the LDD region 106 due to the impurity diffusion by the TED of the source / drain region 105 is reduced. Is diffused by TED, or
The LDD region 106 is covered by the diffusion of the impurity implanted into the source / drain region 105, which causes a problem that the LDD region is not secured.

The phenomenon that the LDD region cannot be secured as described above is more serious in the PMOSFET using boron than in the NMOSFET using arsenic for forming the LDD and source / drain regions. This is for the following reason.

That is, since arsenic has a small thermal diffusion in a silicon substrate, arsenic can be activated with almost no arsenic diffusion by using RTA or spike annealing, and the impurity distribution after the heat treatment can be changed immediately after ion implantation. It is possible to make the distribution substantially coincide with the impurity distribution. However, the diffusion of boron is several times to 10 times larger than that of arsenic. Therefore, even if RTA or spike annealing is used, the impurity distribution after the heat treatment greatly changes from the impurity distribution immediately after ion implantation.

In the case of ion implantation alone, a shallow implantation region can be obtained by implanting not only boron ions but also large molecules such as BF ₂ or decaborane. Since it diffuses as boron, the range of diffusion does not remain.

Therefore, conventionally, as a method for solving the above-mentioned problem, a PMOSF described in JP-A-3-209762 has been proposed.
A technique of making the width of the sidewall different between the ET and the NMOSFET may be used.
In order to suppress the lateral diffusion of the LDD region of the PMOSFET described in No. 2, a technique of obliquely implanting N-type impurity ions into the channel portion inside the LDD region has been used.

[0016]

However, even if the technique of forming two types of sidewalls having different widths is used, there is a problem that the number of process steps increases and the process becomes complicated.

Even if a technique of obliquely implanting N-type impurity ions is used, the impurity concentration in the channel portion increases, the drive current of the transistor decreases, and the threshold voltage of a transistor having a short gate length decreases. A rising inverse short channel effect occurs.

Accordingly, the present invention provides a method of manufacturing a semiconductor device which prevents the above-mentioned problem from occurring and prevents a low concentration region in a source / drain region from being secured due to impurity diffusion.

[0019]

In order to solve the above-mentioned problems, in order to solve the above-mentioned problems, a conductive type formed between a channel region and a source / drain region, having a conductivity type opposite to that of the channel region and having a higher concentration than the channel region. A semiconductor device including a transistor having a short channel effect suppressing region, a gate electrode formed above the channel region, and a sidewall formed in contact with the gate electrode above the short channel effect suppressing region In the manufacturing method, a step of depositing an insulating film on the substrate, a step of depositing a metal material on the entire surface and forming a gate electrode by patterning,
Using the gate electrode as a mask to form a part of the source / drain region by introducing an impurity of the opposite conductivity type to the channel region; depositing an oxide film on the entire surface of the substrate; Forming a sidewall by leaving an oxide film only on the substrate, and simultaneously using the gate electrode and the sidewall as a mask, simultaneously forming a first impurity of the opposite conductivity type and a second impurity of the same conductivity type with the channel region. Introducing process and heat treatment,
And a step of activating the impurities.

Further, in the method of manufacturing a semiconductor device, the first impurity is boron, boron difluoride or decaborane, and the second impurity is arsenic.

Further, in the method of manufacturing a semiconductor device, the concentration of the second impurity is 5 to 15% of the concentration of the first impurity.

According to the above-described manufacturing method, since boron and arsenic are simultaneously ion-implanted into the substrate, and then heat treatment is performed, the diffusion of boron is suppressed, and the interaction between arsenic and boron causes the source / drain region to become inactive. Can be suppressed from being thermally diffused.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

It should be noted that the drawings are to the extent that the present invention can be understood.
It merely shows the size, shape, and location of each component schematically. Also, in the following description, specific materials and numerical conditions of properties will be described. However, these materials and conditions are merely preferable examples, and are not limited thereto.

As shown in FIG. 15A, the semiconductor substrate 1
An element isolation oxide film (not shown) and an oxide film 2 are formed thereon. Next, polysilicon is deposited on the entire surface by a CVD method, and a gate electrode 3 is formed by a photolithography technique and a dry etching technique (see FIG. 15B). Next, using the gate electrode 3 as a mask, the semiconductor substrate 1
Ion implantation is performed on the entire surface to form an LDD region 4 (impurity concentration of 10 ¹⁸ to 10 ²⁰ c
m ⁻³ ) is formed (see FIG. 15C). Subsequently, an oxide film is deposited on the entire surface of the semiconductor substrate 1 by the CVD method, and the sidewall 5 is formed by leaving the oxide film only on the side wall of the gate electrode 3 by the dry etching technique.
(D)). Next, using the gate electrode 3 and the sidewalls 5 as a mask, boron and arsenic are simultaneously ion-implanted into the silicon substrate, and then heat treatment is performed. At the time of implantation, boron is implanted so that the peak of the boron concentration is higher than the uniform concentration of phosphorus, and that the arsenic concentration does not exceed the boron concentration. This is because the higher the arsenic concentration, the more the diffusion of boron is suppressed. However, the resistance of the source / drain region is suppressed, but the resistance of the source / drain region increases. . Here, the dose of arsenic is set to about one tenth of the dose of boron, and the dose of arsenic is set to 3 × 10 ¹⁴ cm ⁻² for the dose of boron of 3 × 10 ¹⁵ cm ⁻² . Thereafter, heat treatment is performed at 900 ° C. for about 10 minutes to activate the impurities (FIG. 15).
(F)).

By the way, S which contains a plurality of impurity atoms
When heat treatment is performed on an i-substrate, a phenomenon in which each impurity atom affects each other and behaves differently than when each impurity diffuses alone is known as interdiffusion. Even in a normal MOSFET,
For example, in the case of forming a source / drain of an N-type region by introducing an arsenic impurity having a concentration higher than that of boron into a part of a P-type well formed by using boron when forming an NMOSFET. Also, interdiffusion involving boron and arsenic, and other impurity atoms occurs. The cause of the mutual diffusion will be described below.

(1) The diffusion of impurity atoms proceeds by forming a pair of an impurity and a point defect (interstitial silicon and vacancy), but the point defect is caused not only by a specific impurity atom but also by boron or boron. Since diffusion acts on all impurity atoms such as arsenic and phosphorus stochastically, diffusion in which a plurality of impurities exist is different from diffusion in the case where a single impurity exists.

(2) In a portion of the silicon substrate where the concentration distribution of a certain impurity is sharply changed, a local electric field is generated by ionization of the impurity, and other impurities which are not electrically neutral are generated. Diffuse under the influence of the electric field. (Here, the phenomenon in which impurity atoms move under the influence of an electric field is a phenomenon called drift, which is different from diffusion (that is, a phenomenon in which the impurity atoms move from a high-concentration region to a low-concentration region). As an example of interdiffusion, an impurity profile (in the depth direction) when arsenic ions are implanted into a silicon substrate containing a uniform concentration of boron and heat treatment is performed is described as an example of the interdiffusion. FIG. 10 shows a result obtained by reproducing a change in impurity distribution) by simulation.
(After implantation) and FIG. 11 (after heat treatment). It can be seen that the boron distribution which was uniform immediately after the implantation of arsenic was changed by the heat treatment. If the heat treatment is simply performed without implanting arsenic ions, the uniformly distributed boron profile does not change (see FIG. 14. The boron concentration is slightly reduced on the surface due to the silicon concentration). And the segregation effect at the oxide film interface.)

As shown in this simulation example, as a result of the interdiffusion between boron and arsenic, the boron has such a distribution as to be swept to the region containing arsenic. In this example, the peak of the implanted arsenic concentration is higher than the boron concentration, so that the arsenic implanted region is an N-type region. That is, the change that occurs in the source / drain formation of the NMOSFET is reproduced.

Next, a simulation example in which low concentration arsenic is implanted into a silicon substrate containing uniform concentration of boron will be described. In this case, immediately after the implantation, the peak of the arsenic concentration is lower than the boron concentration (see FIG. 12), and no N-type region occurs after the heat treatment (see FIG. 13). However, the above-mentioned interdiffusion occurs, and the distribution also becomes such that boron is swept toward the region containing arsenic,
As a result, it can be seen that, in the region corresponding to the base of the arsenic distribution, the boron concentration is conversely reduced (FIG. 1).
3).

A description will be given below with reference to a simulation example.

In the above-described example, the case where boron is distributed in advance at a uniform concentration on the substrate and only arsenic is introduced therein by ion implantation has been described. In the next example, boron is simultaneously implanted with arsenic. The case of injection will be described.

Phosphorus is added to the N-type well of a normal MOSFET.
The diffusion concentration of the layer is 10¹⁷-10¹⁸cm ^-3Is the order of
About 10¹⁷cm^-3Silicon so as to have a uniform concentration of
Into the substrate. Boron and arsenic on this silicon substrate
At the same time, heat treatment is performed after ion implantation. When injecting,
Boron concentration peaks higher than uniform phosphorus concentration
The arsenic concentration does not exceed the boron concentration.
Inject as needed. This is because the higher the arsenic concentration, the more boron
Of the source / drain region is greatly suppressed.
Although the resistance is suppressed, the resistance of the source / drain region increases.
Therefore, it is desirable to set it to about 5 to 15%. here
Means that the injection amount of arsenic is about 1/10 of the injection amount of boron.
And boron dose 3 × 10¹⁵cm^-2Against arsenic
Dose 3 × 10¹⁴cm^-2And Then at 900 ° C
A heat treatment is performed for about 10 minutes to activate the impurities.

FIGS. 2 and 3 show the results of calculating the above steps by simulation. FIGS. 6 and 7 show simulation results in the case where heat treatment is performed by implanting only boron without implanting arsenic.

Therefore, when arsenic is implanted together with boron, the boron in the arsenic-implanted portion is agglomerated as if swept away by the mutual diffusion of boron and arsenic, and the boron in the portion is diffused. Not because
It can be seen that the diffusion of boron as a whole is greatly suppressed.

Further, a step of performing heat treatment after boron implantation and arsenic implantation is performed in a patterned state,
FIGS. 4 and 5 show an example implemented in the process of manufacturing a MOSFET.
In addition, a process of performing a heat treatment after boron implantation without performing arsenic implantation is performed in a patterned state, that is, a PMOSF.
FIGS. 8 and 9 show an example implemented in the ET manufacturing process. Here, according to the LDD structure creation flow shown in FIG.
In the source / drain implantation step, boron (here, B
Infusion) and arsenic is ion-implanted as F _2. FIG. 5 and FIG. 9 show the boron distribution after the heat treatment. It can be seen that when arsenic is implanted together with boron, the diffusion of boron is suppressed and the spread in the lateral direction is reduced.

The process conditions used here will be described. The sidewall width is 0.13 μm, and the LDD implantation condition is BF ₂
With a dose of 2.5 × 10 ¹³ cm ^-2 and an energy of 25 ke
V, source / drain implantation is performed with BF ₂ at a dose of 3 × 10 ¹⁵
cm-2, energy 50 keV, arsenic dose 2 × 10 ¹⁴ cm ⁻² , energy 50 keV, activation annealing conditions are temperature 900 ° C. and time 10 minutes.

In addition to the above heat treatment conditions, RTA
, The same effect can be obtained even when the normal annealing and the RTA process are combined.

FIG. 5 shows the boron concentration distribution at the outermost surface of the channel.
And FIG. Thus, when arsenic is not implanted, the LDD is diffused due to the diffusion of the source / drain regions.
Although the low-concentration region cannot be determined from the low-concentration region corresponding to the region, when arsenic is implanted, the diffusion of boron in the source / drain region is suppressed.
It can be seen that the region is formed and the effective channel length is also long.

By using the above method, fine PM
It can be seen that a PMOSFET having an LDD structure can be formed even when the sidewall width is reduced in the OSFET.

Further, P which simultaneously implants boron and arsenic
For the MOSFET and the PMOSFET not implanted with arsenic, a simulation was performed by changing the gate length.
FIG. 1 shows the relationship between the gate length and the threshold value. Simultaneous ion implantation of boron and arsenic to obtain the same V _th can shorten the gate length. That is, it is understood that the short channel effect is suppressed.

[0042]

According to the present invention, in the source / drain implantation step of the PMOSFET, it can be carried out by ion implantation of arsenic with an appropriate concentration and energy, and the number of masks can be increased as compared with the conventional process. In addition, since the number of ion implantation steps is increased only once, the process does not become complicated and the cost does not increase.

The arsenic ions introduced into the source / drain have a concentration of about 1/10 of the boron concentration.
Since there is little change in the impurity concentration in the D region and the channel region, there is no side effect such as a decrease in drive current.

Although the resistance of the source / drain regions is expected to increase, the resistance of the source / drain regions is greatly reduced by using the method of covering the source / drain surfaces with metal silicide, and the characteristics of the MOSFET are reduced. Has no effect.

[Brief description of the drawings]

FIG. 1 is a diagram showing a reduction effect of a short channel effect of a PMOSFET formed by carrying out the present invention.

FIG. 2 is a view showing an impurity concentration profile in a depth direction immediately after ion implantation in the present invention.

FIG. 3 is a diagram showing an impurity concentration profile in a depth direction after performing an activation annealing process in the present invention.

FIG. 4 is a diagram showing a boron concentration distribution in a cross section of a MOSFET according to the present invention.

FIG. 5 is a diagram showing an impurity concentration profile in a lateral direction along the channel surface of FIG. 4;

FIG. 6 is a diagram showing an impurity concentration profile in a depth direction immediately after ion implantation in a conventional method.

FIG. 7 is a diagram showing an impurity concentration profile in a depth direction after activation annealing in a conventional method.

FIG. 8 is a diagram showing a boron concentration distribution in a cross section of a MOSFET in a conventional method.

FIG. 9 is a diagram showing an impurity concentration profile in a lateral direction along the channel surface of FIG. 8;

FIG. 10 is a process simulation diagram showing a profile change due to the interdiffusion between arsenic and boron. FIG. 10 is an impurity concentration profile immediately after ion implantation when the ion implantation is performed so that the peak concentration of arsenic exceeds boron. It is.

FIG. 11 is a process simulation diagram showing a profile change due to interdiffusion between arsenic and boron. FIG. 11 shows impurities in the case where heat treatment is performed after ion implantation is performed so that the peak concentration of arsenic exceeds boron. It is a density profile.

FIG. 12 is a process simulation diagram showing a profile change due to interdiffusion between arsenic and boron. FIG. 12 is an impurity concentration profile when ion implantation is performed so that the peak concentration of arsenic does not exceed boron.

FIG. 13 is a process simulation diagram showing a change in profile due to interdiffusion between arsenic and boron. FIG. 13 shows a case where heat treatment is performed after ion implantation so that the peak concentration of arsenic does not exceed boron. It is an impurity concentration profile

FIG. 14 is an impurity concentration profile when heat treatment is performed without arsenic ion implantation.

FIG. 15 shows a MOSF having an LDD structure according to the present invention.
2 shows a part of a manufacturing process of ET.

FIG. 16 shows a conventional MOS having an LDD structure.
2 shows a part of a manufacturing process of the FET.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 oxide film 3 gate electrode 4 LDD region 5 sidewall 6 source / drain region

Claims (4)

[Claims] 1. A short channel effect suppressing region formed between a channel region and a source / drain region, having a conductivity type opposite to that of the channel region and higher in concentration than the channel region, and above the channel region. A method of manufacturing a semiconductor device including a transistor having a gate electrode formed in the above and a sidewall formed in contact with the gate electrode above the short channel effect suppressing region, wherein an insulating film is deposited on the substrate. Forming a gate electrode by depositing a metal material over the entire surface and patterning the same; and introducing an impurity of the opposite conductivity type to the channel region by using the gate electrode as a mask to form one of the source / drain regions. Forming an oxide film, depositing an oxide film on the entire surface of the substrate, and leaving an oxide film only on the side wall of the gate electrode by etch back Forming a sidewall by the above steps; simultaneously introducing a channel region and a first impurity of the opposite conductivity type and a second impurity of the same conductivity type using the gate electrode and the sidewall as a mask; And a step of activating the impurities. 2. The method according to claim 1, wherein the first impurity is boron, boron difluoride, or decaborane, and the second impurity is arsenic. 3. The method according to claim 1, wherein the concentration of the second impurity is 5 to 15% of the concentration of the first impurity. 4. A semiconductor device of an LDD type PMOSFET, wherein a source / drain region portion is made of boron and arsenic.