JP2002289693A - Method of design of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To give in a macro an unused area in which the layout of a separate functional block is possible as layout information that can be recognized by a design tool in a form which follows a conventional design system. SOLUTION: In the design step of placing and wiring a placing and wiring tool recognizes the inner unused area 3 of the macro 1 as a placing area of a new block except for the real block or the like belonging to the macro 1, by describing specifically an area in use in which the real block or the like of the inside of the macro 1 exists as a placing and wiring prohibited area 903 and by suggestively defining the unused region 3 in which no real block or the like of the inside of the macro 1 exists without describing especially the unused region 3 in which no real block or the like of the inside of the macro 1 exists as a placing and wiring possible area which is the opposition logic of placing and wiring prohibited area 903 in the definition part of placing and wiring area information that is the area in which the placing and wiring of the inside of a macro 1 is prohibited in the description of a library describing the macro 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit, and more particularly to a method of designing a semiconductor integrated circuit having a hard macro having an empty area for another function block.

[0002]

2. Description of the Related Art In recent years, for example, CBIC (Cell B
2. Description of the Related Art Large-scale semiconductor integrated circuits (LSIs) designed by using an integrated circuit (cell-based integrated circuit) have been widely used. This type of LSI is generally composed of a plurality of hard macros each including one or a plurality of functional blocks.

In general, a signal wiring passing through an upper (inner) portion of a macro has a waveform dull due to a signal passing through only a long distance without inserting a repeater, resulting in deterioration of delay, and a chip formed by a long wiring. (Wafer) There have been the following problems caused by the manufacturing process, particularly the fine processing. However, even if the signal delay time due to the wiring passing through the upper part of the macro is within the allowable range with respect to the target frequency of the chip, or even if the delay time of the wiring is out of the allowable range, the vicinity of the corresponding macro Is bypassed while inserting a repeater, thereby satisfying the target frequency. In addition, even if it is referred to as fine processing, the processing size is such that the gate insulating film is not broken due to the antenna effect.

[0004] However, in recent years, SOC (system-on-
With the promotion of “chips”, there is a tendency that “functional blocks” conventionally prepared as separate chips are incorporated on the same chip. As a result, a larger hard macro is required, a higher target frequency is required by being integrated on the same chip, and processing dimensions are such that gate insulating film breakdown due to an antenna effect becomes a problem. . Therefore, even if the signal wiring is simply allowed to freely pass over the large-scale macro, it is actually possible to detour while inserting a repeater,
In some cases, it is necessary to reconsider the shape of the hard macro itself, and in reality, the wiring area above the macro prepared for the passing wiring cannot be used effectively.

Therefore, it is required that a block of another function unrelated to the hard macro, that is, a repeater (relay buffer) can be inserted (arranged) even in a large-scale hard macro.

In order to meet such a demand, for example, a conventional method for designing a semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 05-160266 uses a spare element embedded in advance and uses the spare element as necessary. Propose that.

However, the original purpose of this prior art is to realize a semiconductor device which can easily and quickly cope with a change caused in a product development process. The main objective is to correct the products that have entered the stage at the lowest possible cost. Therefore, it does not correspond to correction at the chip design stage before the manufacturing process.

Referring to FIG. 7, which shows an example of an LSI to which a conventional method of designing a semiconductor integrated circuit is applied in the form of a board layout, the LSI shown in FIG. 7 is a macro formed on a substrate 101 and each consisting of a circuit group. 8 modules M1
01 to M108 and predetermined spare gates RG1 arranged in three empty areas generated between the arranged modules.
And spare units RU1 and RU2, and a number of bonding pads PAD formed along four sides of the substrate 101.

Next, the operation of the conventional method for designing a semiconductor integrated circuit will be described with reference to FIG.
Are designed by the so-called CBIC method. Each of the modules M101 to M108 is constituted by a standard module prepared in a module library in advance or a user module formed by combining macro cells prepared in a cell library in advance, and is logically connected via an internal bus (not shown). Join.

The modules M101 to M108 are designed to realize the functions to be performed with the minimum number of elements, the layout area, and the wiring length, and the layout and the connection wiring of these modules use computer-aided design (CAD). This is performed by the automatic wiring placement design system. As a result, the design period of the LSI is shortened, the number of elements as a whole LSI, the required area of the substrate is reduced, and the signal transmission delay time is reduced.

As described above, the modules M101 to M10
8 is designed to realize its function with the minimum number of elements, layout area and wiring length, and is fixedly formed with a determined optimum circuit configuration and optimum arrangement. At this time, the layout shapes of the modules M101 to M108 are inevitably rectangular, and even if an optimal design is performed, some empty areas are generated between the modules in this example. Therefore, a spare gate RG1 and spare units RU1 and RU2 are arranged in these three empty areas.

If any change occurs in the course of product development, when the fabrication of the semiconductor substrate is completed, the corresponding connection wiring is changed to FIB (Focused Ion Beam) or laser CVD (Chemical Vapor Deposition).
selectively enabled by selectively cutting or adding using a position.

As described above, in the conventional method of designing a semiconductor integrated circuit, a spare element such as a spare gate or a spare unit is previously arranged in an empty area between modules. The tool needs to be recognized as a "hard macro with spare elements".

As a result, the macro having the spare element needs to be modeled in advance with the spare element.
The operation must be finely defined when the spare element is used or not, and the library becomes complicated, and the macro development TAT is unexpectedly prolonged.

In addition, it is necessary to always treat each terminal correctly (connection to a power supply or GND) for a spare element that is finally unused. If the treatment is forgotten, a DC current will flow, or in the worst case latch-up will occur. There is a risk of causing it.

If the original delay information or current consumption information of the macro changes between the case where the spare element is used and the case where the spare element is not used, the timing of the entire chip is determined by using / non-use of the corresponding portion as a repeater. Has a disadvantage that the chip design itself does not easily converge.

Further, when a corresponding macro with a spare element is used in a lower layer of a hierarchical design, there is a possibility that the spare element cannot be recognized from an upper layer.

Furthermore, since it is necessary to manually determine whether the spare element was not used finally or whether the terminal connection (processing) could not be correctly performed due to a tool problem, it is necessary to make a mistake such as forgetting to confirm. Is expected to be mixed in, or an enormous verification time is required.

Furthermore, since it is necessary to add a design flow for correctly recognizing a macro with a spare element to various design tools, there is a problem that a significant change is required from the existing design system.

[0020]

In the above-described conventional method for designing a semiconductor integrated circuit, a spare element is previously arranged in an empty area between modules. Since it is necessary to recognize in the form of `` hard macro with '', macros with spare elements need to be modeled in advance with spare elements, and when spare elements are used and not However, there is a disadvantage that the library becomes complicated and the macro development TAT is unexpectedly prolonged.

In addition, it is necessary to always treat each terminal correctly (connecting to a power supply or GND) for a spare element that is finally unused. If the treatment is forgotten, a DC current will flow, or in the worst case latch-up will occur. There was a drawback that there was a risk of starting.

If the original delay information or current consumption information of the macro changes between the case where the spare element is used and the case where the spare element is not used, the timing of the entire chip is determined by using / non-use of the corresponding portion as a repeater. However, there is a drawback that the chip design itself does not easily converge because of the change in.

Further, when a corresponding macro with a spare element is used in a lower layer of a hierarchical design, there is a disadvantage that the spare element may not be recognized from an upper layer.

Furthermore, since it is necessary to manually determine whether the spare element was not used finally or whether the terminal connection processing could not be correctly performed due to a tool problem, it is necessary to make a mistake such as forgetting to confirm. There is a drawback that contamination and the necessity of an enormous verification time may occur.

Further, since it is necessary to add a design flow for correctly recognizing a macro with a spare element to various design tools, there is a disadvantage that a drastic change from the existing design system is required.

An object of the present invention is to provide an unused area in which a block of another function can be arranged inside a hard macro in a form that can follow the conventional design system as it is, that is, an area where elements and wiring do not exist in advance. Another object of the present invention is to provide a method of designing a semiconductor integrated circuit having layout information in a form recognizable by a design tool.

[0027]

According to a first aspect of the present invention, there is provided a method of designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), wherein the macro is described. In the description of the library that is the layout data for placement and routing, the definition part of the information of the placement and routing prohibition area, which is the area where placement and routing inside the macro is prohibited, is defined as the used area where the actual element or block and the wiring inside the macro exist. Explicitly describe as a placement and routing prohibited area, and particularly describe an unused area inside the macro where there is no actual element or block and wiring as a placement and routing enabled area that is the opposite logic of the placement and routing prohibited area. The unused area inside the macro is defined implicitly by the place and route tool at the place and route design stage. It is characterized in that to recognize the arrangement region of the new block or new elements other than the actual elements or blocks belonging to black.

According to a second aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, the internal unused area of the macro defined implicitly is completed by the placement and routing tool. It is characterized in that it is treated equivalently to an existing unused area outside the macro existing outside the macro.

According to a third aspect of the present invention, in the method of designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), the layout data for layout and wiring describing the macro is used. In the description of a library, the definition part of the information of the placement and routing prohibited area, which is the area where the placement and routing inside the macro is prohibited, is explicitly prohibited for the use area where the actual element or block and the wiring inside the macro exist. It is described as an area, and the unused area inside the macro where the actual elements or blocks and wiring are not present is defined implicitly without any particular description as a placeable / routable area that is the opposite logic of the placement / disabled area. At the design stage of the placement and routing, the unused area inside the macro belongs to the macro by the placement and routing tool. It is recognized as an arrangement area of a new block or a new element other than an actual element or block, and the number of the internal unused area of the macro is the size of the internal unused area, its arrangement position, and a plurality of inside the macro. In this case, there is a certain regularity regarding the arrangement interval (pitch).

According to a fourth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the third aspect, the size of the internal unused area is at least one new repeater block serving as a signal relay buffer. It can be arranged as

According to a fifth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the third aspect, when the macro can be rotated or arranged in a mirror, the macro can be arranged in a rotation or a mirror. The vertical and horizontal sizes of the internal unused area of the macro can sufficiently arrange at least one repeater block as a signal relay buffer.

According to a sixth aspect of the present invention, in the method of designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), the layout data for layout and wiring describing the macro is used. In the description of a library, the definition part of the information of the placement and routing prohibited area, which is the area where the placement and routing inside the macro is prohibited, is explicitly prohibited for the use area where the actual element or block and the wiring inside the macro exist. It is described as an area, and the unused area inside the macro where the actual elements or blocks and wiring are not present is defined implicitly without any particular description as a placeable / routable area that is the opposite logic of the placement / disabled area. At the design stage of the placement and routing, the unused area inside the macro belongs to the macro by the placement and routing tool. Wiring related to signal integrity that takes into account signal degradation due to signal delay and / or attenuation and / or the effects of electromigration / thermoelectrons, as a new block or new device placement area other than the actual element or block Is defined as the limit distance,
The internal unused area that is first arranged from the outer periphery of the macro toward the inside is arranged within the limit distance in both the vertical and horizontal directions from the outer periphery of the macro, and the macro All the internal unused areas inside are arranged within the limit distance from each other in both the vertical direction and the horizontal direction.

According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit designing method according to the first or third or sixth aspect.
A power supply is provided from the power supply line of the macro to the new block or the new element arranged in the internal unused area.

According to an eighth aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the sixth aspect, when the size of any of the macros in the vertical direction and the horizontal direction is within the limit distance, the plurality of macros are set. Are defined as an upper macro, which is a functional block of an upper hierarchy, and the internal unused area inside the macro is mutually reciprocal in both the vertical and horizontal directions of the upper macro. It is characterized in that it is configured to be arranged within the limit distance.

[0035]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

The method for designing a semiconductor integrated circuit according to the present embodiment is a method for designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), which is a library which is layout data for layout and wiring describing the macro. In the description of the above, the definition part of the information of the placement and routing prohibited area, which is the area where placement and routing inside the macro is prohibited, is explicitly defined as the use area where the actual element or block and the wiring inside the macro exist. The unused area in which the actual element or block and the wiring inside the macro are not present is defined and implicitly defined as a placeable / routable area that is the opposite logic of the placement / disabled prohibited area. At the design stage, the unused area inside the macro is assigned to the actual It is characterized in that to recognize as the arrangement area of the block or element other than a child or block.

Next, referring to FIG. 1A, which is a layout diagram showing an example of a hard macro (hereinafter, macro) to which the design method of the embodiment of the present invention is applied, the semiconductor of the embodiment shown in FIG. A macro to which the integrated circuit design method is applied is a rectangle surrounded by points abcd (hereinafter, rectangle abcd).
d, etc.), an unused area 2 outside of the macro 1 where nothing is arranged,
And an unused area 3 which is surrounded by a rectangle efgh and for which no placement prohibition is defined. There is no element or wiring in this, and it is in the same state as the unused area 2 outside the macro 1.

The macro 1 is a use area defined by rectangles aihl, ibje, fjck, and lgkd, each of which divides the macro 1 and is a layout prohibited area 11, 12, 13, or 14 for prohibiting the placement of a new block. Having.

Referring to FIG. 1B, which shows a method of defining the macro 1 in the library by a program description, a description 900 showing the entire definition of the macro 1 is a description 901 defining the pin information of the macro 1 and a description 901 defining the macro 1 And a description 902 defining the prohibition information.

The description 902 is a description 903 which is a part of the prohibition information that particularly defines the prohibition on placement.
Having.

When the placement prohibition information (area) is explicitly defined in this manner, the placement and routing tool can implicitly place an unused area for which "placement prohibition" is not defined as the opposite logic of the placement prohibition area. It will be recognized as region 3.
In this way, the allocable area can be defined.

Normally, another block is not overlapped and arranged inside the hard macro (since each element and wiring are short-circuited). Therefore, an arrangement prohibited area is explicitly defined. If not, the placement and routing tool recognizes that "the entire macro is prohibited from being placed."

The method of defining layout information to be placed in the placement prohibited area in FIG. 1A and other layout information in FIG. 1B is well known to those skilled in the art, and is directly related to the present invention. Therefore, the description of the detailed configuration is omitted.

Next, the operation of the present embodiment will be described with reference to FIGS. 1A and 1B and FIG. 2 which shows a layout diagram of the macro 1 recognized by the placement and routing tool in a layout diagram. The placement and routing tool reads a layout shape in which placement prohibition information is explicitly defined as shown in FIG. 1 (B), so that the area other than the placement prohibition area, that is, the area in which the placement prohibition is not defined, becomes “ This is an unused area where nothing is arranged. "

In general, as shown in FIG. 1C, the placement and routing tool intentionally forcibly arranges the unused areas into macros 11A, 12A, 13A, and 14A, which are different functional blocks. In this case, it is designed to be recognized as an unused area which is completely the same as the unused area 3A which is a free area remaining as a placeable area. Also in the present embodiment, it is assumed that the placement and routing tool has the assumed recognition function.

The unused area 2A is composed of the macros 11A and 12A.
A unused area outside of A, 13A, and 14A in which nothing is arranged, and an unused area 3A is an unused area surrounded by macros 11A to 14A.

Next, in the design stage of the detailed wiring, if it is necessary to pass the signal wiring over the macro 1,
If the placement and routing tool determines that a repeater (buffer for signal relay) needs to be inserted in the middle of the wiring, the unused area 3 inside the macro 1 is set in the same manner as the unused area 2 outside the macro 1. Insert a repeater and design a chip.

This is because there is no element in the unused area 3 from the beginning, and the placement and routing tool interprets the element as completely the same as the normal unused area 2.

As described above, by actively using the placement prohibition definition, the placeable area can be defined implicitly, and is recognized as the placeable area by the placement and routing tool without using any special method. .

For the placement and routing tool, the empty area inside the macro 1, that is, the unused area 3 is treated as completely equivalent to the normal unused area 2 outside the macro 1, so that the unused area inside the macro 1 is not used. If necessary, a spare element such as a repeater, which is another functional block, can be arranged in the use area 2 as needed.

In this case, since the macro and the spare element are independent of each other, there is no need to change the design flow and the design tool at all as before.

Further, since the spare element does not exist in advance, the processing when the spare element is unused and the verification thereof are not required.

Further, it is not necessary to give feedback to the chip design depending on which part of the spare element is used.

Next, referring to FIGS. 2 (A) and 2 (B), which are layout diagrams showing macros characterizing the second embodiment of the present invention, the macro 1B of the present embodiment shown in FIG. Is different from the macro 1 of the first embodiment in that the unused areas 300 to 309, 310 to 319, which are a plurality of disposable areas created implicitly inside the macro 1B.
, 391 to 399.

The size of the repeater 4 to be placed in the unused area shown in FIG. 2B is defined as the lengths c and d in the horizontal and vertical directions for convenience of explanation.

The signal integrity (Signal Int)
The limit length of the wiring related to (eg. The distance B is a distance that satisfies 0 ≦ B <A, and indicates the arrangement interval (pitch) of the repeaters 4 here. Here, the limit length of the wiring related to signal integrity refers to signal deterioration due to signal delay and / or attenuation when a longer wiring length is used, and EM (Electromigration) / HotE.
It means the distance which becomes a problem due to the influence of (thermal electrons).

Unused areas 300 to 309, 310 to 319,..., 3 inside the macro 1B shown in FIG.
Each of the dimensions 91 to 399 is such that at least one repeater 4 can be arranged. Unused areas that first appear in the vertical and horizontal directions from the outer periphery of the macro 1B to the inside of the macro must always appear within a range that satisfies the distance B, and all unused areas are adjacent to each other. The fitting interval is prepared so as to satisfy the distance B. Furthermore, the layout configuration is such that the base point of the distance that satisfies the distance B is calculated by assuming the position of the input / output terminal of the repeater 4 that will be arranged in the unused area.

At this time, when the signal wiring passes over the macro 1, it is possible to pass the signal wiring while inserting (arranging) the repeater 4 in any of the unused areas 300 to 399.

Here, in the process generation where the distance A is L = 0.15 μm, it is necessary to insert a repeater about every 3 mm from the viewpoint of delay, and EM (electromigration) / HotE (hot Due to the restrictions on the electron, it depends on the operating frequency but is not limited to 0.
It is predicted that only about 5 pF (2-3 mm in terms of wiring capacitance) is likely to be acceptable. For this reason, conventionally,
If there is a 4-5mm square hard macro,
There was a problem that it was necessary to bypass the outer periphery of the macro because it would not be possible to pass on this macro.However, since there is a relay point where repeaters can be arranged inside a large-scale hard macro, The signal can pass.

In the present embodiment, regularity is given to the size and interval (pitch) of the unused area, that is, the arrangable area, so that the repeater always relays the signal even in either the vertical or horizontal direction. Therefore, there is an effect that the speed is not deteriorated and the wiring is not concentrated due to the detour.

Next, macros characterizing the third embodiment of the present invention are shown in layout diagrams in FIGS.
Referring to (C), the difference between the macro 1C of the present embodiment shown in this figure and the macro 1 of the first embodiment described above is that the macro 1C can be rotated and arranged in a mirror. .

FIG. 3A shows the macro 1C in FIG.
Indicates a macro 1CA in which the macro 1C is rotated by 90 degrees.

The macro 1C has unused areas 31 and 32, and the macro 1CA has unused areas 31A and 32A when the unused areas 31 and 32 are arranged by rotating by 90 degrees.

FIG. 3C shows unused areas 31, 32, 3
The repeaters 4 scheduled to be arranged at 1A and 32A are shown.
The horizontal and vertical dimensions of the repeater 4 are c and d, and
It is assumed that d> c.

FIG. 3A shows the distance A, which is the limit length of the wiring related to the signal integrity described above, and the distance B, which is the repeater arrangement interval (pitch) satisfying 0 ≦ B <A.

At this time, the vertical and horizontal sizes of the unused areas 31, 32, 31A and 32A, which are the areas where the repeater 4 can be arranged, are always the same regardless of how the macro 1C is rotated and arranged in the mirror. Is characterized in that each side is configured to have a size equal to or larger than d so that can be correctly arranged.

As a result, it is possible for the signal wiring to pass over the macro 1C without any problem regardless of how they are arranged, with relaying by the repeater 4.

Next, referring to FIG. 4A which shows a macro which characterizes the fourth embodiment of the present invention in a layout diagram, FIG. 4 (A) shows a macro 1D of the present embodiment shown in FIG. The difference from the macro 1 of the embodiment is that the macro 1
Two power supply lines 5 for supplying power to the unused area 3D to specifically show a power supply method for the repeater 4D, which is a block disposed in the unused area 3D inside D.
D, 6D.

Here, for convenience of explanation, it is assumed that the macro 1D is composed of a basic cell such as an IP core having a constant length in the vertical direction (hereinafter referred to as pitch in the Y direction).
Therefore, the pitch of the unused area 3D in the Y direction is the same as that of the internal cell of the macro 1D. The repeater 4D has the same size in the Y direction as the internal cell of the macro 4D. The intervals (Y-direction pitch) between the power supply lines 5D and 6D in the Y-direction are also the same as the Y-direction pitch of the internal cells of the macro 1D.

In this case, the arrangement positions of the power supply lines 5D and 6D are the same as the arrangement positions of the power supply lines inside the macro 1D, which is the IP core, so that they are located at these power supply lines 5D and 6D. , A power supply terminal for the unused area 3D is provided. As described above, since the Y-direction pitch of the internal cell of the macro 1D is the same as the Y-direction pitch of the unused area 3D and the Y-direction pitch of the repeater 4D disposed therein, there is no problem. Power is supplied to the arranged repeater 4D in the same manner as in the case of arranging cells at the same time.

As described above, the power supply to the unused area inside the macro and the power supply to the repeater arranged therein can be connected without a special power generation flow.

Next, referring to FIG. 4B, which is a layout diagram showing macros characterizing the fifth embodiment of the present invention, the above-described fourth macro of the macro 1E of the present embodiment shown in FIG. The difference from the macro 1D of the embodiment is that the macro 1E
Is a macro such as a RAM macro in which a power supply line does not exist at a pitch in the Y direction (or a pitch in the horizontal (X) direction: hereinafter simply referred to as pitch) of a basic cell, and has an unused area 3E inside such a macro 1E. That is, the repeater 4E is arranged therein.

In this case, the unused area 3
Power supply rings L5E and L6E are provided inside E, and these power supply rings L5E and L6E are connected to the power supply line of the macro 1E at power supply lead terminals T5E and T6E, respectively.
Inside the power supply rings L5E and L6E, power supply lines 5E and 6E connected to the power supply rings L5E and L6E, respectively.
Is provided.

When the pitch of the power supply line does not match the pitch of the power supply terminal of the repeater 4E as shown in FIG.
The power supply rings L5E and L6E are once disposed in the unused area 3E, and the power supply lines 5E and 6E are again arranged from the power supply rings L5E and L6E toward the inside of the ring so as to match the pitch of the power supply terminals of the repeater 4E. Is arranged.
By doing so, power can be supplied without depending on the power supply line pitch inside the macro 1E.

Next, referring to FIG. 5, which is a layout diagram showing macros characterizing the sixth embodiment of the present invention, the above-described fourth embodiment of the macro 1F of the present embodiment shown in FIG. Is different from the macro 1D in that the repeater 4F disposed in the unused area 3F itself passes through the power supply lines 5F and 6F directly passing above the macro 1F to the power supply pads P5F and P6F provided inside the unused area 3F and the unused area 3F. That is, power is supplied via the power supply lines 5G and 6G in the area 3F.

When the size of the unused area 3F is large enough to independently have power supply pads P5F and P6F for connecting to the power supply lines 5F and 6F above the macro 1F,
This is used when it is desired to separate the power supply inside the macro 1F from the power supply in the unused area 3F.

In the unused area 3F, the power supply pad P5
In the case where power supply pads such as F and P6F can be independently arranged, they can be easily connected to an upper power supply line without using power supply means from the inside of the macro 1F.

In this way, separate power can be supplied to the repeater inside the macro, and the macro and the repeater are separated from each other, so that it is possible to construct a macro that is not mutually affected by power noise.

Next, referring to FIG. 6 showing a layout diagram of the seventh embodiment of the present invention, a macro 100 which is a high-order large-scale hard macro which characterizes this embodiment shown in FIG. Macros 111 to hard macros
121.

The macros 111 to 121 have unused areas 700 to 720 inside. Unused areas 700 to 703 arranged in the X direction at the bottom in the Y direction, and unused areas 710 to 713 arranged in the X direction second from the bottom in the Y direction.
And unused areas 72 arranged in the X direction at the top of the Y direction
0 to 723. For convenience of explanation, the arrangement intervals (pitch) in each of the X and Y directions are the same.

Therefore, in the example shown in FIG.
0 to 703, 710 to 713, 720 to 720 are arranged in each macro as follows.

The macro 111 has an unused area 720 inside.
, And the macro 112 has an unused area 71 inside.
0, the macro 113 has an unused area 700 inside, the macro 114 has unused areas 711 and 701 inside, the macro 115 has an unused area 702, and the macro 116 has an unused area inside. It has a use area 703 and a macro 117
Has an unused area 712 inside, and macros 118 to 12
1 are arranged adjacent to each other without a gap, and macros 118 and 121
Macro 119 and macro 1 have no unused area inside
20 has an unused area 713 inside the boundary.

Each of the macros 111 to 121 has a size that does not cause a problem with respect to the limit length of wiring related to signal integrity. However, by combining them by a hierarchical design, a higher-order hard macro is constructed, and May cause the problem of the limited length.

Here, for convenience of explanation, X of macro 100
The size in the direction and the Y direction is assumed to be sufficiently larger than the distance A which is the limit length of the wiring (A), and the size of the macro in the lower layer, typically the macro 113, in the X and Y directions is the distance A.
Smaller (<A).

In this case, when viewed from the macro 100, the unused area 700 is set so that the size and arrangement pitch of the unused area satisfy the conditions described in the second and third embodiments.
703, 710-713, 720-720 may be selected.

In this way, signal wiring can pass through a large-scale module generated by hierarchical design without any problem.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made. For example, the block arranged in the unused area inside is not limited to the repeater, but may be another logical block without departing from the gist of the present invention.

[0088]

As described above, the method of designing a semiconductor integrated circuit according to the present invention provides a method of designating a library in which a macro is described. In the definition part, the used area where the actual block etc. inside the macro exists is explicitly described as the placement and routing prohibited area, and the unused area where the actual block etc. inside the macro does not exist is opposite to the placement and routing prohibited area. A special method is defined by implicitly defining it as a placeable and routable area that is a logic, and making the place and route tool recognize the unused area as a placement area for a new block etc. at the stage of placement and routing. The placement and routing tool recognizes unused areas inside the macro as unused areas even if they are not used. Treat as the Ku equivalent, there is an effect that can be placed spare cell is another functional block later as needed in an unused area of the internal macro.

Further, since the macro and the spare element are independent of each other, there is an effect that the design flow and the design tool do not need to be changed at all as before.

Further, since the spare element does not exist in advance, there is an effect that the processing when the spare element is unused and the verification thereof are not required.

Further, it is not necessary to provide feedback to the chip design depending on which part of the spare element is used, so that an increase in the design period is eliminated, and the design can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing an example of a macro to which a first embodiment of a method of designing a semiconductor integrated circuit according to the present invention is applied;

FIG. 2 is a layout diagram showing an example of a macro characterizing a second embodiment of the method of designing a semiconductor integrated circuit according to the present invention;

FIG. 3 is a layout diagram illustrating an example of a macro characterizing a third embodiment of the method of designing a semiconductor integrated circuit according to the present invention;

FIG. 4 is a layout diagram showing each example of a macro characterizing the third and fifth embodiments of the method for designing a semiconductor integrated circuit according to the present invention;

FIG. 5 is a layout diagram showing an example of a macro characterizing a sixth embodiment of the semiconductor integrated circuit design method of the present invention.

FIG. 6 is a layout diagram showing an example of a macro characterizing a seventh embodiment of the method of designing a semiconductor integrated circuit according to the present invention.

FIG. 7 illustrates an example of an L level to which a conventional semiconductor integrated circuit design method is applied.
FIG. 3 is a layout diagram illustrating an example of an SI.

[Description of Signs] 1, 1B, 1C, 1CA, 1D, 1E, 1F, 11A,
12A, 13A, 14A, 100, 111 to 121
Macro 2,3,2A, 3A, 3E, 3F, 31,32,31
A, 32A, 300-309, 310-319, ...
・, 391-399,700-703,710-71
3,720-723 Unused area 4,4D, 4E, 4F Repeater 5D, 6D, 5E, 6E, 5F, 6F, 5G, 6G
Power supply line 11-14 Placement prohibited area 900-903 Description L5E, L6E Power supply ring P5F, P6F Power supply pad T5E, T6E Power supply lead terminal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA05 5F038 CA03 CA05 CA17 EZ09 EZ20 5F064 AA06 DD02 DD05 DD26 HH06 HH12

Claims (8)

[Claims] 1. A method for designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), wherein placement and routing inside a macro is prohibited in description of a library which is layout data for placement and routing describing the macro. The defined portion of the information of the placement and routing prohibited area, which is the area, is explicitly described as a placement and routing prohibited area, where the actual element or block inside the macro and the use area where the wiring is present, and the actual element inside the macro Alternatively, an internal unused area where blocks and wiring do not exist is defined implicitly without any particular description as a placeable / routable area that is the opposite logic of the placement / routing prohibited area, and the macro is added to the placement and routing tool in the placement and routing design stage. The unused area inside the macro is replaced with a new block or block other than the actual element or block belonging to the macro. Is a method for designing a semiconductor integrated circuit, characterized in that it is recognized as an arrangement area of a new element. 2. The unused area inside the macro of the implicitly defined macro is treated equivalently to an existing unused area outside the macro existing outside the macro after placement by the placement and routing tool. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein: 3. A method for designing a semiconductor integrated circuit having at least one hard macro (hereinafter, macro), wherein placement and routing inside a macro is prohibited in description of a library which is layout data for placement and routing describing the macro. The defined portion of the information of the placement and routing prohibited area, which is the area, is explicitly described as a placement and routing prohibited area, where the actual element or block inside the macro and the use area where the wiring is present, and the actual element inside the macro Alternatively, an internal unused area where blocks and wiring do not exist is defined implicitly without any particular description as a placeable / routable area that is the opposite logic of the placement / routing prohibited area, and the macro is added to the placement and routing tool in the placement and routing design stage. The unused area inside the macro is replaced with a new block or block other than the actual element or block belonging to the macro. Is recognized as an arrangement area of a new element, and the internal unused area of the macro is fixed with respect to the size of the internal unused area, its arrangement position, and the arrangement interval (pitch) when a plurality of the internal unused areas exist inside the macro. A method for designing a semiconductor integrated circuit, characterized by having regularity. 4. The method for designing a semiconductor integrated circuit according to claim 3, wherein the size of the internal unused area is such that at least one repeater block serving as a signal relay buffer can be arranged as a new block. . 5. When the macro is rotatable or mirror-arrangeable, the vertical and horizontal sizes of the internal unused area of the macro are at least one even if the macro is rotatable or mirror-arranged. 4. The method for designing a semiconductor integrated circuit according to claim 3, wherein a repeater block as a buffer for use can be sufficiently arranged. 6. A method for designing a semiconductor integrated circuit having at least one hard macro (hereinafter referred to as a macro), wherein a layout inside a macro is prohibited in a description of a library which is layout data for layout describing the macro. The definition part of the information of the placement and routing prohibited area, which is an area, is explicitly described as a placement and routing prohibited area of a use area where an actual element or block and wiring inside the macro is located, and the actual element inside the macro is Alternatively, an internal unused area where blocks and wiring do not exist is defined implicitly without any particular description as a placeable / routable area that is the opposite logic of the placement / routing prohibited area, and the macro is added to the placement and routing tool in the placement and routing design stage. The unused area inside the new block or new block other than the actual element or block belonging to the macro Is defined as a placement area of a new element, and a limit distance of a wiring limit related to signal integrity in consideration of signal degradation and / or electromigration / thermoelectron effects due to signal delay and / or attenuation is defined as a limit distance. The inner unused area that is first arranged from the outer peripheral portion toward the inside is disposed within the limit distance in both the vertical and horizontal directions from the outer peripheral portion of the macro, A method of designing a semiconductor integrated circuit, characterized in that all the internal unused areas are arranged within the limit distance from each other in both the vertical direction and the horizontal direction. 7. The semiconductor according to claim 1, wherein power is supplied from said power supply line of said macro to said new block or new element arranged in said internal unused area. How to design integrated circuits. 8. When the size of any of the macros in the vertical direction and the horizontal direction is within the limit distance, a plurality of the macros are arranged in combination to define an upper macro as a functional block of an upper hierarchy, 7. The semiconductor according to claim 6, wherein the unused area inside the macro is arranged within the limit distance from each other in both the vertical and horizontal directions of the upper macro. How to design integrated circuits.