JP2002288990A - Peak hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably perform accurate peak hold without being affected by dielectric absorption of a capacitor and a device. SOLUTION: This circuit has a differential circuit 21 for obtaining an absolute value of difference between an output signal and an input signal of an operational amplifier 16, a comparator 22 comparing a signal from the differential circuit with a reference value, a hold timing section 23 outputting repeatedly a hold command until difference gets in the prescribed range (threshold value) when difference is found in the compared result, and a reset signal section 24 stopping the hold command at a point of time at which difference gets in the prescribed range.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit for holding a peak of a voltage waveform, and more particularly to a peak hold circuit suitable for an input signal having a relatively slow change.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional example of a peak hold circuit. In FIG. 3, reference numeral 1 denotes an input terminal, 2 denotes a buffer operational amplifier for lowering the output impedance of a signal source, 3 denotes a diode for half-wave rectification, 4 denotes a capacitor for holding a half-wave rectified voltage, An operational amplifier 5 senses the voltage held by the capacitor 4 with a high input resistance, and 6 is an output terminal.

In the peak hold circuit having the above configuration, when a positive input signal is input from the input terminal 1 to the positive side of the operational amplifier 2, the operational amplifier 2 becomes a positive output,
Half-wave rectification is performed by the diode 3 and held by the capacitor 4. Here, if the voltage held by the capacitor 4 is lower than the output voltage of the operational amplifier 2,
Through the capacitor 4. Since the voltage charged in the capacitor 4 is fed back to the negative side of the operational amplifier 2 through the operational amplifier 5, the voltage input to the positive side of the operational amplifier 2 is held and output as an output signal from the output terminal 6.

In this case, if the voltage signal input to the positive side of the operational amplifier 2 is lower than the voltage held up to that point, or if there is a negative side voltage signal, charging through the diode 3 is performed. Since there is no output, the output of the operational amplifier 5 retains the previous state.

[0005]

The peak hold circuit shown in FIG. 3 has the following problems. In other words, the capacitor 4 used in the peak hold circuit is made of a dielectric, but a phenomenon occurs in which the value held at the time of resetting becomes unstable due to the influence of the degree of absorption of the dielectric. This is a phenomenon that occurs because the electric charge in the capacitor 4 cannot be completely discharged. Therefore, it is necessary to use a substance having a small dielectric absorption or to take data several times and take an average value thereof. That is the fact.

However, in the case of the former capacitor,
There is no limit even for those with small dielectric absorption, and there is no one with a smaller absorption degree below that.In the case of the latter capacitor, it is selected in advance by the actual device to take the average value of repeated data Therefore, there is a problem that an accurate value is not always held.

The present invention has been made in view of the above circumstances, and can accurately hold a peak value without being affected by the influence of dielectric absorption of a capacitor and without being affected by a device. It is an object to provide a peak hold circuit.

[0008]

Means for Solving the Problems To solve the above problems, the present invention employs the following means. In the present invention, in a peak hold circuit that holds a peak value of an input signal as a voltage stored in a capacitor, a differential circuit that determines an absolute value of a difference between the held peak hold value and an input signal, A comparator for comparing the absolute value of the difference due to the differential circuit with the reference signal, and when the comparison result indicates that the output signal of the comparator exceeds an allowable range, a peak timing signal is output until the output signal falls within the allowable range; A peak timing section for repeatedly executing the hold operation, and a reset signal section for setting the held value to the final peak hold value only when the output signal of the comparator is within an allowable range.

In the present invention, the differential circuit performs a function when a reset signal is input.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention.
A description will be given based on FIG. FIG. 1 shows an embodiment of a peak hold circuit according to the present invention. When a positive input signal enters the plus side of an operational amplifier 12 from an input terminal 11, the operational amplifier 12 becomes a positive output, is half-wave rectified by a diode 13, and is then held by a capacitor 15 via a resistor 14. Is done. At this time, if the voltage held by the capacitor 15 is lower than the output voltage of the operational amplifier 12, the capacitor 15 is charged through the diode 13 and the resistor 14.

Since the voltage charged in the capacitor 15 is fed back to the minus side of the operational amplifier 12 through the operational amplifier 16, the voltage input to the plus side of the operational amplifier 12 is held, and the held voltage is output from the output terminal 17. It is designed to be output as a signal. In FIG. 1, reference numeral 18 denotes a diode for preventing backflow, and 19 denotes a transistor.

In this embodiment, a differential circuit 21 for obtaining an absolute value of a difference between an output signal and an input signal of an operational amplifier 16 and a comparator 22 for comparing a signal from the differential circuit with a reference value are provided. If there is a difference as a result of the comparison, a hold timing unit 23 that repeatedly outputs a hold command until the difference falls within a predetermined range (threshold), and stops the hold command when the difference enters a predetermined range. And a reset signal section 24.

The differential circuit 21 has its input connected to the output of the operational amplifier 16 and the input terminal 11, and takes in the output signal from the operational amplifier 12 and the input signal from the input terminal 11 to obtain the differential signal. It outputs the absolute value of the difference. The comparator 22 has its input connected to the output of the differential circuit 21 and connected to a preset reference voltage (ref), and outputs the difference between the output signal from the differential circuit 21 and the reference voltage. And outputs (H, L) whether there is a difference or not.

The hold timing section 23 waits for a command from a reset signal section 24 to be described later when the result of the comparison by the comparator 22 is within a predetermined allowable range (threshold). Is designed to repeatedly output a timing signal so that the difference falls within an allowable range, and hold the timing signal each time. That is, the hold timing unit 23 repeatedly outputs and holds the timing signal only when the output of the comparator 22 is large as a result of the comparison, so that the timing signal falls within the allowable range.

On the other hand, although not shown in detail, the reset signal section 24 outputs a reset signal to the hold timing section 23 when the comparison result of the comparator 22 enters an allowable range (threshold), The value within the range is held by the capacitor 15 as a final peak hold value. Therefore, although not shown in detail, the reset signal unit 24 monitors the output from the comparator 22, and only when the difference between the comparison results falls within the allowable range,
The reset signal is output to the hold timing unit 23, for example, by a CPU.

The hold circuit configured as described above has
When an input signal enters the plus side of the operational amplifier 12 from the input terminal 11, the operational amplifier 12 becomes a positive output, is half-wave rectified by the diode 13, and is held by the capacitor 15 via the resistor 14. At this time, the differential circuit 21 calculates the absolute value of the difference between the signal corresponding to the voltage held by the capacitor 15 and the current input signal, and then compares the difference with the comparator 22. As a result of the comparison by the comparator 22, if the difference due to the differential circuit 21 exceeds a predetermined allowable range (threshold), the peak timing unit 23 repeatedly outputs a timing signal so as to fall within the allowable range, and the capacitor 15 It will be repeatedly held again. When the comparison result of the comparator 22 falls within the allowable range, a reset signal is input from the reset signal unit 24 to the hold timing unit 23 at that time, and the voltage held by the capacitor is changed to the final peak hold voltage. And

Therefore, this peak hold circuit
The difference between the value held in the capacitor 15 and the input value is monitored, and when the difference exceeds the allowable range, the hold is repeated, and only when the difference is within the allowable range, the final peak hold voltage is set. In addition to the influence of the dielectric absorptance constituting the capacitor 4 unlike the prior art, it is not necessary to select the number of times of taking in the actual device, and a stable peak hold value can be accurately obtained. be able to. Such a peak hold circuit is useful for holding a signal whose input (near the peak) signal changes relatively slowly, for example, a rectangular wave, or a peak such as a temperature such as a thermistor or a thermocouple.

FIG. 2 shows another embodiment. This embodiment is different from the above-described embodiment in that when the differential circuit 21 calculates the difference between the voltage signal held by the capacitor 15 and the current input signal, the reset signal from the reset signal unit 24 is used. The calculation is performed only when a signal is output. In FIG. 2, FIG.
The same parts as those described above are given the same reference numerals, and the description of the other parts is omitted.

Therefore, according to this embodiment, the differential circuit 21 functions only when the reset signal from the reset signal section 24 is input, and the comparator 22 and the peak timing section 23 operate accordingly. For example, when the input signal is extremely lowered, if the reset signal is output from the reset signal unit 24, the electric charge stored in the capacitor 15 can be released and held in response to the reset signal. As a result, even if a signal that is changing is input, it can follow the input signal. As a result, even if an extremely low signal is input, it can be reliably held as a new peak value.

[0020]

As described above, according to the present invention, the difference between the held value and the input value is monitored, and if the difference exceeds the allowable range, the hold is repeated and the hold is repeated. Only when it is in the range, the final peak hold voltage is used, so not only is it not affected by the influence of the dielectric absorptance that constitutes the capacitor, but it is not necessary to select the number of captures by the actual device, and it is stable. There is an effect that the obtained peak hold value can be accurately obtained.

Further, according to the present invention, the differential circuit functions only when the reset signal from the reset signal section 24 is input, and even if a signal that drops extremely is input, it is reliably held as a new peak value. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a peak hold circuit according to the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the peak hold circuit according to the present invention.

FIG. 3 is a circuit diagram showing a conventional peak hold circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input terminal 12, 16 Operational amplifier 13 Diode 15 Capacitor 21 Differential circuit 22 Comparator 23 Hold timing part 24 Reset signal

Claims (2)

[Claims] A peak hold circuit for holding a peak value of an input signal as a voltage stored in a capacitor, wherein the differential circuit obtains an absolute value of a difference between the held peak hold value and an input signal. A comparator for comparing the absolute value of the difference caused by the differential circuit with the reference signal, and when the comparison result indicates that the output signal of the comparator exceeds an allowable range, a peak timing signal is output until the output signal falls within the allowable range. A peak hold circuit comprising: a peak timing section for repeatedly executing a peak hold operation; and a reset signal section for setting a held value to a final peak hold value only when an output signal of the comparator is within an allowable range. . 2. The peak hold circuit according to claim 1, wherein the differential circuit executes a function when a reset signal is input.