JP2002288982A - Input/output line sense amplifier for memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output line sense amplifier of a semiconductor memory in which current consumption and DC current are suppressed. SOLUTION: This amplifier is provided with a current sense circuit sensing a current of an input/output line and a complementary input/output line, a first amplifier bypassing first current of same quantity from the input/output line and the complementary input/output line, amplifying and reversing an output signal of the current sense circuit utilizing the first current, and outputting it to a first output end, and a second amplifier bypassing second current of same quantity from the input/output line and the complementary input/output line, amplifying and reversing an output signal of the current sense circuit utilizing the second current, and outputting it to a second output end. Current consumption and DC current are suppressed by including no voltage sense type amplifier constituted of differential amplifiers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to an input / output line sense amplifier of a semiconductor memory device.

[0002]

2. Description of the Related Art As shown in FIG. 1, in a semiconductor memory device, during a read operation, data stored in a predetermined memory cell 111 in a memory cell array 11 is sensed via a bit line pair BL and BLB. The signal is amplified by the amplifier 112. The amplified signal is transmitted to the local input / output line pair IO, IOB and the global input / output line pair DIO, DIOB via the column selection transistors 113, 114. Next, the data of the global input / output line pair DIO, DIOB is amplified again by the input / output line sense amplifier 13, and the amplified data is output to the outside via the output buffer 15 via the input / output pin DQ. .

In general, an input / output line sense amplifier 13
Is composed of a current sensing amplifier (CSA) or a voltage sensing amplifier (VSA). I / O line pair DIO,
Since the voltage difference of DIOB is very small at the time of read operation, CSA which is faster in speed than VSA is more widely used. However, since the voltage level of the CSA output signal is small, the CSA output signal is immediately latched by the CSA.
When converted to the MOS level, there is a problem that the speed is reduced.

Accordingly, as shown in FIG. 1, in the input / output line sense amplifier 13, the output signal of the CSA
The SA 132 amplifies once more, and this amplified signal is used as an input to the latch 133. Latch 133 is VS
It serves to convert the signal amplified by A132 to a CMOS level.

FIG. 2 is a circuit diagram showing an example of the CSA 131 shown in FIG. Here, Mp11 and Mp12 indicate PMOS transistors, and Mn11 to Mn13 indicate NMOS transistors. DIO and DIOB indicate an input / output line pair DIO and DIOB, and EN indicates an enable signal.

FIG. 3 is a circuit diagram showing an example of the VSA 132 shown in FIG. Referring to FIG.
It can be seen that 2 is composed of a differential amplifier. Where M
p31 to Mp34 indicate PMOS transistors, and Mn
31 to Mn35 indicate NMOS transistors. O1 and O1B indicate output signal pairs of the CSA 131, and EN indicates an enable signal.

FIG. 4 is a circuit diagram showing an example of the latch 133 shown in FIG. Here, Mp41 to Mp44 indicate PMOS transistors, and Mn41 to Mn43 indicate N
2 shows a MOS transistor. O2 and O2B are VSA1
32 indicates an output signal pair, and LAT indicates a latch enable signal. DOUT and DOUTB are output signal pairs of the latch 133, and represent output signal pairs of the input / output line sense amplifier 13 shown in FIG.

However, the conventional input / output line sense amplifier described above has a problem that the current consumption is large, and in particular, the DC current becomes large by including the VSA 132 constituted by a differential amplifier.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and for example, it is an object of the present invention to provide an input / output line sense amplifier for a semiconductor memory device in which current consumption and DC current are suppressed. Aim.

[0010]

According to an aspect of the present invention, there is provided an input / output line sensing amplifier for sensing a signal current and a complementary current thereof. A current sensing circuit for sensing a first portion of the signal current and a first portion of the complementary current in the line sense amplifier; and a signal for generating a first output signal from a first detection output of the current sensing circuit. A first portion that operates upon receiving a second portion of the current and a second portion of the complementary current;
An amplifier, a second amplifier operable to receive and operate a third portion of the signal current and a third portion of the complementary current to generate a second output signal from a second detection output of the current sensing circuit; A latch is provided for receiving the first output signal and the second output signal generated by the first amplifier and the second amplifier.

According to a preferred embodiment of the present invention, the second portion of the signal current is equal in amount to the second portion of the complementary current.

According to a preferred embodiment of the present invention, the first amplifiers are connected to each other and connected to the first of the current sensing circuits.
A first transistor and a second transistor controlled by a detection output; and a third transistor connected to the first transistor and the second transistor and controlled by a first detection output of the current sensing circuit, wherein the first transistor is Upon receiving a second portion of the signal current, the third transistor receives a second portion of the complementary current.

According to a preferred embodiment of the present invention, the ratio of the channel length to the channel width of the first transistor (W /
L) is equal to the ratio between the channel length and the channel width of the second transistor.

According to another embodiment of the present invention, there is provided an input / output line sense amplifier for sensing currents of an input / output line and a complementary input / output line, the input / output line, A first amplifier for bypassing the same amount of the first current from the complementary input / output line, amplifying and inverting an output signal of the current sensing circuit using the first current, and outputting the amplified signal to a first output terminal; A second current that bypasses the same amount of the second current from the output line and the complementary input / output line, amplifies and inverts the complementary output signal of the current sensing circuit using the second current, and outputs the amplified signal to the second output terminal. An amplifier is provided.

According to a preferred embodiment of the present invention, the current sensing circuit comprises: a first current sensing transistor connected between the input / output line and a first node to which the output signal is output; A second current sensing transistor connected between the input / output line and a second node to which the complementary output signal is output; a first load transistor connected between the first node and a ground voltage; A second load transistor connected between two nodes and the ground voltage.

According to a preferred embodiment of the present invention, the first amplifier is connected between the complementary input / output line and the first output terminal, and is controlled by the output signal of the current sensing circuit. A first transistor, a second transistor connected between the input / output line and the first output terminal and controlled by the output signal of the current sensing circuit, and a second transistor between the first output terminal and the ground voltage; A third transistor connected to and controlled by the output signal of the current sensing circuit.

According to a preferred embodiment of the present invention, the second amplifier is connected between the input / output line and the second output terminal, and is controlled by the complementary output signal of the current sensing circuit. A fourth transistor connected between the complementary input / output line and the second output terminal, a fifth transistor controlled by the complementary output signal of the current sensing circuit, and a fourth transistor connected between the second output terminal and the ground voltage; Connected between
A sixth transistor controlled by the complementary output signal of the current sensing circuit.

According to a preferred embodiment of the present invention, the channel width and the channel length of the first transistor are equal to those of the second transistor.
It is preferable that the channel width and the channel length of the transistor be equal. It is preferable that a channel width and a channel length of the fourth transistor are equal to a channel width and a channel length of the fifth transistor.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Like reference numerals present in each drawing indicate the same or corresponding elements.

FIG. 5 is a circuit diagram of an input / output line sense amplifier of a semiconductor memory device according to a preferred embodiment of the present invention.

Referring to FIG. 5, an input / output line sensing amplifier according to an embodiment of the present invention includes a current sensing circuit 51 and a first sensing circuit.
It can be seen that the amplifier 53, the second amplifier 55, the enable unit 59, and the latch 57 are provided.

The current sensing circuit 51 senses currents of an input / output line pair for transmitting data read from a predetermined memory cell in the semiconductor memory device, that is, an input / output line DIO and a complementary input / output line DIOB. The first amplifier 53 includes an input / output line DIO and a complementary input / output line DI.
The same amount of the first current α is bypassed from the OB and the first current α
And amplifies and inverts the output signal V1P of the current sensing circuit 51 and outputs the amplified signal to the first output terminal O. Second amplifier 55
Is the input / output line DIO and the complementary input / output line DIOB
, The second current β of the same amount is bypassed, and the complementary output signal V2P of the current sensing circuit 51 is amplified and inverted using the second current β and output to the second output terminal OB.

The enable unit 59 includes an enable signal EN
In response to the current sensing circuit 51, the first amplifier 53, and the second
Enable the amplifier 55. The latch 57 latches the signal of the first output terminal O and the signal of the second output terminal OB, and
Convert to level and output.

The configuration of each element will be described below. The current sensing circuit 51 includes two PMOS transistors Mp5
1, Mp52 and two NMOS transistors Mn51,
Mn52. The PMOS transistor Mp51 is a current sensing transistor that senses the current of the input / output line DIO, and is connected between the input / output line DIO and a node from which the output signal V1P is output. PM
The OS transistor Mp52 is connected to the complementary input / output line DIO.
A current sensing transistor that senses the current of B, and is connected between the complementary input / output line DIOB and a node from which the complementary output signal V2P is output.

The PMOS transistor Mp51 and the PMOS
The transistor Mp52 is cross-coupled. That is, the gate of the PMOS transistor Mp51 is connected to a node at which the complementary output signal V2P is output, and the gate of the PMOS transistor Mp52 is connected to a node at which the output signal V1P is output.

The NMOS transistor Mn51 is a load transistor serving as a resistor, and has an output signal V1P
Is output between the common node N and the node from which the is output. The NMOS transistor Mn51 outputs the output signal V1P
The drain and the gate are commonly connected to the node from which is output, and functions as a diode. The NMOS transistor Mn52 is also a load transistor that plays the role of a resistor, and is connected between a node from which the complementary output signal V2P is output and the common node N. NMOS transistor Mn5
2 has a drain and a gate commonly connected to a node to which the complementary output signal V2P is output, and functions as a diode.

The first amplifier 53 includes two PMOS transistors Mp53 and Mp54 and one NMOS transistor Mn53.

The PMOS transistor Mp53 is connected between the complementary input / output line DIOB and the first output terminal O,
It is controlled by the output signal V1P of the current sensing circuit 51.
The PMOS transistor Mp54 is connected to the input / output line DIO.
, And is controlled by the output signal V1P of the current sensing circuit 51. The NMOS transistor Mn53 is connected between the first output terminal O and the common node N, and is controlled by the output signal V1P of the current sensing circuit 51. It is desirable that the channel width and the channel length of the PMOS transistor Mp53 are equal to the channel width and the channel length of the PMOS transistor Mp54.

The second amplifier 55 includes two PMOS transistors Mp55 and Mp56 and one NMOS transistor Mn54.

The PMOS transistor Mp55 is connected between the input / output line DIO and the second output terminal OB, and is controlled by a complementary output signal V2P of the current sensing circuit 51.
The PMOS transistor Mp56 has a complementary input / output line D
It is connected between the IOB and the second output terminal OB, and is controlled by a complementary output signal V2P of the current sensing circuit 51. NMO
The S transistor Mn54 is connected between the second output terminal OB and the common node N, and is controlled by a complementary output signal V2P of the current sensing circuit 51. PMOS transistor Mp
It is desirable that the channel width and the channel length of 55 are equal to the channel width and the channel length of the PMOS transistor Mp56.

The enable unit 59 is connected between the common node N and the ground voltage VSS and includes an NMOS transistor Mn55 controlled by the enable signal EN.

The enable unit 59 may not be included in the input / output line sense amplifier of FIG. 5 if necessary. In this case, one ends of the NMOS transistors Mn51 to Mn54 are directly connected to the ground voltage VSS.

Hereinafter, the configuration and operation of the input / output line sense amplifier according to the preferred embodiment of the present invention will be further described with reference to FIG. The input / output line sensing amplifier shown in FIG. 5 is a circuit in which a current sensing circuit 51 and amplifiers 53 and 55 are mixed. The current sensing circuit 51 is optimized so that the input resistance value becomes almost 0 in order to maximize the input current, and the input / output line DIO and the complementary input / output line DIOB have almost the same voltage level.

On the other hand, in the first amplifier 53, the PMOS
The channel width and channel length of the transistor Mp53 are P
If the channel width and the channel length of the MOS transistor Mp54 are equal to each other,
MOS transistor Mp54 has the same VGS (voltage between gate and source). Accordingly, the PMOS transistor Mp53 and the PMOS transistor Mp54 each supply the same amount of the first current α to the complementary input / output line DI.
Bypass from OB and input / output line DIO.

In the second amplifier 55, the channel width and the channel length of the PMOS transistor Mp55 are PM
If the channel width and the channel length of the OS transistor Mp56 are equal to each other, the PMOS transistors Mp55 and PMp
The OS transistor Mp56 has the same VGS. Accordingly, the PMOS transistor Mp55 and the PMOS transistor Mp56 respectively bypass the same amount of the second current β from the input / output line DIO and the complementary input / output line DIOB.

Thus, in the current sensing circuit 51, N
The current flowing through the MOS transistor Mn51 is I1-α-
becomes β, and the current flowing through the NMOS transistor Mn52 becomes I2-α-β. Where I1 is the input / output line DI
O2 is a current flowing through the complementary input / output line DIOB. Therefore, the difference between the two currents becomes I1-I2, and the magnitude of the differential input current is not affected.

The PMOS transistors Mp53 and PMO
The first current α bypassed by the S transistor Mp54 is used to amplify the output signal V1P of the current sensing circuit 51. That is, the PMOS transistors Mp53 and Mp54 of the first amplifier 53 and the NMOS transistor Mp
n53 forms one inverter, and the inverter uses the first current α to output the output signal V of the current sensing circuit 51.
Amplify and invert 1P.

The bias voltage for operating the first amplifier 53 having the function as an inverter under the optimum bias condition is provided by the output signal V1P of the current sensing circuit 51. This is because the output signal V1P forms an operating point near the threshold voltage of the inverter due to the voltage distribution effect of the PMOS transistor Mp51 and the NMOS transistor Mn51. In other words, W / L (W is the channel width of the transistor and L / L
Is the channel length of the transistor).
51 = (Mp53 + Mp54): If optimized to Mn53, V1P automatically supplies a bias voltage having a value near the threshold voltage of the inverter, independent of temperature and process variations.

The PMOS transistors Mp55 and PMO
The second current β bypassed by the S transistor Mp56 is used to amplify the complementary output signal V2P of the current sensing circuit 51. That is, the PMOS of the second amplifier 55
The transistors Mp55 and Mp56 and the NMOS transistor Mn54 form one inverter, and the inverter amplifies and inverts the complementary output signal V2P of the current sensing circuit 51 using the second current β.

The bias voltage for operating the inverter type second amplifier 55 under the optimum bias condition is provided by the complementary output signal V2P of the current sensing circuit 51. This is because the output signal V2P is the PMOS transistor Mp52.
And an NMOS transistor Mn52 to form an operating point near the threshold voltage of the inverter. In other words, W / L is Mp5
2: Mn52 = (Mp55 + Mp56): If optimized to be Mn54, V2P automatically supplies a bias voltage having a value near the threshold voltage of the inverter, independent of temperature and process variations.

As described above, according to the preferred embodiment of the present invention, the input / output line sensing amplifier is a circuit in which the current sensing circuit 51 and the amplifiers 53 and 55 are mixed. It does not include a VSA composed of a dynamic amplifier. Accordingly, the preferred embodiments of the present invention have been described with reference to the drawings and the specification, which can provide an input / output line sense amplifier of a semiconductor memory device with reduced current consumption and DC current. Certain terms used in the present invention are used merely for the purpose of describing the present invention and limit the meaning or limit the scope of the present invention described in the claims. It was not used for. Therefore, it will be understood by those skilled in the art that various modifications and equivalent embodiments can be made without departing from the concept of the present invention.
Therefore, the scope of the present invention is given by the technical idea which belongs to a claim.

[0042]

According to the present invention, for example, an input / output line sense amplifier of a semiconductor memory device in which current consumption and DC current are suppressed can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a read data path of a semiconductor memory device.

FIG. 2 is a circuit diagram showing an example of the CSA shown in FIG.

FIG. 3 is a circuit diagram showing an example of the VSA shown in FIG. 1;

FIG. 4 is a circuit diagram showing an example of the latch shown in FIG. 1;

FIG. 5 is a circuit diagram of an input / output line sense amplifier of a semiconductor memory device according to a preferred embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 51 Current sensing circuit 53 First amplifier 55 Second amplifier 57 Latch Mp51, 52, 53, 54, 55, 56 PMOS transistor Mn51, 52, 53, 54, 55 NMOS transistor

Claims (11)

[Claims] 1. An input / output line sense amplifier for a semiconductor memory device for sensing a signal current and its complementary current, comprising: a current sensing circuit for sensing a first portion of the signal current and a first portion of the complementary current; A first amplifier operable to receive a second portion of the signal current and a second portion of the complementary current to generate a first output signal from a first detection output of the current sensing circuit; A second amplifier operable to receive a third portion of the signal current and a third portion of the complementary current to generate a second output signal from the second detection output of the first and second amplifiers; A latch for receiving the first output signal and the second output signal generated by the amplifier. 2. The input / output line sense amplifier of claim 1, wherein the second portion of the signal current is equal in amount to the second portion of the complementary current. 3. The first amplifier is connected to a first transistor and the second transistor connected to each other and controlled by a first detection output of the current sensing circuit, and connected to the first transistor and the second transistor. A third transistor controlled by a first detection output of the current sensing circuit, the first transistor receiving a second portion of the signal current, and the third transistor receiving a second portion of the complementary current. The input / output line sense amplifier according to claim 1, wherein the input / output line sense amplifier receives the signal. 4. The device according to claim 3, wherein a ratio between a channel length and a channel width of the first transistor is equal to a ratio between a channel length and a channel width of the second transistor.
2. An input / output line sense amplifier according to claim 1. 5. The input / output line sense amplifier of a semiconductor memory device for sensing an input / output line transmitting data read from a memory cell and a complementary input / output line. A first current of the same amount is bypassed from the input / output line and the complementary input / output line, and an output signal of the current detection circuit is amplified and inverted using the first current; A first amplifier that outputs to a first output terminal, and a second current of the same amount is bypassed from the input / output line and the complementary input / output line, and a complementary output signal of the current sensing circuit is used by using the second current. Amplify and invert the second
An input / output line sense amplifier for a semiconductor memory device, comprising: a second amplifier that outputs an output signal. 6. The current sensing circuit, comprising: a first current sensing transistor connected between the input / output line and a first node to which the output signal is output; a complementary input / output line and the complementary output signal A second current sensing transistor connected between the first node and a ground voltage; a second load transistor connected between the first node and a ground voltage; Second connected between
6. A load transistor, comprising: a load transistor.
10. The input / output line sense amplifier of the semiconductor memory device according to claim 1. 7. The first amplifier connected between the complementary input / output line and the first output terminal, a first transistor controlled by the output signal of the current sensing circuit, and the input / output line. And the first output terminal.
A second controlled by the output signal of the current sensing circuit;
7. The semiconductor memory according to claim 6, further comprising: a transistor; and a third transistor connected between the first output terminal and the ground voltage and controlled by the output signal of the current sensing circuit. Device input / output line sense amplifier. 8. The second amplifier is connected between the input / output line and the second output terminal,
A fourth transistor controlled by the complementary output signal of the current sensing circuit, a fourth transistor connected between the complementary input / output line and the second output terminal and controlled by the complementary output signal of the current sensing circuit; A fifth transistor connected between the second output terminal and the ground voltage and controlled by the complementary output signal of the current sensing circuit;
The I / O line sense amplifier of a semiconductor memory device according to claim 7, further comprising a transistor. 9. The input / output line sense amplifier, comprising: a third node to which one end of the first load transistor, one end of the second load transistor, one end of the third transistor, and one end of the sixth transistor are commonly connected. 9. The power supply of claim 8, further comprising an enable unit connected between the current sense circuit and the ground voltage to enable the current sensing circuit, the first amplifier, and the second amplifier in response to an enable signal. Input / output line sense amplifier for semiconductor memory devices. 10. The amplifier of claim 7, wherein a channel width and a channel length of the first transistor are equal to a channel width and a channel length of the second transistor. 11. The input / output line sense amplifier of claim 8, wherein the channel width and the channel length of the fourth transistor are equal to the channel width and the channel length of the fifth transistor.