KR19990004899A - Cross-coupled sense amplifiers in semiconductor devices - Google Patents

Abstract

The present invention relates to a cross-coupled sense amplifier of a semiconductor device that can reduce power consumption by reducing the current consumption, and detects the voltage difference between the bit line and the inverted bit line by a sense enable signal, and outputs an output terminal and an inverted output terminal. A cross-coupled sense amplifier of an output semiconductor device, comprising: storage means for temporarily storing a signal that is enabled by the sense-amplified signal and sense-amplified.

Description

Cross-coupled sense amplifiers in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a cross-coupled sense amplifier of a semiconductor device capable of reducing power consumption by reducing current consumption.

In general, sense amplifiers are widely used in DRAM circuits, and these sense amplifiers only amplify the difference between the two input stage voltages, and the voltages commonly input to the two terminals do not affect the output. When the signal line of is used as the input of the sense amplifier, the electrical noise commonly induced in the signal line has no effect on the output and can only amplify the differential signal. Sense amplifiers include current mirrors with different input and output nodes, and cross-couple types with shared input and output nodes.

Cross-coupled sense amplifiers are also called latched amplifiers because they can amplify the signal from the supply voltage to ground and latch the amplified voltage. Like the bit line sense amplifier that amplifies the cell data, the input and output lines are the same, so data detection and rewriting can be performed simultaneously, which is advantageous for low power.

A conventional cross-coupled sense amplifier for sensing and amplifying a voltage difference between a bit line and an inverted bit line of a semiconductor memory device will be described with reference to FIG. 1.

Referring to FIG. 1, a conventional cross-coupled sense amplifier includes a differential amplification NMOS transistor NM1 and an NMOS transistor NM2 having a bit line BL and an inverted bit line / BL connected to a gate, respectively. The power supply voltages are respectively connected to the source, the drains are commonly connected to the drains of the differential amplification NMOS transistor NM1 and the NMOS transistor NM2, respectively, and the gates of the differential amplification NMOS transistor NM1 and the NMOS transistor NM2 are respectively. PMOS transistor PM1 and PMOS transistor PM2 cross-connected to the drain.

In addition, the conventional cross-coupled sense amplifier is connected between the output node (OND) and the inverted output node (/ OND), the output node (OND) and inverted output by the sense enable signal (SE) applied to the gate A differential amplification NMOS transistor NM1 and NMOS transistor NM2 are driven by the equalizing PMOS transistor PM3 for equalizing the voltage of the node / OND and the sense enable signal SE applied to the gate. And a current source NMOS transistor NM3.

Referring to the operation of the conventional cross-coupled sense amplifier having the above structure is as follows.

When the high sense enable signal SE is applied, the equalizing PMOS transistor PM3 equalizes the voltage at the output terminal OND and the inverting output node / OND.

In addition, the current source NMOS transistor NM3 is turned on so that the differential amplification NMOS transistors NM1 and NM2 sense and amplify the voltage difference between the bit line BL and the inverting bit line / BL.

That is, when the voltage of the bit line BL is higher than the voltage of the inverting bit line / BL, the differential amplification NMOS transistor NM1 is turned on relatively larger than the differential amplification NMOS transistor NM2, so that the PMOS transistor PM2 is turned on. ) Is relatively lower than the gate voltage of the PMOS transistor PM1, so that the PMOS transistor PM2 is turned on more strongly than the PMOS transistor PM1.

Therefore, the differential amplification NMOS transistor NM1 differentially amplifies the voltage of the bit line BL and outputs it through an output terminal (not shown) connected to the output node OND.

On the contrary, when the voltage of the bit line BL is lower than the voltage of the inverting bit line / BL, the differential amplification NMOS transistor NM2 is turned on relatively larger than the differential amplification NMOS transistor NM1, so that the PMOS transistor ( The gate voltage of PM1 is relatively lower than the gate voltage of PMOS transistor PM2 so that PMOS transistor PM1 is turned on more strongly than PMOS transistor PM2.

Accordingly, the differential amplification NMOS transistor NM2 differentially amplifies the voltage of the inverting bit line / BL and outputs it through an output terminal (not shown) connected to the inverting output node / OND.

The operating characteristics of the cross-coupled sense amplifier of the conventional semiconductor device will be described with reference to FIG. 2A.

Referring to FIG. 2A, (a) is a voltage characteristic of the bit line BL, (b) is a voltage characteristic of the inverting bit line / BL, (c) is a characteristic of the sense enable signal SE, and (d Is the voltage characteristic of the output node OND, and (e) is the voltage characteristic of the inverted output node / OND.

As shown in FIG. 2A, in a period in which the voltage a of the bit line BL is relatively higher than the voltage b of the inverting bit line / BL, and the sense enable signal c of the high state is applied, the output The signal d of the node OND goes high, and the signal e of the inverted output terminal / OND goes low.

Fig. 2B shows a characteristic diagram of the current of a cross-coupled sense amplifier of a conventional semiconductor device.

However, the cross-coupled sense amplifier of the conventional semiconductor device as described above has a problem that the current is consumed by sensing and amplifying the voltage difference between the bit line and the inverted bit line only by applying a sense enable signal for a relatively long time. Existed.

Accordingly, the present invention is to solve the above problems, by reducing the application time of the sense enable signal by storing the signal sensed and amplified using a plurality of MOS transistors, the current consumption of the semiconductor device can be reduced The object is to provide a cross-coupled sense amplifier.

1 is a circuit diagram of a cross-coupled sense amplifier of a conventional semiconductor device.

2A and 2B are characteristic diagrams of a cross-coupled sense amplifier of a conventional semiconductor device.

3 and 4 are circuit diagrams of a cross-coupled sensing vapor of a semiconductor device according to an embodiment of the present invention.

5A and 5B are characteristic diagrams of a cross-coupled sense amplifier of a semiconductor device according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: storage means 20: precharge branch

21: first precharge means 22: second precharge means

The present invention for achieving the above object, in the cross-coupled sense amplifier of the semiconductor device for detecting the voltage difference between the bit line and the inverted bit line by the sense enable signal and outputs through the output terminal and the inverted output terminal, And storage means for temporarily storing the sensed amplified signal that is enabled by the amplified signal.

A cross-coupled sense amplifier of a semiconductor device according to an embodiment of the present invention, the low voltage is applied to the storage means further comprises a precharge unit for precharging the voltage to an appropriate level.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Referring to FIGS. 3 and 4, the cross-coupled sense amplifier of the semiconductor device of the present invention, as in FIG. 1, has a differential amplification NMOS transistor NM1 and an NMOS transistor NM2, and a gate having a differential amplification NMOS transistor ( PMOS transistors PM1 and PMOS transistor PM2 cross-connected to the drains of NM1 and NMOS transistor NM2, equalizing PMOS transistor PM3, and NMOS transistor NM3 for current source.

In addition, the cross-coupled sense amplifier of the present invention has a storage unit 10 for temporarily storing a signal that is enabled and sensed by the sense-amplified signal, and a proper voltage when a low voltage is applied to the storage unit 10. It is further provided with a precharge section 20 for precharging to a level.

The storage unit 10 is composed of an SR flip-flop.

The precharge unit 20 includes a first precharge unit 21 for precharging one input terminal of the storage unit 10 and a second precharge unit for precharging the type force stage of the storage unit 10. It consists of 22.

The SR flip-flop includes a first CMOS inverter composed of a PMOS transistor PM4 and an NMOS transistor NM4 to which a signal of an output node OND is applied to a gate through an input terminal S, and an input terminal R. A second CMOS inverter including a PMOS transistor PM5 and an NMOS transistor NM5 to which a signal of the inverted output node / OND is applied to a gate through the PMOS transistor PM5 and the NMOS transistor NM5 of the second CMOS inverter. A third CMOS inverter consisting of a PMOS transistor PM6 and an NMOS transistor NM6 having an output terminal Q connected to a gate connected to a common connected drain thereof, a PMOS transistor PM4 of a first CMOS inverter, and The output terminal QB connected to the common connected drain of the NMOS transistor NM4 consists of a fourth CMOS inverter composed of a PMOS transistor PM7 and an NMOS transistor NM7 connected to the gate, respectively.

The first precharge unit 21 has a sense enable signal SE applied to a gate thereof, and includes a PMOS transistor PM8 connected between the power supply voltage and the storage unit 20.

The second precharge unit 22 has a sense enable signal SE applied to a gate thereof, and includes a PMOS transistor PM9 connected between the power supply voltage and the storage unit 20.

Referring to the operation of the cross-coupled sense amplifier of the present invention having the structure as described above is as follows.

Operation descriptions that overlap with those described in FIG. 1 will be omitted.

When the sense enable signal SE of the high state is applied, the differential amplification NMOS transistors NM1 and NM2 sense and amplify the voltage difference between the bit line BL and the inverting bit line / BL applied to the gate, respectively. Then, the sensed amplified signal is transferred to the input terminals S and R of the SR-flip flop of the storage unit 20 through the output node OND and the inverted output node / OND, and then the storage unit 10 ) Stores the input signals that are enabled and input according to the sensed amplified signals respectively input.

Subsequently, even when the sense enable signal SE is switched to the low state, the voltages of the output node OND and the inverted output node OND are equalized by the equalizing PMOS transistor PM3, and in this case, the SR flip-flop The input terminal (S, R) recognizes the high state and maintains the storage state.

The SR flip-flop of the storage unit 10 outputs the stored signals through the output terminals Q and QB when the sense enable signal SE in the low state is switched back to the high state.

That is, when the signal of the output node OND applied to the input terminal S is high and the signal of the inverted output node / OND applied to the input terminal R is low, The SR-flip-flop temporarily stores the input signals after being reset and outputs a high signal to the output terminal QB, and outputs a low signal through the output terminal Q.

On the contrary, when the signal of the output node OND applied to the input terminal S is low and the signal of the inverted output node / OND applied to the input terminal R is high, the storage unit 10 The SR flip-flop is set to temporarily store the input signal, output a low signal through the output terminal QB, and output a high signal through the output terminal Q.

On the other hand, when the sense enable signal SE is low, if a very low voltage is applied to the input terminals S and R of the SR-flip-flop of the storage unit 10, the SR-flip-flop is an input terminal. Since the voltage of the (S, R) is recognized as low and the signal cannot be stored, the precharge unit 20 applies a voltage to maintain the input terminals S and R of the SR flip-flop high. give.

Accordingly, the cross-coupled sense amplifier of the present invention can temporarily store the sense-amplified signal using the SR-flip-flop even when the sense enable signal SE is low. Since the enable signal SE does not have to be maintained for a long time, the amount of current consumed when applying the sense enable signal SE in the high state can be reduced.

The operating characteristics of the cross-coupled sense amplifier of the semiconductor device of the present invention will be described with reference to FIG. 5A. Referring to FIG. 5A, (a) is a voltage characteristic of a bit line BL, and (b) is an inverted bit line. Voltage characteristic of (/ BL), (c) is characteristic of sense enable signal SE, (d) is voltage characteristic applied to input terminal S, (e) is voltage applied to input terminal R The characteristic (f) is the voltage characteristic of the output terminal Q, and (g) is the output characteristic of the output terminal QB.

As shown in FIG. 5A, in a period in which the voltage a of the bit line BL is relatively higher than the voltage b of the inverting bit line / BL, and the sense enable signal c of the high state is applied, the SR The high signal d is applied to the input terminal S of the flip-flop, the low signal e is applied to the input terminal R of the SR-flop flop, and the output terminal Q of the output terminal Q of the SR-flop flop. The signal f goes high, and the signal g of the output terminal QB of the SR-flop flop goes low.

Fig. 5B shows a characteristic diagram of the current of a cross-coupled sense amplifier of a conventional semiconductor device.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

As described above, the cross-coupled sense amplifier of the semiconductor device of the present invention temporarily stores a signal sensed and amplified using the SR-flip-flop even when the sense enable signal is low, thereby applying the sense enable signal. This reduces the current consumption by shortening.

Claims (6)

A cross-coupled sense amplifier of a semiconductor device for detecting a voltage difference between a bit line and an inverted bit line by a sense enable signal and outputting the same through an output terminal and an inverted output terminal. And a storage means for temporarily storing a signal enabled and sensed and amplified by the sense-amplified signal. The method of claim 1, The storage means A cross-coupled sense amplifier of a semiconductor device comprising an SR-flip-flop. The method of claim 1, And a precharge unit for precharging the voltage to an appropriate level when a low voltage is applied to the storage means. The method of claim 3, wherein The precharge section A first precharge unit for precharging one input terminal of the storage unit; And And a second precharge portion for precharging the type force stage of the storage means. The method of claim 4, wherein The first precharge means A sense enable signal is applied to a gate and includes a PMOS transistor coupled between a power supply voltage and the storage means. The method of claim 4, wherein The second precharge means A sense enable signal is applied to a gate and includes a PMOS transistor coupled between a power supply voltage and the storage means.