JP2002288257A - Method and device for power consumption evaluation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method to greatly shorten the time for simulation required for the number of times of toggle for output of each logic gate, in a circuit where power consumption is to be measured. SOLUTION: In the toggle detecting circuit, one-bit registers 101 and 102 are provided and each signal for times t-1 and t-2 is retained for input 100 at a time 't'. '1' is outputted by a detector 103 only for variations of from 0 to 1 and from 1 to 0 at the time 't'. Signals obtained by a detector 102 is added by an accumulator 104. The number of toggles are retained by a register 105 for a number of bits, and a toggle detection circuit 106 and a power consumption measuring circuit are realized to a programmable array, test vector for simulation is inputted and the toggle number of times is obtained by referring the result of the resistor 105, after the simulation is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a power consumption evaluation method and apparatus for preliminarily evaluating the power consumption of an integrated circuit at high speed.

[0002]

2. Description of the Related Art In order to evaluate the power consumption of an integrated circuit in advance, a power consumption analysis tool linked with a software simulator such as Verilog-XL or VCS is used to determine the toggle probability of each logic gate in the integrated circuit. Is simulated, and the power consumption is calculated from the following equation.

The power consumption of an integrated circuit = Σ (Tr × F × (P
0 + ΔPs × Δs + CL × ΔPCL)) Tr: Toggle rate F: Operating frequency P0: Power consumption per unit frequency peculiar to logic gate ΔPs: Power consumption by signal rounding per unit frequency ΔPCL: Power consumption by output load per unit frequency Δs : Signal rounding CL: Output load capacity Tr = Number of toggles / Number of simulation cycles

[0004]

However, as the scale of an integrated circuit increases, the time required to measure the number of toggles of each logic gate increases. It is getting more and more difficult.

On the other hand, the logic verification which has recently been performed by software emulators such as Verilog-XL and VCS is performed by a hardware emulator using a field programmable array at a speed of 10,000 to 100,000 times faster. It is becoming possible.

Accordingly, an object of the present invention is to provide a power consumption evaluation method and apparatus that can greatly reduce the time required for calculating the number of toggles by using a field programmable array as compared with the related art.

[0007]

SUMMARY OF THE INVENTION In view of the above, the present invention provides an integrated circuit function and a power consumption measuring function in a field-programmable array. It is intended to speed up the output of the number of toggles of the logic gate which becomes a bottleneck.

According to a first aspect of the present invention, there is provided a power consumption evaluation method, wherein a power consumption measurement target circuit and a toggle detection circuit for detecting the number of toggles of circuit elements of the power consumption measurement target circuit are configured in a field programmable array. Enter the simulation pattern into the array,
It is characterized in that the number of toggles detected by the toggle detection circuit after the end of the simulation is obtained as the power consumption of the power consumption measurement target circuit.

According to the power consumption evaluation method of the present invention, the simulation time for calculating the number of toggles of each logic gate output of the power consumption measurement target circuit can be significantly reduced as compared with the power consumption evaluation method using the conventional software emulator. , Thus allowing for significant speedups,
Early evaluation of power consumption becomes possible.

According to a second aspect of the present invention, there is provided a power consumption evaluation apparatus comprising: a field programmable array comprising a power consumption measurement target circuit; and a toggle detection circuit for detecting the number of toggles of the output of each logic gate of the power consumption measurement target circuit. Prepared,
A power consumption evaluation device for calculating the number of toggles for measuring the power consumption of a power consumption measurement target circuit by simulation using a field programmable array,
The toggle detection circuit includes a first register that holds the output of each logic gate at time t, a second register that holds the output of each logic gate at time t−1, a first register and a second register. A detector for detecting a toggle change in the output of the register, an adder for accumulating the number of detections of the detector, and a shift register for storing the accumulation result of the adder; Is obtained.

According to the power consumption evaluation device of the present invention, in order to evaluate the power consumption of the integrated circuit, the detection circuit is provided as a means for measuring the number of toggles of each logic gate in the evaluation target block. Logic gate output signal from “Low” to “High” or “High” to “Low”
In order to reliably detect ", a register for holding the output signal of the logic gate at time t and a register for holding the output signal of the logic gate at time t-1 are provided. And a register for accumulating the number of detections of the detector, and a register for storing the accumulation result of the adder. It is realized together with the integrated circuit itself whose power consumption is to be measured, and measures the power consumption of the integrated circuit.

As described above, the function of the function integrated circuit of the toggle detection circuit is realized in the field programmable array, and the power consumption of the integrated circuit is measured. Therefore, in order to model not only the function of the integrated circuit but also the function that can measure the power consumption using the real device called the field programmable array, Since the signal propagation time is reduced, the time required for the simulation can be significantly reduced.

According to a third aspect of the present invention, there is provided a power consumption measuring method for detecting a toggle count of an output of each logic gate of a power consumption measuring circuit by using a document shaping program. Is connected to each output of each logic gate of the text file, and the text file converted into text so that power consumption can be evaluated is
After realizing a general-purpose field programmable array,
The simulation pattern is input to the field programmable array, and the number of toggles of the logic gate is measured.

According to the power consumption evaluation method of the present invention, a toggle circuit is added to the output of each logic gate in the text file describing the power consumption measurement target circuit by a text conversion process using a document conversion program. Since a text file of the added circuit is input to a general-purpose field programmable array, a simple text conversion program and a general-purpose field programmable array can be used to build an integrated circuit function and power consumption measurement function model. Thus, power consumption can be evaluated at low cost.

According to a fourth aspect of the present invention, there is provided a power consumption evaluation method, comprising: a toggle detection circuit for detecting the number of toggling of the output of each logic gate of a power consumption measurement target circuit; and a dedicated field programmable array comprising various logic gates. After the toggle detection circuit is automatically connected to the output of each logic gate whose power consumption is to be measured in the dedicated field programmable array, the number of toggles of the logic gate output is measured by the toggle detection circuit.

According to the power consumption evaluation method of the fourth aspect, the function of the circuit to be measured and the power consumption measurement function are realized in a dedicated field programmable array in which a large number of toggle circuits and general-purpose logic gates are integrated in advance. The logic that implements the function of the integrated circuit itself and the logic that implements the power consumption measurement function are completely separated from each other, making it possible to implement an integrated circuit model capable of measuring power consumption in a field programmable array. It takes less time to do it.

According to a fifth aspect of the present invention, in the third or fourth aspect, a toggle detection circuit is connected to the clock when the clock is present in the power consumption measurement target circuit and the clock is uncontrolled. It does not.

According to the power consumption evaluation method of the fifth aspect, in addition to the same effects as those of the third and fourth aspects, since the clock without control has the number of toggles corresponding to the operating frequency, it can be easily calculated. Therefore, it is possible to reduce the number of points at which the toggle detection circuit is connected, compared to a case where this method is not used.

According to a sixth aspect of the present invention, there is provided a power consumption evaluation method according to the fifth aspect, wherein the power consumption evaluation method includes:
Logic gate output more than input, flip-flop output,
It connects the toggle detection circuit to the latch output or output of the memory.

According to the power consumption evaluation method according to the sixth aspect, in addition to the same effects as the fifth aspect , in the power consumption analysis target circuit, a logic gate having two or more inputs other than the connection of the clock according to the fifth aspect. Since the toggle detection circuit is connected only to the output, flip-flop output, latch output, and memory output, the number of toggles of two or more logic gate outputs, flip-flop outputs, latch outputs, and memory outputs can be measured. Since the number of toggles of the buffer and the inverter connected to the output of the logic gate is the same, it is possible to reduce the number of points for connecting the toggle detection circuit.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a power consumption evaluation method according to an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows an evaluation model which is a power consumption measurement target circuit, that is, a power consumption analysis block (evaluation block), and a waveform thereof in order to evaluate power consumption of an integrated circuit. FIG.
In FIG. 1, reference numeral 10 denotes a D flip-flop, 11 denotes an AND circuit, 12 denotes an OR circuit, 13 denotes an inverter, and 14 denotes a buffer. The input pins are IN1, IN2, IN3, and CK. Output pin is OUT.

FIG. 3 shows a toggle detection circuit 106, that is, a toggle frequency calculation circuit. Reference numerals 101 and 102 denote 1-bit registers.
-1, t-2 signal is held. 103 is “0 →” at time t.
A detector (exclusive OR) that outputs "1" only for changes of "1" and "1 → 0" 104. An adder 104 is a detector 1
Add the signal obtained in 03. Reference numeral 105 denotes a several-bit shift register that holds the number of toggles. Shift register
105 has an input / output that can be connected in a chain to the shift register 105 of another toggle detection circuit in order to output the toggle count result to the outside. The number of bits of the shift register 105 may be set arbitrarily, but if the simulation cycle is N, the number of toggles of each logic gate tends to be statistically 1/4 of the simulation cycle. 2N / 4). Register 10
The initial state of each of 1,102,105 is 0.

When the net list information of the evaluation block shown in FIG. 1 is input to the field programmable array 107 in which the toggle detection circuit 106 shown in FIG. 5 is integrated in advance, the clock line (CK) of the evaluation block, the buffer 14, and the inverter The toggle detection circuit 106 is automatically added only to the outputs of the logic gates (D flip-flop 10, AND circuit 11, and OR circuit 12) excluding 13. As described above, in the case of the clock without control, the toggle detection circuit is not connected to the clock. In the evaluation model of FIG. 1, the toggle detection circuit 106 is attached to the evaluation points D, F, and OUT as shown in FIG.

The above-mentioned field programmable array 1
When 07 is incorporated into a hardware emulator or the like and a simulation is performed, the number of toggles of each logic gate is stored in the register 105 of the toggle detection circuit 106 as shown in FIG. When the simulation is completed, the SMODE of the toggle detection circuit 106 is set to “1”, the shift mode is set, and the entire contents of the register 105 are extracted from the field programmable array 107.

Taking the simulation waveform of FIG. 2 as an example,
Simulation is completed in 10 cycles, D four times, E
Is four times from the result of D, F is six times, and OUT is two times.
The toggle rate is D = E = 0.4, F = 0.6, OUT =
0.2, the operating frequency is FRQ, and PRQ
Assuming that (D), P (E), P (F), and P (OUT) are the power consumption of D, E, F, and OUT, respectively, P (D) = FRQ × 0.2 × (P0 (D) + ΔPs (D) × Δs (D) + CL (D) × ΔPCL (D)) (1) P (E) = FRQ × 0.2 × (P0 (E) + ΔPs (E) × Δs (E) + CL (E ) × ΔPCL (E)) (2) P (F) = FRQ × 0.3 × (P0 (F) + ΔPs (F) × Δs (F) + CL (F) × ΔPCL (F)) (3) P (OUT) = FRQ × 0.1 × (P0 (OUT) + ΔPs (OUT) × Δs (OUT) + CL (OUT) × ΔPCL (OUT)) ... separately calculated (4), 4 from the last to the formula The power consumption is detected by summing the two.

Here, P0, ΔPs, Δs, CL, ΔP
Subscripts in parentheses of CL are power consumption parameters of D, E, F, and OUT output cells, respectively.

As described above, the toggle detection circuit 10 shown in FIG.
6 and the power consumption measurement circuit shown in FIG. 1 are realized in a field programmable array, a simulation test vector (simulation pattern) is input, and the result of the register 105 is referred to after the simulation.
Since the number of toggles is known, the toggle rate is separately calculated for each gate output, and the power consumption is determined.

In the first embodiment, the toggle detection circuit 1
Since a dedicated field programmable array pre-integrated 06 is used, a toggle circuit can be directly connected to the output of each gate of the power consumption evaluation circuit, and an integrated circuit with a power consumption evaluation function can be optimally implemented in a field programmable array at high speed. It is possible to analyze power consumption.

(Second Embodiment) A second embodiment of the present invention will be described. A clock line (CK), a buffer 14, and an inverter 13 are shown in a text representation of the toggle detection circuit 106 as shown in FIG. 4 and a text representation of the power consumption evaluation target circuit in FIG.
Toggle detection circuit only for the output of logic gate (D flip-flop 10, AND circuit 11, OR circuit 12) except for
Edit and connect 106. FIG. 6 shows this state. As shown in FIG. 6, a toggle detection circuit TOGCHECK is added to the original evaluation target circuit HYOUKA.
K is automatically inserted using a text conversion program and converted into HYOUKA-pow.

The converted HYOUKA-pow and TOGCHECK are input to the general-purpose field programmable array 107.

When the general-purpose field programmable array 107 is incorporated in a hardware emulator or the like and simulated, the number of toggles of each logic gate is stored in the shift register 105. When the simulation is completed, the shift register 105 is set to the shift mode, and all the contents of the register are referred to. Calculation of toggle rate,
The method of calculating the power consumption is the same as in the first embodiment described above.

According to the second embodiment, since a circuit for power consumption evaluation analysis is realized using a general-purpose field programmable array, the analysis speed is slightly inferior to that of the first embodiment. It is much faster than the power consumption evaluation method using a software simulator, and the analysis cost can be reduced.

In the present invention, the logic gate of the power consumption measurement target circuit includes a latch or a memory including an AND gate or an OR gate in the circuit, if any.

[0035]

According to the power consumption evaluation method of the first aspect, the simulation time for calculating the number of toggles of each logic gate output of the power consumption measurement target circuit is significantly longer than that of the conventional power consumption evaluation method using the software emulator. Can be shortened, and therefore can be significantly faster,
Early evaluation of power consumption becomes possible.

According to the power consumption evaluation apparatus of the second aspect, in order to model not only functions of an integrated circuit but also functions capable of measuring power consumption using a real device called a field programmable array, a conventional software Since the signal propagation time is shorter than the functional model of the integrated circuit and the power consumption measurement by the simulator, the time required for the simulation can be greatly reduced.

According to the power consumption evaluation method of the third aspect, a toggle circuit is added to the output of each logic gate in the text file describing the power consumption measurement target circuit by a text conversion process using a document conversion program. Since a text file of the added circuit is input to a general-purpose field programmable array, a simple text conversion program and a general-purpose field programmable array can be used to build an integrated circuit function and power consumption measurement function model. Thus, power consumption can be evaluated at low cost.

According to the power consumption evaluation method of the fourth aspect, the function of the circuit to be measured and the power consumption measurement function are realized in a dedicated field programmable array in which a large number of toggle circuits and general-purpose logic gates are integrated in advance. The logic that implements the function of the integrated circuit itself and the logic that implements the power consumption measurement function are completely separated from each other, making it possible to implement an integrated circuit model capable of measuring power consumption in a field programmable array. It takes less time to do it.

According to the power consumption evaluation method of the fifth aspect, in addition to the same effects as those of the third and fourth aspects, the clock without control has the number of toggles corresponding to the operating frequency, so that it can be easily calculated. Therefore, it is possible to reduce the number of points at which the toggle detection circuit is connected, compared to a case where this method is not used.

According to the power consumption evaluation method of the sixth aspect, in addition to the same effects as the fifth aspect, a logic gate having two or more inputs in the power consumption analysis target circuit other than the connection of the clock according to the fifth aspect. Since the toggle detection circuit is connected only to the output, flip-flop output, latch output, and memory output, the number of toggles of two or more logic gate outputs, flip-flop outputs, latch outputs, and memory outputs can be measured. Since the number of toggles of the buffer and the inverter connected to the output of the logic gate is the same, it is possible to reduce the number of points for connecting the toggle detection circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a power consumption analysis block according to a first embodiment of the present invention.

FIG. 2 is a waveform chart of each part of FIG.

FIG. 3 is a toggle detection circuit diagram according to the first and second embodiments of the present invention.

FIG. 4 shows first and second embodiments of the present invention.
FIG. 4 is a circuit diagram illustrating the incorporation of a toggle detection circuit in a power consumption analysis block.

FIG. 5 is a diagram showing a dedicated field programmable array in which a toggle detection circuit is integrated in advance according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a text representation of the power consumption evaluation target circuit of FIG. 1 according to the second embodiment of the present invention and a circuit description capable of power consumption evaluation by adding a toggle detection circuit to the target circuit; This is the converted file.

[Explanation of symbols]

 Reference Signs List 10 D flip-flop 11 AND circuit 12 OR circuit 100 Input data at time t 101 Register storing input data at time t-1 102 Register storing input data at time t-2 103 Detector 104 Adder 105 Number of toggles Storage shift register 106 Toggle detection circuit 107 Field programmable array

Claims (6)

[Claims] 1. A power consumption measurement target circuit and a toggle detection circuit for detecting the number of toggles of circuit elements of the power consumption measurement target circuit are configured in a field programmable array, and a simulation pattern is input to the field programmable array. A power consumption evaluation method, wherein the number of toggles detected by the toggle detection circuit after completion of the simulation is obtained as power consumption of a power consumption measurement target circuit. 2. A field programmable array comprising a power consumption measurement target circuit and a toggle detection circuit for detecting the number of toggles of the output of each logic gate of the power consumption measurement target circuit. What is claimed is: 1. A power consumption evaluation device for calculating the number of toggles for measuring power consumption of a power consumption measurement target circuit by simulation, wherein said toggle detection circuit comprises: a first register for holding an output of each logic gate at time t; , A second register for holding the output of each logic gate at time t-1, a detector for detecting a toggle change in the output of the first register and the second register, and accumulating the number of detections of the detector. And a shift register for storing the accumulation result of the adder. Power evaluation device, characterized in that to obtain a number. 3. A toggle detection circuit for detecting the number of toggles of the output of each logic gate of the power consumption measurement target circuit,
After using a document shaping program to connect the output of each logic gate of the text file describing the power consumption measurement target circuit to a text file converted to text so that power consumption can be evaluated, a general-purpose field programmable array A power consumption evaluation method for inputting a simulation pattern to the field programmable array and measuring the number of toggles of the logic gate. 4. Using a toggle detection circuit for detecting the number of toggles of the output of each logic gate of the power consumption measurement target circuit and a dedicated field programmable array composed of various logic gates, each of the power consumption measurement targets is used. A power consumption evaluation method, wherein a toggle detection circuit is automatically connected to an output of a logic gate in the dedicated field programmable array, and then the number of toggles of the logic gate output is measured by the toggle detection circuit. 5. The power consumption evaluation method according to claim 3, wherein a toggle detection circuit is not connected to the clock when there is a clock in the power consumption measurement target circuit and the clock is not controlled. 6. The method according to claim 6, wherein said signal is present in a power consumption measurement target circuit.
Logic gate output more than input, flip-flop output,
6. The power consumption evaluation method according to claim 5, wherein a toggle detection circuit is connected to the latch output or the output of the memory.