CN116151187B

CN116151187B - Method, apparatus and storage medium for processing trigger condition

Info

Publication number: CN116151187B
Application number: CN202310168578.7A
Authority: CN
Inventors: 李鹤; 于真
Original assignee: Core Huazhang Technology Beijing Co ltd
Current assignee: Core Huazhang Technology Beijing Co ltd
Priority date: 2023-02-14
Filing date: 2023-02-14
Publication date: 2024-01-19
Anticipated expiration: 2043-02-14
Also published as: CN116151187A

Abstract

The application provides a method for processing trigger conditions using a hardware simulation tool. The hardware simulation tool includes a programmable logic device having a plurality of computing units formed thereon in a particular configuration, the method comprising: generating a first operation and a second operation according to the triggering condition; decomposing the first operation and the second operation into a first plurality of first instructions and a second plurality of second instructions, respectively, the plurality of first instructions and the plurality of second instructions corresponding to the plurality of computing units, respectively; determining execution timings of the plurality of first instructions and the plurality of second instructions on the plurality of computing units according to the specific structure; and executing the first plurality of instructions and the second plurality of instructions according to the execution timing.

Description

Method, apparatus and storage medium for processing trigger condition

Technical Field

The present disclosure relates to the field of chip verification technologies, and in particular, to a method, an apparatus, and a storage medium for processing trigger conditions using a hardware simulation tool.

Background

A hardware simulation tool (e.g., a prototype verification board or hardware simulation tool (simulator)) may prototype (prototype) and debug a logic system design that includes one or more modules. The logic System design may be, for example, a design for an integrated circuit (Application Specific Integrated Circuit, ASIC for short) or a System-On-Chip (SOC) for special applications. Thus, the logic system design under test in the simulation tool may also be referred to as a design under test (Design Under Test, DUT for short). The simulation tool may simulate the design under test by one or more configurable components, such as a field programmable gate array (Field Programmable Gate Array, FPGA for short), including performing various operations on the design under test to test and verify the functionality of the various modules of the design under test prior to fabrication. The design to be tested and various peripherals can be tested to be used as a complete system to run by externally connecting various peripheral daughter cards on the simulation tool.

In the verification of logic system designs using hardware simulation tools, trigger conditions may typically be set as waveform grabbing or event triggering. When the trigger condition is set, the condition needs to be calculated and judged. Since verification using hardware simulation tools requires compiling the RTL code of the logic system design into a netlist. To facilitate simulation debugging, it is necessary to calculate and determine quickly whether the trigger condition is satisfied.

Disclosure of Invention

A first aspect of the present application provides a method of processing a trigger condition using a hardware emulation tool. The hardware simulation tool includes a programmable logic device having a plurality of computing units formed thereon in a particular configuration, the method comprising: generating a first operation and a second operation according to the triggering condition; decomposing the first operation and the second operation into a first plurality of first instructions and a second plurality of second instructions, respectively, the plurality of first instructions and the plurality of second instructions corresponding to the plurality of computing units, respectively; determining execution timings of the plurality of first instructions and the plurality of second instructions on the plurality of computing units according to the specific structure; and executing the first plurality of instructions and the second plurality of instructions according to the execution timing.

A second aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of the first aspect.

A third aspect of the present application provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first aspect.

Drawings

In order to more clearly illustrate the technical solutions of the present application or related art, the drawings that are required to be used in the description of the embodiments or related art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 shows a schematic structural diagram of a host according to an embodiment of the present application.

FIG. 2 shows a schematic diagram of a simulation system according to an embodiment of the present application.

Fig. 3 shows a schematic diagram of a trigger condition processor according to an embodiment of the present application.

FIG. 4 illustrates a schematic diagram of a plurality of operations and execution timing of a plurality of instructions corresponding to the plurality of operations.

FIG. 5 illustrates a flow chart of a method of processing trigger conditions using a hardware simulation tool.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings.

It is to be noted that unless otherwise defined, technical or scientific terms used herein should be taken in a general sense as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items. The term "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

As described above, in order to calculate and determine whether the trigger condition is satisfied, it is common practice to form a small CPU in the FPGA of the hardware simulation tool and perform calculation using the CPU. This is typically done by determining the operands based on the calculation instructions of the trigger conditions, sequentially reading the data serially and then caching, and then performing the calculations based on the calculation instructions sequence using arithmetic units in the CPU.

However, this is relatively slow due to the serial acquisition of data and sequential computation, which tends to slow the overall verification rate.

In order to accelerate the processing of the trigger condition, the embodiments of the present application propose the following method, apparatus and storage medium.

Fig. 1 shows a schematic structural diagram of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running an emulation system. As shown in fig. 1, the host 100 may include: processor 102, memory 104, network interface 106, peripheral interface 108, and bus 110. Wherein the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively coupled to each other within the electronic device via a bus 110.

The processor 102 may be a central processing unit (Central Processing Unit, CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits. The processor 102 may be used to perform functions related to the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated as a single logical component. As shown in fig. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system used to simulate the test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., program instructions for implementing the methods of locating errors of the present application) as well as data to be processed (e.g., the memory may store temporary code generated during compilation). The processor 102 may also access program instructions and data stored in the memory and execute the program instructions to perform operations on the data to be processed. The memory 104 may include volatile storage or nonvolatile storage. In some embodiments, memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSD), flash memory, memory sticks, and the like.

The network interface 106 may be configured to provide communication with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the foregoing. It will be appreciated that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, receivers, modems, routers, gateways, adapters, cellular network chips, etc.

The peripheral interface 108 may be configured to connect the host 100 with one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as keyboards, mice, touchpads, touch screens, microphones, various types of sensors, and output devices such as displays, speakers, vibrators, and indicators.

Bus 110 may be configured to transfer information between the various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), etc.

It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the electronic device architecture may also include other components necessary to achieve proper operation. Furthermore, those skilled in the art will appreciate that the electronic device architecture described above may also include only the components necessary to implement the embodiments of the present application, and not all of the components shown in the figures.

FIG. 2 shows a schematic diagram of a simulation system 200 according to an embodiment of the present application.

As shown in FIG. 2, the simulation system 200 may include a simulation tool 202 and a host 100 coupled to the simulation tool 202.

Simulation tool 202 is a hardware system for simulating a Design Under Test (DUT). The simulation tool 202 may be a prototype verification board or a hardware simulator (simulator). One design under test may include multiple modules. The design under test may be combinational logic, sequential logic, or a combination of the two. The simulation tool 202 may include one or more configurable circuits (e.g., FPGAs) for simulating a design under test.

The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 for communication between the host 100 and the simulation tool 202. In some embodiments, interface unit 2022 may include one or more interfaces with electrical connection capabilities. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN interface, an optical fiber interface, IEEE1394 (firewire interface), and the like. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a WIFI interface, a bluetooth interface, or the like.

The host 100 may transmit compiled DUTs, debug instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data or the like to the host 100 via the interface unit 2022.

The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values generated by the design under test during the simulation process may be directly read by the host 100. It will be appreciated that the memory 2024 may also be provided by the stand-alone simulation tool 202, for example, using an external memory.

The simulation tool 202 may also include an FPGA 2026 for hardware implementation of the logic system design onto the FPGA. It is understood that the simulation tool 202 may include a plurality of FPGAs, which are only examples.

In addition to being connected to the host 100, the emulation tool 202 can also be connected to one or more daughter cards 204 via an interface unit 2022.

The daughter card is used to provide peripherals to the DUT to build a complete electronic system when prototype verification is performed using simulation tool 202. Prototype verification refers to a verification mode for restoring the actual use scene of a chip as far as possible before chip streaming, and verifying whether the chip functions are accurate and complete. The daughter cards 204 may include memory daughter cards (e.g., providing DDR memory interfaces), communication daughter cards (e.g., providing various network interfaces or wireless network card interfaces), and the like.

The host 100 may be used to configure the simulation tool 202 to simulate a design under test. The design under test may be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, host 100 may be a virtual host in a cloud computing system. The logic System design (e.g., ASIC or System-On-Chip) may be designed by a hardware description language (e.g., verilog, VHDL, system C, or System Verilog).

The host 100 may receive a request from a user to debug a design under test. As described above, the design under test may include one or more modules. Description of the design under test may be accomplished in a hardware description language. The host 100 may synthesize based on the description of the design under test to generate, for example, a gate level netlist (not shown) of the design under test. The gate level circuit netlist of the design under test may be loaded into simulation tool 202 for execution, which may in turn form a circuit structure (e.g., a number of computational cells) corresponding to the design under test in simulation tool 202. Accordingly, the circuit structure of the design under test can be obtained from this description, and accordingly, the circuit structure of each block in the design under test can also be obtained similarly.

The trigger condition of the logic system design in the verification process may be "a > b & & a > c ≡a+b >3 ≡a ≡ 2>5 ≡b+1<3". A, b, c, etc. in the trigger condition are all signals of the logic system design. For different values of the signals a, b, c during the operation of the logic system design, the host connected to the hardware simulation tool needs to determine whether the above conditions are triggered, so it needs to quickly calculate whether "a > b & & a > c ≡a+b >3 ≡a ≡ 2>5 ≡b+1<3" is satisfied.

Unlike a traditional CPU solving trigger condition, the trigger condition processor is in the form of an FPGA and has a plurality of computing units with specific structures. The trigger condition may be converted by the host into an operation corresponding to a plurality of computing units of the particular architecture and executed quickly.

Fig. 3 shows a schematic diagram of a trigger condition processor 300 according to an embodiment of the present application.

The trigger condition processor 300 may be part of a configurable component (e.g., FPGA) on a hardware simulation tool.

A host coupled to the hardware simulation tool may receive the trigger condition 302 and read a signal value associated with the trigger condition 304 from a configurable component running the logic system design (hereinafter referred to as the logic system design). Depending on whether the trigger condition is met, the host may decide whether a certain authentication operation is to be performed. Whether the trigger condition is satisfied will be calculated by the trigger condition processor 300.

The trigger condition processor 300 includes a decoder 312 and a plurality of computing units 314-324 of a particular architecture. The specific structure may be a structure as shown in fig. 3, i.e., one multiplexer 314 is connected to two parallel shift units 316 and 318, the outputs of which are connected to an arithmetic logic unit 320 and then to an arithmetic logic unit 322, and finally output or skip to the next processing unit via a communication and skip unit 324. It will be appreciated that the particular structure may vary depending on the particular application and is not limited to the example of fig. 3. Thus, a particular architecture of the plurality of computing units 314-324 is configurable.

A host (e.g., host 100) coupled to the hardware simulation tool may generate a plurality of operations, each operation in turn comprising a plurality of operations, based on the trigger conditions 302 and the particular structure. For example, "a > b & & a > c & & a+b >3 & & a × 2>5 & b+1<3" may include a first operation of calculating whether "a > b" is true, a second operation of calculating whether "a > c" is true, a third operation of calculating whether "a+b >3" is true, a fourth operation of calculating whether "a x 2>5" is true, a fifth operation of calculating whether "b+1<3" is true, and a sixth operation of calculating the sum of the results of the above operations.

These first through sixth operations may be sent as operation instructions from the host computer to the hardware simulation tool.

In some embodiments, when the specific structures of the plurality of computing units are different, a plurality of operations different from the above-described examples may be generated. For example, when a plurality of arithmetic logic units capable of calculating and operating are included in the plurality of calculation units, after the results of the first operation to the fourth operation are obtained, the sum operation of the results of the first operation and the second operation and the sum operation of the results of the third operation and the fourth operation may be calculated in advance, and then the results of the two sum operations and the result of the fifth operation may be further subjected to the sum operation.

Each operation, in turn, may be decoded by decoder 312 to comprise a plurality of instructions corresponding to a plurality of computing units 314-324. For example, an operation may be decomposed into one or more of a selection instruction for selecting one or more specific signals from a plurality of signals, a shift instruction for shifting a signal value, an arithmetic instruction for arithmetically processing a shifted signal value, or a communication instruction for communicating or jumping a processing result. For example, the first operation may include a select instruction, a shift instruction, and an arithmetic instruction; the sixth operation may include an arithmetic instruction and a communication instruction.

The host may determine the timing of execution of the plurality of instructions on the plurality of computing units 314-324 according to the particular architecture described above.

FIG. 4 illustrates a schematic diagram of a plurality of operations and execution timing 400 of a plurality of instructions corresponding to the plurality of operations.

As shown in FIG. 4, depending on the trigger condition, the host may generate 6 operations (op 1-op 6). Operation op1 is further broken down into 4 instructions, including sel1, S11, S12, and alu1. Similarly, operation op2 is further broken down into 4 instructions, including sel2, S21, S22, and alu2. These instructions may be distributed by decoder 312 of fig. 3 to corresponding computing units for execution at a given timing.

For example, according to the particular architecture of FIG. 3, sel1 may be performed using multiplexer 314 in a first cycle; sel2 is performed using the multiplexer 314, S11 is performed using the shift unit 316, and S21 is performed using the other shift unit 318 in the second cycle; performing S12 using a shift unit 316, S22 using another shift unit 318, and performing a portion of alu1 using an arithmetic logic unit 320 in a third cycle; in the fourth cycle, a part of alu2 is executed using arithmetic logic unit 320, and another part of alu1 is executed using arithmetic logic unit 322.

It follows that in the second, third and fourth cycles, a portion of the instructions of operation op1 and operation op2 are executed in parallel, thereby accelerating the execution of operation op1 and operation op 2.

The operations op3-op5 are similarly broken down into multiple instructions and enable parallelized execution.

As shown in FIG. 4, operation op6 may include 2 instructions, alu6 and com, for calculating and sending out the results produced by operations op1-op5, respectively.

In some embodiments, the host may read trigger conditions associated with the logic system design and determine the plurality of computing units and their specific structures based on the trigger conditions. In this way, a small number of computational units may be used for a logic system design with simple trigger conditions, while a more computational units and a more complex specific structure may be used for a logic system design with complex trigger conditions, enabling dynamic configuration.

Thus, the present application enables the determination of trigger conditions to be broken down into instructions by implementing multiple computational units with specific structures on a configurable component (FPGA). The instructions can be executed in parallel on the plurality of computing units with the specific structure, so that the calculation of the trigger condition is accelerated. Compared with the common practice, on one hand, the structure of a plurality of computing units with specific structures is simpler than that of a small CPU, and the limited resources of the FPGA can be saved; on the other hand, parallel execution of the trigger condition can accelerate computation as compared with serial execution of the CPU. In addition, a plurality of computing units with specific structures can realize dynamic configuration of the computing units, so that flexibility is improved.

FIG. 5 illustrates a flow chart of a method 500 of processing trigger conditions using a hardware simulation tool. Method 500 may be performed by, for example, host 100 of fig. 1. The host 100 has software running thereon that corresponds to the hardware simulation tool. The hardware simulation tool (e.g., hardware simulation tool 202 of FIG. 2) may include a programmable logic device (e.g., FPGA 2026) on which a plurality of computing units (e.g., computing units 314-324 of FIG. 3) of a particular architecture are formed. In some embodiments, the plurality of computing units of the particular structure may include: the multi-channel selector comprises a selector, a first shifting unit and a second shifting unit which are connected with the multi-channel selector, a first arithmetic logic unit and a second arithmetic logic unit which are connected with the first shifting unit and the second shifting unit, and a communication and jump unit which is connected with the first arithmetic logic unit and the second arithmetic logic unit.

The method 500 may include the following steps.

At step 502, the host 100 may generate a first operation (e.g., op1 of FIG. 4) and a second operation (e.g., op2 of FIG. 4) according to the trigger condition. In some embodiments, the host 100 may generate the first and second operations according to the trigger condition and the specific structure. That is, the specific structure itself may also affect the generation of the first operation and the second operation.

At step 504, the host 100 may decompose the first and second operations into a first plurality of first instructions (e.g., sel1, S11, S12, alu1, etc. of fig. 4) and a second plurality of second instructions (e.g., sel2, S21, S22, alu2, etc. of fig. 4), respectively, corresponding to the plurality of computing units. The first plurality of first instructions may include: a first select instruction, a first one-to-shift instruction, a first two-to-shift instruction, a first one-to-arithmetic instruction, a first two-to-arithmetic instruction, the second plurality of second instructions comprising: the second selection instruction, the second first shift instruction, the second first arithmetic instruction, the second arithmetic instruction.

At step 506, the host 100 may determine execution timing (e.g., timing 400 of fig. 4) of the plurality of first instructions and the plurality of second instructions on the plurality of computing units according to the particular structure. In some embodiments, the execution timing may include: executing the first select instruction at the selector during a first clock cycle; in a second clock cycle, the second selection instruction is executed at the selector, and the first one-shift instruction and the first two-shift instruction are executed at the first shift unit and the second shift unit.

At step 508, the host 100 may execute the first plurality of instructions and the second plurality of instructions according to the execution timing.

In some embodiments, the method 500 may further comprise: the plurality of computing units and the specific structure are determined according to the trigger condition. In this way, a small number of computational units may be used for a logic system design with simple trigger conditions, while a more computational units and a more complex specific structure may be used for a logic system design with complex trigger conditions, enabling dynamic configuration.

The embodiment of the application also provides an electronic device. The electronic device may be the host 100 of fig. 1. The host 100 may include a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method 500.

Embodiments of the present application also provide a non-transitory computer readable storage medium. The non-transitory computer readable storage medium stores a set of instructions of a computer that, when executed, are to cause the electronic control device to perform the method 500.

Embodiments of the present application also provide a simulation system (e.g., simulation system 200 of fig. 2) including a hardware simulation tool and the above-described electronic device coupled to the hardware simulation tool.

Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Those of ordinary skill in the art will appreciate that: the discussion of any of the embodiments above is merely exemplary and is not intended to suggest that the scope of the application (including the claims) is limited to these examples; the technical features of the above embodiments or in different embodiments may also be combined under the idea of the present application, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in details for the sake of brevity.

While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of those embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

This application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalents, improvements and the like, which are within the spirit and principles of the application, are intended to be included within the scope of the present application.

Claims

1. A method of processing trigger conditions of a logic system design using a hardware simulation tool, the hardware simulation tool comprising a programmable logic device having a plurality of computing units formed thereon in a particular configuration, the method comprising:

generating a first operation and a second operation according to the triggering condition;

decomposing the first operation and the second operation into a first plurality of first instructions and a second plurality of second instructions, respectively, the plurality of first instructions and the plurality of second instructions corresponding to the plurality of computing units, respectively;

determining execution timings of the plurality of first instructions and the plurality of second instructions on the plurality of computing units according to the specific structure; and

executing the first plurality of instructions and the second plurality of instructions according to the execution timing, wherein,

the method further comprises: the plurality of computing units and the specific structure are determined according to the trigger condition.

2. The method of claim 1, wherein the plurality of computing units of the particular structure comprise: the multi-channel selector comprises a selector, a first shifting unit and a second shifting unit which are connected with multi-channel selection, a first arithmetic logic unit and a second arithmetic logic unit which are connected with the first shifting unit and the second shifting unit, and a communication and jump unit which is connected with the first arithmetic logic unit and the second arithmetic logic unit.

3. The method of claim 2, wherein the first plurality of first instructions comprises: a first select instruction, a first one-to-shift instruction, a first two-to-shift instruction, a first one-to-arithmetic instruction, a first two-to-arithmetic instruction, the second plurality of second instructions comprising: the second selection instruction, the second first shift instruction, the second first arithmetic instruction, the second arithmetic instruction.

4. The method of claim 3, wherein the execution timing comprises:

executing the first select instruction at the selector during a first clock cycle;

in a second clock cycle, the second selection instruction is executed at the selector, and the first one-shift instruction and the first two-shift instruction are executed at the first shift unit and the second shift unit.

5. The method of claim 1, wherein generating the first operation and the second operation according to the trigger condition further comprises:

and generating the first operation and the second operation according to the triggering condition and the specific structure.

6. An electronic device, comprising:

a memory for storing a set of instructions; and

at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any one of claims 1-5.

7. A non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of any of claims 1-5.

8. A simulation system comprising a hardware simulation tool and the electronic device of claim 6 coupled to the hardware simulation tool.