CN115906730A - Method, apparatus and storage medium for verifying logic system design - Google Patents
Method, apparatus and storage medium for verifying logic system design Download PDFInfo
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Abstract
The present disclosure provides a method, apparatus, and storage medium for verifying a logic system design. The method comprises the following steps: receiving a description of the logic system design and assertion statements for verifying the logic system design, the assertion statements being associated with a plurality of signals of the logic system design; determining a plurality of assertion states of the assertion statement over a plurality of operating cycles based on values of the plurality of signals over the plurality of operating cycles, respectively, the assertion states including assertion success or assertion failure; determining a transition relationship of the plurality of assertion states according to values of the plurality of signals over a plurality of operating cycles; and generating a graphical assertion state diagram according to the assertion states and the conversion relation.
Description
Technical Field
The present disclosure relates to the field of chip verification technologies, and in particular, to a method for verifying a logic system design, an electronic device, and a storage medium.
Background
In the field of Verification of integrated circuits, formal Verification (Formal Verification) refers to the mathematically complete demonstration or Verification of whether an implementation of a circuit does indeed implement the functionality described by a circuit design. The logic system Design (e.g., circuit Design) being tested and verified may be referred to as a Design Under Test (DUT).
In performing formal authentication, a user needs to input an authentication target (e.g., assertion statement) of the DUT. The verification target may set a target that the DUT needs to achieve in each state to determine whether the DUT satisfies specified attributes. If the DUT is proved to be capable of achieving the target of the assertion requirement through formal verification, the DUT is consistent with the attribute of the design, otherwise, the design is in a problem and needs to be modified. The way to prove can be to prove that the DUT possesses the property, or the counterexample of the existence of the property.
Evaluation and composition of assertion statements is complex. For example, a concurrent assertion (current assertion) describing an attribute owned by a sequential logic circuit makes an evaluation attempt (evaluation attack) on each rising clock edge, but there is uncertainty in timing or evaluation path for each evaluation. With only the verification results given by the formal verification tool (e.g., the counter example, indicating a verification failure), it is difficult for the user to determine from which clock cycle the evaluation that caused the assertion declaration failure started, and at which evaluation path occurred. That is, according to the conventional evaluation of assertion statements, a user can only obtain the evaluation result of the assertion statements, but cannot know the process causing the result.
Disclosure of Invention
A first aspect of the present application provides a method of validating a logic system design, comprising: receiving a description of the logic system design and assertion statements for verifying the logic system design, the assertion statements being associated with a plurality of signals of the logic system design; determining a plurality of assertion states of the assertion statement over a plurality of operating cycles based on values of the plurality of signals over the plurality of operating cycles, respectively, the assertion states including assertion success or assertion failure; determining a transition relationship of the plurality of assertion states according to values of the plurality of signals over a plurality of operating cycles; and generating a graphical assertion state diagram according to the assertion states and the conversion relation.
A second aspect of the present application provides an electronic device. The electronic device includes a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform the method according to the first aspect.
A third aspect of the application provides a non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of the first aspect.
According to the method, the equipment and the storage medium for verifying the logic system design, provided by the disclosure, through generating the graphical assertion state diagram, a user can intuitively see the jump path of the assertion state in the evaluation process of the assertion statement, so that the path of the assertion statement in the evaluation process is determined, and a state chain reaching the assertion state is intuitively obtained while the assertion state is obtained. Through the waveform diagram corresponding to the assertion state, the form verification tool can visually display the change condition of the signals related to the logic system design in the assertion and the assertion state in each period. The method provided by the disclosure is helpful for helping a user to analyze the reason of the evaluation result causing the assertion statement and quickly modify the design problem.
Drawings
In order to more clearly illustrate the technical solutions in the present application or the related art, the drawings needed to be used in the description of the embodiments or the related art will be briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 shows a schematic structural diagram of an exemplary host according to an embodiment of the present disclosure.
FIG. 2 shows a schematic diagram of an exemplary formal verification tool in accordance with an embodiment of the present disclosure.
FIG. 3A illustrates a schematic diagram of an exemplary assertion state diagram in accordance with an embodiment of the present disclosure.
Fig. 3B illustrates a schematic diagram of an exemplary waveform diagram corresponding to a state chain in accordance with an embodiment of the disclosure.
FIG. 4 illustrates a flow chart of a method of verifying a logic system design according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to specific embodiments and the accompanying drawings.
It is to be noted that, unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" and similar words are intended to mean that the elements or items listed before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "coupled" and similar terms are not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Fig. 1 shows a schematic structural diagram of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running an emulation system. As shown in fig. 1, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Wherein processor 102, memory 104, network interface 106, and peripheral interface 108 are communicatively coupled to each other within the host via bus 110.
Processor 102 may be a Central Processing Unit (CPU), an image processor, a neural Network Processor (NPU), a Microcontroller (MCU), a programmable logic device, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits. The processor 102 may be used to perform functions associated with the techniques described herein. In some embodiments, processor 102 may also include multiple processors integrated into a single logic component. As shown in FIG. 1, the processor 102 may include a plurality of processors 102a, 102b, and 102c.
The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). In some embodiments, the simulation test system for simulating a test design may be a computer program stored in memory 104. As shown in fig. 1, the data stored by the memory may include program instructions (e.g., for implementing the methods of validating a logic system design of the present application) as well as data to be processed (e.g., the memory may store temporary code generated during the compilation process). The processor 102 may also access memory-stored program instructions and data and execute the program instructions to operate on the data to be processed. The memory 104 may include volatile memory devices or non-volatile memory devices. In some embodiments, the memory 104 may include Random Access Memory (RAM), read Only Memory (ROM), optical disks, magnetic disks, hard disks, solid State Disks (SSDs), flash memory, memory sticks, and the like.
The network interface 106 may be configured to provide communications with other external devices to the host 100 via a network. The network may be any wired or wireless network capable of transmitting and receiving data. For example, the network may be a wired network, a local wireless network (e.g., bluetooth, wiFi, near Field Communication (NFC), etc.), a cellular network, the internet, or a combination of the above. It is to be understood that the type of network is not limited to the specific examples described above. In some embodiments, network interface 106 may include any combination of any number of Network Interface Controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, and the like.
Bus 110 may be configured to transfer information between various components of host 100 (e.g., processor 102, memory 104, network interface 106, and peripheral interface 108), such as an internal bus (e.g., processor-memory bus), an external bus (USB port, PCI-E bus), and so forth.
It should be noted that although the host architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in a specific implementation, the host architecture may also include other components necessary to achieve normal operation. Furthermore, those skilled in the art will appreciate that the above-described host architecture may also include only the components necessary to implement the embodiments of the present application, and need not include all of the components shown in the figures.
FIG. 2 shows a schematic diagram of an exemplary formal verification tool 200 in accordance with an embodiment of the present disclosure. In the field of chip design, the format verification tool 200 may be a GalaxFV format verification tool produced by seocho technologies, inc. The formal verification tool 200 may be a computer program running on the electronic device 100. In some embodiments, formal verification tool 200 may include components such as a simulator.
In some embodiments, system design 202 may be an RTL design. In integrated circuit design, RTL is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, a chip is composed of a set of registers and logical operations between the registers. This is so because most circuits can be viewed as storing binary data by registers, and processing data by logical operations between registers, and the flow of data processing is controlled by a sequential state machine, and these processes and controls can be described by a hardware description language.
As shown in FIG. 2, system design 202 and assertion declaration 204 ultimately output verification result 206 after processing via verification tool 200. The verification result 206 may be an assertion success or an assertion failure. In some embodiments, the verification result 206 may also be inconclusive.
As described above, the assertion declarations 204 may include a coverage property (cover property) that describes a Design Under Test (DUT). For example, assertion declaration 204 may be:
c1:cover property(@(posedge clk)(req[0]##1gnt[0])or(req[1]##1gnt[1])
the assertion 204 relates to the req signal and the gnt signal as described by the logic system. Assertion statement 204 describes that system design 202 should cover the following cases: when req [0] is true, gnt [0] is also true after one cycle; or when req [1] is true and gnt [1] is also true after one cycle, the assertion is successful, otherwise the assertion fails.
As with the assertion statements described above in c1, assertion statements 204 may include multiple states and transitions between the multiple states. In current formal verification tools, the states involved in and transitions between states for an assertion declaration 204 are dependent only on user understanding through code. Meanwhile, assertion statement 204 can only feed back transitions related to the failure state. For example, for c1 above, current formal verification tools typically only give values for the req signal and the gnt signal for 2 cycles. That is, the form verification tool may give req [0] (1) =0 and req [1] (1) =0 or req [0] (1) =1 and gnt [0] (2) =0, where req [0] (1) and req [1] (1) represent values of req [0] and req [1] at the first cycle, respectively, and gnt [0] (2) represents a value of gnt [0] at the second cycle. However, in the actual verification work, the signal causing the fail state may be derived from an earlier signal, that is, a cause caused by an earlier signal transition (for example, a cause of causing a transition of req [0] (0) =1 to req [0] (1) = 0).
In summary, the prior art fails to visually present the connotation of assertion statements 204, nor process information to the user of how system design 202 has been run to a failed state.
Fig. 3A illustrates a schematic diagram of an exemplary assertion state diagram 300 in accordance with an embodiment of the present disclosure.
As shown in FIG. 3A, the state where assertion statement 204 begins is initial state 301. The signals req [0] and req [1] may have 4 states (00,11,10,01). When req [0] =0, req [1] =0, the evaluation condition of the assertion statement 204 is not satisfied, so the assertion statement 204 does not evaluate, and jumps directly to the failed result state 305. When req [0] =1, req 2 [1] =1, assertion statement 204 makes an evaluation attempt at the beginning of a clock rising edge, at which time assertion statement 204 is in state 302; the assertion statement 204 will jump from the state 302 to the failed result state 305 only if the next period gnt [0] =0& & gnt [1] =0, otherwise it will jump from the state 302 to the successful result state 306. When req [0] =1, req 2 [1] =0, the assertion statement 204 makes an evaluation attempt at a clock rising edge, at which time the assertion statement 204 is in state 303; the next cycle gnt [0] =1, the assertion condition is satisfied, the assertion statement 204 jumps from the state 303 to the successful result state 306, and the next cycle gnt [0] =0, the assertion condition is not satisfied, the assertion statement 204 jumps from the state 303 to the failed result state 305. When req [0] =0, req 2 1] =1, the assertion statement 204 makes an evaluation attempt at a clock rising edge, at which time the assertion statement 204 is in state 304; the next cycle gnt [1] =1, the assertion condition is satisfied, the assertion statement 204 jumps from the state 304 to the successful result state 306, and the next cycle gnt [1] =0, the assertion condition is not satisfied, the assertion statement 204 jumps from the state 304 to the failed result state 305.
Thus, the assertion states of assertion statements 204 and the transition relationships between these assertion states are shown in assertion state diagram 300.
In some embodiments, the formal verification tool 200 may receive a user issued instruction to select a failed assertion state in the assertion state diagram 300. Based on the instruction, formal verification tool 200 may highlight a state chain of failed assertion states in assertion state diagram 300. As shown in FIG. 3A, with the state chain shown in bold, assertion statement 204 transitions from initial state 301 to state 303, and then to result state 305. It is to be understood that fig. 3A is merely an exemplary state chain highlighting a failed predicate state, and formal verification tool 200 may display more state chains of predicate states, including a failed predicate state or a successful predicate state, according to user instructions. The bold display shown in fig. 3A is also only one form of highlighting, and the form verification tool 200 may also highlight in other ways (e.g., displaying the jumped connection lines in other colors), which the present disclosure is not limited to.
In some embodiments, a chain of states shown in assertion state diagram 300 can be one evaluation attempt of assertion statements 204.
In some embodiments, formal verification tool 200 may receive an instruction from a user to select a target state and highlight the state chain from the initial state 301 to the target state.
In some embodiments, the highlighted state chain may include multiple states, while the highlighted state chain in state diagram 300 includes only some of the multiple states, with the remaining states not shown being displayed with icons omitted. For example, ellipses may be used as icons for omission to represent the remaining states that are not displayed. The formal verification tool 200 may receive an instruction from the user to further click on the elision icon in the state diagram 300 to expand the remaining states not shown. In some embodiments, clicking on the omit icon may allow the user to further define which portion of the remaining state not displayed by the expansion display.
Fig. 3B illustrates a schematic diagram of an exemplary waveform diagram 310 corresponding to a state chain in accordance with an embodiment of the disclosure.
For the highlighted state chain of failed assertion states shown in fig. 3A, formal verification tool 200 may generate and display a waveform diagram 310 corresponding to this state chain. As seen in waveform diagram 310, formal verification tool 200 generates an evaluation attempt of coverage properties: req [1:0]:00,01, gnt 1: 00,11,10, the evaluation of assertion statement 204 starts from the second cycle, and assertion statement 204 passes through the evaluation path of initial state 301- > state 303- > result state 305. It should be noted that, although only the waveform diagram of 3 operation cycles is shown in fig. 3B, in an actual operation process, the waveform diagram may be the waveform diagram of the entire verification process including more operation cycles. For example, after this evaluation attempt results in a failed result state 305, formal verification tool 200 may continue with the next evaluation attempt and the waveform diagram may continue to display the waveforms of signals req and gnt for the next fourth, fifth, or even more cycles.
It is to be appreciated that formal verification tool 200 may also display a waveform diagram for any of the assertion states in assertion state diagram 300. The waveform diagram showing specifically what kind of assertion state is determined by actual requirements. In some embodiments, the actual requirement to display the waveform map of the predicate state may be an instruction issued by the user to select a target predicate state from which the formal verification tool 200 displays the waveform map corresponding to the predicate state.
In this way, by generating a graphical assertion state diagram, formal verification tool 200 can not only display to the user the transition process of an assertion statement, but can also visually display a chain of states that reach an assertion state. Through the waveform diagram corresponding to the assertion state, the formal verification tool 200 can visually display the change of the signal associated with the logic system design and the assertion state in the assertion in each period. The method provided by the disclosure can help a user to analyze the reason causing the assertion result and quickly modify the design problem.
The embodiment of the application provides a method for verifying logic system design.
FIG. 4 illustrates a flow diagram of a method 400 of verifying a logic system design according to an embodiment of the present application. Method 400 may be performed by host 100 of fig. 1, and more specifically, by formal verification tool 200 running on host 100. The method 400 may include the following steps.
At step 402, formal verification tool 200 may receive a description of the logic system design (e.g., system design 202 of FIG. 2) and an assertion statement (e.g., assertion statement 204 of FIG. 2) for verifying the logic system design, the assertion statement being associated with a plurality of signals (e.g., signals req and gnt) of the logic system design. The assertion declaration may include assert, or cover.
At step 404, formal verification tool 200 may determine a plurality of assertion states (e.g., initial states, intermediate states, and result states) of the assertion statement over a plurality of run cycles, respectively, based on values of the plurality of signals over the plurality of run cycles, the assertion states including assertion success or assertion failure.
At step 406, formal verification tool 200 may determine the transition relationships of the plurality of assertion states based on the values (e.g., 0 or 1) of the plurality of signals over a plurality of cycles of operation.
At step 408, formal verification tool 200 may generate a graphical assertion state diagram (e.g., assertion state diagram 300 of FIG. 3A) based on the plurality of assertion states and the transformation relationships. In some embodiments, the assertion state diagram may show the transition of the assertion from an initial state (e.g., initial state 301 of FIG. 3A) to an intermediate state (e.g., states 302, 303, 304 of FIG. 3A) to a result state (e.g., result states 305, 306 of FIG. 3A). The asserted state diagram may also show the values (e.g., 0 or 1) of the plurality of signals (e.g., signals req and gnt) over a plurality of operating cycles. The formal verification tool 200 may also generate and display a waveform diagram.
In some embodiments, the assertion state diagram can include an initial assertion state (e.g., initial state 301 of fig. 3A) and a failed assertion state (e.g., failed result state 305 of fig. 3A) in which the assertion failed. Formal verification tool 200 may receive an instruction to select the failed predicate state on the predicate state diagram; highlighting a chain of states (e.g., the bold displayed chain of states of FIG. 3A) from the initial assertion state to the failed assertion state.
In some embodiments, the formal verification tool 200 may display a waveform diagram (e.g., waveform diagram 310 of fig. 3B) corresponding to the state chain. For example, waveform diagram 310 may show the values of signals req and gnt in three cycles of operation in an assertion (e.g., assertion 204), whose assertion evaluation begins with the second cycle, and whose evaluation path may be initial state 301- > state 303- > result state 305.
In some embodiments, formal verification tool 200 may receive an instruction to select a target predicate state (e.g., a failed predicate state) among a plurality of predicate states on the predicate state diagram (e.g., predicate state diagram 300 of fig. 3A); displaying a waveform diagram corresponding to the target assertion state.
In this way, through the graphical chain of assertion states and the waveform diagram, the formal verification tool 200 can not only give the evaluation result of the assertion declaration, but also visually display the evaluation process of the assertion declaration (i.e., the transition relation of the assertion states) and the change of the associated signals in the assertion.
The embodiment of the application also provides the electronic equipment. The electronic device may be the host 100 of fig. 1. The electronic device may include a memory to store a set of instructions; and at least one processor configured to execute the set of instructions to cause the electronic device to perform method 400.
Embodiments of the present application also provide a non-transitory computer-readable storage medium. The non-transitory computer readable storage medium stores a set of instructions for a computer that, when executed, cause the computer to perform the method 400.
Some embodiments of the present application are described above. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the context of the present application, features from the above embodiments or from different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity.
While the present application has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures, such as Dynamic RAM (DRAM), may use the discussed embodiments.
The present application is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the application are intended to be included within the scope of the application.
Claims (7)
1. A method of validating a logic system design, comprising:
receiving a description of the logic system design and assertion statements for verifying the logic system design, the assertion statements being associated with a plurality of signals of the logic system design;
determining a plurality of assertion states of the assertion statement over a plurality of operating cycles based on values of the plurality of signals over the plurality of operating cycles, respectively, the assertion states including assertion success or assertion failure;
determining a transition relationship of the plurality of assertion states according to values of the plurality of signals over a plurality of operating cycles; and
and generating a graphical assertion state diagram according to the assertion states and the conversion relation.
2. The method of claim 1, wherein the assertion state diagram includes an initial assertion state and a failed assertion state in which assertion fails, the method further comprising:
receiving an instruction to select the failed predicate state on the predicate state diagram;
highlighting a chain of states from the initial assertion state to the failed assertion state.
3. The method of claim 1, wherein the method further comprises:
receiving an instruction to select a target predicate state among a plurality of predicate states on the predicate state diagram;
displaying a waveform diagram corresponding to the target assertion state.
4. The method of claim 2, wherein the method further comprises:
and displaying a waveform diagram corresponding to the state chain.
5. A method as recited in claim 1, wherein the assertion declaration comprises assert, or cover.
6. An electronic device comprises
A memory for storing a set of instructions; and
at least one processor configured to execute the set of instructions to cause the electronic device to perform the method of any of claims 1-5.
7. A non-transitory computer readable storage medium storing a set of instructions of a computer for, when executed, causing the computer to perform the method of any of claims 1 to 5.
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| CN116663467A (en) * | 2023-07-27 | 2023-08-29 | 北京开源芯片研究院 | Method and device for constructing assertion equivalent hardware library, electronic equipment and storage medium |
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