JP2002279789A - Non-volatile semiconductor memory and its programming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable parallel write for a plurality of memory cells one memory cell row of a VG type memory cell array and to shorten a whole programming time. SOLUTION: This device comprises a memory cell array 1 consisting of a plurality of sub-arrays and a control circuit 5. The control circuit 5 performs programming operation comprising a first stage in which a control gate CL capacitively coupled to a channel forming region of a memory transistor constituting a memory cell is driven, each of a plurality of sub-arrays is divided electrically in the row direction every prescribed numbers of memory cells, also, data of the prescribed bit unit to be written simultaneously in a plurality of memory cells selected by division is extracted from input data and it is loaded in the prescribed place and a second stage in a state in which data loaded in the first stage is written in a corresponding sub-array in a stage, in a state which a stage is shifted among a plurality of sub-arrays.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a so-called virtual ground type memory cell array. For example, a memory cell row is divided into a plurality of rows, and a plurality of bits are assigned to a part of a memory cell row accessible by the division. The present invention relates to a nonvolatile semiconductor memory device that can be written in parallel, and a method of programming the same.

[0002]

2. Description of the Related Art A so-called virtual ground (Vertual G)
In the round: VG) type memory cell array structure, for example,
p-type semiconductor substrate or p formed on the main surface of the semiconductor substrate
Without forming a dielectric isolation layer that electrically insulates elements from each other on the surface of a well or the like, only n ⁺
Impurity regions (source / drain impurity regions) are repeatedly formed in parallel stripes at predetermined intervals in the word line direction. On the surface of the p-well between the source / drain impurity regions, a gate electrode is laminated via a plurality of insulating films including charge storage means in or between the films. Therefore, the p-well surface portion functions as a channel formation region of the memory transistor.

In the case of the FG (floating gate) type,
On the lowermost gate insulating film, a floating gate made of a conductive film is formed as a charge storage means, and ON is formed thereon.
A control gate is formed via an inter-gate insulating film such as an O (Oxide-Nitride-Oxide) film. The control gate usually also serves as a word line commonly provided between memory transistors in the word line direction.

On the other hand, MONOS (Metal-Oxide-Nitride-O
In the case of the xide-semiconductor type, a gate electrode is formed over a channel formation region with an ONO film interposed. In this case, carrier traps near the interface between the nitride film and the oxide film in the ONO film and in the nitride film function as charge storage means. Other devices using such charge storage means discretized in the plane and in the film thickness direction facing the channel include an MNOS type, a nanocrystal type, and the like. Note that there are a case where the gate electrode is also used as a word line, and a case where the gate electrode formed in an isolated pattern is connected by an upper metal wiring formed as a word line.

In any of the above types, the source / drain impurity region functions as a bit line or a sub-bit line connected to an upper-layer main bit line. The word lines are usually arranged in parallel stripes perpendicular to the source / drain impurity regions. The VG memory cell array thus configured does not require a dielectric isolation layer and has a common source / drain impurity region for two cells in the word line direction. Therefore, there is an advantage that the memory cell area is small.

[0006]

In a VG type memory cell array, when writing or reading out one memory transistor connected to a certain word line, two sources adjacent to a channel forming region of the memory transistor to be operated are used. Apply a predetermined read drain voltage or write drain voltage between the drain impurity regions.

However, since these source / drain impurity regions are shared by two non-selected memory transistors adjacent in the word line direction, the applied voltage is different from those of the other non-selected memory transistors located outside the non-selected memory transistor. The voltage of one source / drain impurity region is regulated. That is, in order not to operate two adjacent non-selected memory transistors sharing the word line with the selected memory transistor, the two source / drain impurity regions located on both outer sides must have the same level as the adjacent source / drain. Need to be applied. This also applies to the outer and outer source / drain impurity regions. In this manner, when the voltage of the source / drain impurity region of one memory transistor is defined, the effect of the influence is successively spread outward to other source / drain impurity regions connected to the same word line, and finally the memory cell array Even the memory transistor at the end.

Due to the above disadvantages in voltage setting, in a conventional memory cell array, random access for arbitrarily selecting one of a plurality of memory transistors connected to one word line is possible. Cannot be accessed simultaneously. Also,
Even if access can be made, this happens only when the voltage setting constraint is met, and such conditional access is not practical. Therefore, in the conventional memory cell array, a plurality of memory transistors connected to one word line cannot be arbitrarily and independently operated. As a result, in a conventional nonvolatile memory device using a memory cell array, high-speed operation cannot be performed at a word line or close to it, and even if the bit cost is small, it can be applied to a large-capacity application, but the high-speed operation is required. There is a disadvantage that it can not be used.

An object of the present invention is to enable a parallel writing to a plurality of memory cells in one memory cell row of a so-called VG type memory cell array and complete a program of the memory cell row. It is therefore an object of the present invention to provide a nonvolatile semiconductor memory device and a programming method thereof in which the total programming time is reduced as compared with a case where a plurality of parallel writings are continuously performed while sequentially changing an access target in the same row.

[0010]

In order to achieve the above object, a nonvolatile semiconductor memory device according to a first aspect of the present invention has a memory cell array and a peripheral circuit for operating the memory cell array. The memory cell array is
A memory transistor comprising a plurality of sub-arrays having memory cells arranged in a matrix, wherein each of the memory cells has a charge storage means and a channel forming region and is cascaded between memory cells in the same row; A control gate capacitively coupled to a channel forming region of the plurality of sub-arrays, and the peripheral circuit drives the control gate to electrically divide each of the plurality of sub-arrays every predetermined number of memory cells in a row direction, and A first stage for extracting data of a predetermined bit unit to be simultaneously written into a plurality of memory cells selected by division from input data and loading the data in a predetermined location; and loading the data loaded in the first stage in a corresponding sub-array. A program operation including a second stage for writing to the sub-arrays is performed between the plurality of sub-arrays. And a control circuit that performs in a state of being shifted di units.

[0011] In the second stage, the control circuit performs writing and reads and verifies the written data. Alternatively, the program operation includes, in addition to the first and second stages, a third stage for reading and verifying data written by the second stage. Alternatively, the control circuit may control the second stage after the first stage in one program operation.
And the third stage are repeated a plurality of times until the verification result is sufficient for writing.

A data holding circuit for holding the write data on a row-by-row basis is arranged for each of the sub-arrays in the peripheral circuit, and the control circuit controls the data holding circuit, and the control circuit controls the data holding circuit at different timings for at least two sub-arrays. Execute the first stage. Also, a stage for reading and verifying the data after writing is included in the program operation, the data holding circuit holds the write data at the time of writing, and holds the read data at the time of the verification, and compares the read data with a predetermined threshold value. Then, a verification circuit for changing the holding voltage of the data holding circuit to a voltage having a larger amplitude when the comparison result becomes sufficient for writing is arranged for each of the sub-arrays in the peripheral circuit.

Regarding a specific configuration of the memory cell array, preferably, the control gate also serves as a gate of the memory transistor, and is shared by memory cells in the same column. Preferably, each of the memory cells in the same row is arranged between each channel forming region of the plurality of memory transistors cascaded in the row direction, the bit line including a semiconductor impurity region of the opposite conductivity type to the channel forming region. A word line that is capacitively coupled to a part of the channel formation region between the memory transistor and one of the bit lines via a single-layer dielectric film, and a word line formed in each of the memory cells. A select transistor that controls a channel in a part of the channel forming region that is capacitively coupled. In this case, more preferably, two memory transistors sharing a channel formation region are formed in one memory cell, and the select transistor sharing the channel formation region with the two memory transistors is provided between the two memory transistors. Is formed.

In order to achieve the above object, a method for programming a nonvolatile semiconductor memory device according to a second aspect of the present invention includes a memory cell array and a peripheral circuit for operating the memory cell array. A memory cell array comprising a plurality of sub-arrays having memory cells arranged in a matrix, wherein each of the memory cells has a charge storage means and a channel forming region and is cascaded between memory cells in the same row; And a control gate capacitively coupled to a channel formation region of a memory transistor, the method comprising the steps of: (a) driving the control gate; Are electrically divided in the row direction every predetermined number of memory cells, and A first stage for extracting data of a predetermined bit unit to be simultaneously written to a plurality of selected memory cells from input data and loading the data in a predetermined location, and writing the data loaded in the first stage in a corresponding subarray Executing a program operation including the second stage in a state where the stages are shifted by a unit among the plurality of sub-arrays.

According to the present invention, in each sub-array in the memory cell array, one row is electrically divided into a plurality of rows by applying, for example, a voltage at which a channel cannot be turned on to a predetermined number of control gates. By this division, the influence of the bias voltage set in one memory cell is cut off at the division point, and the other memory cells outside it are not affected. As a result, for example, a plurality of memory cells scattered every several bits in the row direction can be simultaneously accessed. Then, data to be written to the access location is simultaneously loaded with data, and writing and verification are continuously performed on this bit unit. At this time, when viewed between the sub-arrays, the execution timing of the program operation is shifted in units of stages such as data load constituting the program operation.

[0016]

FIG. 1 is a block diagram showing a main configuration of a nonvolatile memory device according to an embodiment of the present invention.

This nonvolatile memory device has a memory cell array 1, a row decoder 2, a column decoder 3, an input / output circuit 4, a control circuit 5, and a charge circuit 6. In this figure, a power supply circuit, an address buffer, and the like are omitted. The input / output circuit 4 in the figure includes a column selection circuit CS, a sense amplifier SA, a write circuit WR, a column latch circuit CLH, an input / output buffer I / OBUF.
And all the circuits on the bit line side necessary for writing, erasing and reading.

The row decoder 2 receives the address signal ADR, selects any or all of the plurality of word lines WL arranged in the memory cell array 1 in response thereto, and reads and writes the selected word line WL. Alternatively, it is activated by changing to a voltage corresponding to the erase.

The column decoder 3 has an address signal ADR
In response to this, the column selection circuit CS in the input / output circuit 4 is controlled accordingly, and a plurality of bit lines BL arranged in the memory cell array 1 are selected, for example, every predetermined number.

At the time of reading, the column selection circuit CS connects all of the selected bit lines to the sense amplifier SA,
At the time of writing, all of the selected bit lines are connected to the write circuit WR.

At the time of reading, data stored in the memory cell is transferred from the selected bit line BL to the column selection circuit CS.
And is detected by the sense amplifier SA.
Input / output buffer I / OB via column latch circuit CLH
The data is temporarily stored in a predetermined address of the UF. This is because, as will be described later, data that is collectively read in the present embodiment is discrete every predetermined bit. When all of the stored data in one row are obtained after a plurality of readings, the data is output as read data _Dout to an external data bus or the like in a predetermined word unit, for example. Alternatively, discretely read data may be handled as it is as one-word storage data without buffering, and output to an external data bus or the like.

Further, at the time of writing, it had been temporarily stored input data D _in from the outside to the input-output buffer I / OBUF, after loading the column latch circuit CLH optionally discretely by a column selection circuit CS The data of one row is written into the memory cell while converting the data of one row from the bit line voltage to the threshold voltage of the memory transistor by a plurality of write operations using the plurality of bit lines BL selected as a unit. Alternatively, when the input data D _in from the outside is sent as one-word storage data to be discretely written, the input data is not buffered, but sequentially.
The data may be written in the memory cell array.

The memory cell array 1 according to the embodiment of the present invention is divided into a plurality of sub-arrays (hereinafter, referred to as banks). For example, as shown in FIG.
It has two banks of a size of 12 bytes, that is, a first bank BK1 and a second bank BK2. Bank B
The column latch circuit CLH1 is connected to K1, and the column latch circuit CLH2 is connected to the bank BK2. In each bank, a control gate line CL is provided as a common line in the bit line direction in a pair with the bit line BL, as will be described in detail later. Control gate line C
L may be one for one bit line BL or two for one bit line BL. In addition,
The number of banks is not limited to two and can be arbitrarily determined, such as four or eight. Details of control between banks will be described later.

The control gate lines CL are connected to a control circuit 5. The control circuit 5 receives the control signal decoded by the column decoder 3 and electrically divides the memory cell row connected to one word line according to a predetermined rule, and changes the division. Specifically, the voltage of the control gate line CL, which should be a division, is switched from the initial voltage to the cut-off voltage, and when the division is released, the voltage is switched from the cut-off voltage to the initial voltage.
The control circuit 5 switches the operation mode in response to various permission signals such as the write permission signal WE, and controls the operation timing based on the clock CLK. In addition, it controls the output voltage and the like of the input / output circuit 4 or the row decoder 2 according to a desired operation.

The charge circuit 6 is connected to the bit line BL. The charge circuit 6 is provided with a discharge signal DIS or a precharge signal PR from the column decoder 3.
In response to E, a predetermined bit line is charged and discharged.

Hereinafter, an example of a memory cell array configuration in each bank will be described with reference to FIGS. 3 to 8, and then a program operation according to the present embodiment will be described in detail.

One memory cell constituting the bank according to the present embodiment has a configuration in which a select transistor ST is arranged between two memory transistors MT1 and MT2 having a charge storage layer CAM. Structurally, 1
A select gate (word line WL) is disposed at the center between the source and the drain of the memory cell, and a charge storage layer CAM whose charge storage amount is controlled in accordance with a voltage applied to the control gate CG is disposed on both sides thereof. I have. In the bank according to the present embodiment, the select gate of the select transistor ST of each memory cell MCij is connected to the word line WL,
Both the source and the drain are connected to the bit line BL, and have an array structure in which a control gate line CL for controlling the charge storage layer is arranged in parallel with the bit line BL.

In the present embodiment, it is assumed that data stored in one charge storage layer CAM is one bit. In the memory cell according to the present embodiment, since one select gate is opposed to two bits, the memory cell size per bit is small. The control gate CG and the word line WL are formed of polysilicon or the like, and the bit line BL
Is formed by an n ⁺ impurity diffusion layer.

In the bank according to the present embodiment, there are two types of cell array structures depending on whether the control gate is separated or shared with that of the memory cell adjacent in the word line direction, specifically, the control gate separated type and the control gate shared type. There are two types of cell array structures.

FIGS. 3 to 5 show a control gate separated type bank. 3 is an equivalent circuit diagram showing a control gate separated bank, FIG. 4 is a schematic sectional view of the control gate separated bank in a word line direction (row direction), and FIG. 5 is a partial plan view of the control gate separated bank. FIG.

The control gate separated type bank 1A comprises:
i × j memory cells MC11, M12,.
MC22,..., Mij are arranged in a matrix. In FIG. 3, for simplification of the drawing, eight memory cells MC11, MC1 in two rows and four columns (2 × 4) are shown.
2, MC13, MC14, MC21, MC22, MC2
3, only MC24 is shown.

As described above, each of the memory cells MC11 to MC24 has two memory transistors having the charge storage layer CAM, that is, the first memory transistor MT1 and the second memory transistor MT2. A select transistor S is provided between the first and second memory transistors.
T are arranged so as to share a channel forming region. Memory cells MC11 to MC14 arranged in the first row
Of the select transistor ST of the word line WL1
And the memory cells MC arranged in the second row
The gates of the select transistors 21 to MC24 are commonly connected to the word line WL2. Actually, the gate of the select transistor ST is formed by a word line WL as shown in FIG.

The control gates of the first memory transistors MT1 of the memory cells MC11 and MC21 arranged in the first column are connected to a common control gate line CLL1, and the control gate of the second memory transistor MT2 is connected to a common control gate line CLR1. It is connected to the. Similarly, memory cells MC1 arranged in the second column
2 and the control gate of the first memory transistor MT1 of the MC22 are connected to a common control gate line CLL2, and the control gate of the second memory transistor MT2 is connected to a common control gate line CLR2. The control gates of the first memory transistors MT1 of the memory cells MC13 and MC23 arranged in the third column are connected to a common control gate line CLL3, and the control gate of the second memory transistor MT2 is connected to a common control gate line CLR3. ing. The memory cells MC14 and MC arranged in the fourth column
The control gates of the 24 first memory transistors MT1 are connected to a common control gate line CLL4, and the control gates of the second memory transistors MT2 are connected to a common control gate line CLR4.

The source of each memory cell is connected to the drain of another memory cell adjacent to one side in the row direction, and the drain of each memory cell is connected to the source of another memory transistor adjacent to the other side in the row direction. Have been. The common source and drain are in the bit line direction (column direction).
And a line-shaped source / drain impurity region (n ⁺ impurity diffusion layer) connecting the connection points of other sources and drains. The source / drain impurity regions thus formed have a parallel stripe pattern over the entire bank, as shown in FIG. In the present embodiment, these source / drain impurity regions are used as they are as the bit lines BL1, BL2, BL3,. It should be noted that bit lines BL1, BL2, BL3 formed of metal wiring layers are formed above the source / drain impurity regions.
... may be provided. In this case, each bit line BL1, BL
, BL3,... Are wired in the column direction while appropriately making contact with the corresponding lower source / drain impurity regions.

FIGS. 6 to 8 show a control gate sharing type bank. 6 is an equivalent circuit diagram showing a shared control gate bank, FIG. 7 is a schematic cross-sectional view in the row direction of the shared control gate bank, and FIG. 8 is a plan view of a part of the shared control gate bank.

The shared control gate bank 1B shown in FIG. 6 is the same as the control gate separated bank 1A shown in FIG.
Similarly, for example, i × j memory transistors M
, MC21, MC22, ..., Mij are arranged in a matrix. In FIG. 6, for simplification of the drawing, eight memory cells MC11, MC12, MC13, MC14 of two rows and four columns (2 × 4) are used.
Only MC21, MC22, MC23 and MC24 are shown.

This shared control gate bank 1B
However, the difference from the control gate separated type bank 1A is that the first memory transistor MT1 of each memory cell is
The control gate CG is shared with the second memory transistor MT2 of the adjacent memory cell, and the first and second memory transistors MT1 and MT2 adjacent at the memory cell boundary of two columns are connected to a common control gate line CL. Is to be.

More specifically, the first memory transistors MT1 of the memory cells MC11 and MC21 arranged in the first column
Is the second memory transistor M of the memory cells MC10 and MC20 (not shown) on the left side in the drawing.
It is connected to the control gate line CL0 together with the control gate of T2. Similarly, the memory cell MC1
1 and the control gate of the second memory transistor MT2 of MC21 are connected to the memory cells MC12, M
C22 is connected to the control gate line CL1 together with the control gate of the first memory transistor MT1. The control gates of the second memory transistors MT2 of the memory cells MC12 and MC22 are connected to the control gate line CL2 together with the control gates of the first memory transistors MT1 of the memory cells MC13 and MC23 on the right side in the drawing. Memory cell MC13
And the control gate of the second memory transistor MT2 of MC23 is connected to the memory cells MC14, MC
It is connected to the control gate line CL3 together with the control gates of the 24 first memory transistors MT1. The control gates of the second memory transistors MT2 of the memory cells MC14 and MC24 are connected to the control gate line CL4 together with the control gates of the first memory transistors MT1 of the memory cells MC15 and MC25 (not shown) on the right in the drawing.

The other structure is substantially the same as that of the above-mentioned control gate separated type bank, so that the detailed description is omitted here.

Regarding the charge storage layer CAM, in the case of the control gate separated type, the floating gate (F
G) or a dielectric film including a nitride film on which discrete traps are formed, and in the case of a shared control gate type, a dielectric film including a nitride film on which discrete traps are formed. In each of the memory transistors MT1 and MT2, between the control gate and the p well, M
In the case of the ONOS type, a plurality of dielectric films stacked so as to include an interface between an oxide film and a nitride film are formed. In the case of the FG type or nanocrystal type, a plurality of dielectric films are formed at least immediately below the control gate, and a single film or a conductive material dispersed in countless fine particles is embedded between the films. Have been. The conductive material, or the interface between the oxide film and the nitride film and the carrier traps in the nitride film function as charge storage means of the memory transistor.

The threshold voltage Vth of the memory transistor changes in accordance with the amount of charge stored in the charge storage means. When writing is performed by using channel hot electron (CHE) injection, the amount of charge storage varies depending on, for example, a lateral electric field applied to a channel turned on at the time of writing, and the lateral electric field is determined according to a bit line voltage. .
That is, the write data transmitted to the memory cell as the presence or absence of the bit line voltage setting is converted into a difference in threshold voltage Vth at the time of writing, and stored in the memory cell. At the time of reading, a voltage for turning on or off the memory transistor according to the logic of the stored data is applied to the gate of the memory transistor via the control gate line with a predetermined read drain voltage applied between both bit lines. I do. Thus, only when the memory transistor is turned on, a current flows between both bit lines via the channel, and the bit line voltage changes. The presence or absence of this bit line voltage change is detected and read by the sense amplifier SA or the like. That is, in the case of reading, contrary to the case of writing, the stored data is converted from the difference in threshold voltage Vth of the memory transistor to the bit line voltage difference, so that it can be transmitted to the outside.

The charge storage layer CAM is MON
It is desirable to use an OS (or MNOS) type. The reason is as follows.

In a MONOS type nonvolatile semiconductor memory transistor, a nitride film [S
ix Ny (0 <x <1, 0 <y <1)] in the film or
Carrier traps at the interface between the nitride film and the top oxide film formed thereon are spatially discrete (that is, in the plane direction and the film thickness direction) and spread. For this reason, the charge retention characteristic is not only the bottom dielectric film thickness of the lowermost layer, but also
It depends on the energy and spatial distribution of the charge trapped by the carrier trap in the xNy film.

When a leak current path occurs locally in the bottom dielectric film, in the FG type, a large amount of charge leaks through the leak path, and the charge retention characteristics are apt to deteriorate. On the other hand, in the MONOS type, since the charge storage means is spatially discretized, local charges around the leak path only leak locally through the leak path, and the charge retention characteristics of the entire storage element deteriorate. Hard to do. For this reason,
In the MONOS type, the problem of lowering the charge retention characteristics due to the thinner bottom dielectric film is not as serious as the FG type. Therefore, the scaling property of the bottom dielectric film in a micro memory transistor having an extremely short gate length is as follows.
The MONOS type is superior to the FG type. Further, when electric charges are locally injected into the distribution plane of the carrier traps discretized in a plane, the electric charges are held without being diffused in the plane and in the film thickness direction unlike the FG type.

In the memory cell of this embodiment, a source side injection type MONOS (or NMOS) transistor for injecting CHE from the source side is realized for the purpose of improving the writing speed.

FIG. 9 schematically shows the principle of this source-side CHE injection. At the time of writing, a relatively low voltage is applied to the select gate SG and a relatively high voltage is applied to the control gate CG arranged on the source side of the memory transistor. At this time, a high lateral electric field is generated on the surface of the channel formation region at the boundary between the select gate SG and the charge storage layer CAM. As a result, as shown by the arrow in the figure,
Energically excited charges (channel hot electrons) are injected into the charge storage layer CAM from the source side. The injection efficiency is higher than in a normal CHE injection method in which a high electric field is generated on the drain side and charges are injected into the charge storage layer CAM from the drain side, so that the writing time can be reduced.

The source-side CHE injection can be applied to both the FG type in which the charge storage layer is a floating gate and the MONOS (MNOS) type memory transistor including a nitride film.

The MONOS (MNOS) type memory transistor writes binary information independently on the source side and the drain side of the charge storage layer, paying attention to the fact that charges can be injected into a part of discrete traps by the CHE injection method. It is possible. In this case, 2-bit information is written by CHE injection, for example, by changing the voltage application direction between the source and the drain. At the time of reading, a so-called "reverse read" method in which a predetermined voltage is applied between the source and the drain in a direction opposite to that at the time of writing, the 2-bit information can be reliably read even when the writing time is short and the accumulated charge amount is small. Therefore, in the case of the above-mentioned shared control type, a MONOS (MNOS) type memory transistor is preferable.

FIG. 10 is a sectional view showing a specific example of the structure of a MONOS type memory transistor. The memory transistor includes a gate electrode GT of a select transistor formed on the center of the channel formation region of the p-well W and connected to the word line WL, and first electrodes provided on both sides in the channel direction insulated from the gate electrode GT. It has a control gate CGL of a memory transistor and a control gate CGR of a second memory transistor. Between the control gates CGL, CGR and the bit line BL or the end of the channel formation region, the gate dielectric films 10a, 1
0b is formed.

The gate dielectric film 10a includes a bottom dielectric film 11a, a nitride film 12a, and a top dielectric film 13a. Similarly, the gate dielectric film 10b includes a bottom dielectric film 11b, a nitride film 12b, and a top dielectric film 13b. The gate electrode GT has two control gates CGL and CGL spatially separated on the source side and the drain side.
It is buried between the GR and the lamination pattern of the gate insulating films 10a and 10b via a single-layer dielectric film.
The gate electrode GT is connected to an upper wiring layer forming a word line WL (not shown), and is commonly connected between memory cells in the word line direction.

As described above, the select transistor ST connected to the word line and having the MOS structure is formed at the center of the channel formation region. In addition, control gates CGL and CGR are arranged above the pocket region PCT and the diffusion layer (bit line BL) formed by oblique ion implantation via ONO film type gate insulating films 10a and 10b including charge storage means. I have. This gate G
The combination of T and control gates CGL and CGR is
This is basically the same as the source side injection type memory cell having the split gate structure. The select transistor is used for efficiently performing source side injection at the time of writing. In addition, at the time of erasing, even when the charge storage means is over-erased, the memory transistor plays a role of keeping the threshold voltage Vth in the erased state constant. Therefore, the threshold voltage of this select transistor is set, for example, between 0.5V and 1V.

As the bottom dielectric films 11a and 11b, a silicon oxide film formed by a normal thermal oxidation method and a silicon oxynitride film formed by nitriding the silicon oxide film are used. In addition, a dielectric film exhibiting FN tunneling characteristics, for example, any of a FN silicon nitride film, an FN silicon oxynitride film, or a multilayer film including these and other films can be used as the bottom dielectric film. When a dielectric film exhibiting FN tunneling characteristics is used,
The energy barrier on the conduction band side is reduced from 3.2 eV in the case of a normal silicon oxide film, and the injection efficiency of hot electrons is further improved.

FIG. 11 is a circuit diagram including a part of the input / output circuit and a specific configuration of the charge circuit. In FIG.
The above-described column selection circuit CS and column latch circuit CLH
And a page buffer including a sense amplifier S / A and controlling writing and reading of data in page units where one program is completed.

Each unit of the page buffer connected to one bit line has two inverters INV1, INV
2 and six MOS transistors M0 to M5. The inverters INV1 and INV2 have their inputs and outputs connected to each other, and constitute a column latch circuit CLH. One of the nodes LAT is connected to the bit line via the nMOS transistor M0. The gate of the nMOS transistor M0 is simultaneously controlled in all units by a control signal PGM activated based on the write enable signal WE.

The node LAT of the column latch circuit is nMO
It is connected to the data line I / O via the S-transistor M3, and the other node of the column latch circuit is connected to the data auxiliary line I / O_ via the nMOS transistor M4. The gates of the two nMOS transistors M3 and M4 are controlled by a column selection signal CSL. Also,
The drain of the nMOS transistor M5 whose source is grounded is connected to another node of the column latch circuit. The gate of the nMOS transistor M5 is controlled by a reset signal RST.

Further, two pMOS transistors M1 and M2 are cascaded between the supply line of the power supply voltage V _CC and another node of the column latch circuit. The source of the pMOS transistor M1 is connected to the supply line of the power supply voltage V _CC , the drain is connected to the source of the pMOS transistor M2, and the gate is connected to the bit line BL. The pMOS transistor M1 turns on when the voltage of the bit line BL exceeds its threshold voltage, and maintains the off state when the voltage of the bit line BL is equal to or lower than the threshold voltage. The drain of the pMOS transistor M2 is
It is connected to another node of the column latch circuit. pM
The gate of the OS transistor M2 is connected to the control signal SENSE.
Are controlled simultaneously by all units. The pMOS transistor M2 is turned on / off of the pMOS transistor M1.
Timing control is performed when another node of the column latch circuit is pulled up to the power supply voltage V _CC in accordance with the off state.

The page buffer unit having such a configuration is provided for each bit line.

The discharge circuit has nMOS transistors DM for controlling bit line discharge, the number of which is equal to the number of bit lines. The drain of each nMOS transistor DM is connected to the corresponding bit line BL, and the source is connected to the ground line. The gates of all the nMOS transistors DM are simultaneously controlled by the discharge signal DIS.

The precharge circuit controls bit line charging.
NMOS transistors PM0 to PM2. n
The drains of the MOS transistors PM0 to PM2 are
Pressure V _CCOf the corresponding bit
Connected to the line. nMOS transistors PM0
In the example of FIG. 11, each of PM2
Connected to the line. NMOS transistors of the same sign
Are controlled by the same precharge signal. sand
That is, a plurality of periodically arranged nMOS transistors
The gate of PM0 is activated by a precharge signal PRE0.
Controlled at the same time. Similarly, a plurality of nMOS transistors
The gate of the transistor PM1 is driven by the precharge signal PRE1.
At the same time, and a plurality of nMOS transistors PM
2 at the same time by the precharge signal PRE2
Controlled. The nMOS transistors controlled simultaneously in this manner are
The transistor cycle corresponds to the word division cycle of the bank.
Can be determined. In the example of FIG. 11, the memory cell array
1 has a shared control gate bank,
The minimum unit after word division is three in the word line direction.
(6 bits). For this configuration
In response, precharge the bit lines every three lines at the same time
The precharge circuit is configured as described above.

Next, a program operation for a control gate shared bank will be described with reference to the drawings. FIG. 12 is a diagram showing a program condition for a shared control gate memory cell array. Hereinafter, a case will be described with reference to FIG. 12 where writing and verification are simultaneously performed on the second memory transistors of the memory cells MC11 and MC14 in the first and fourth columns of the shared control gate bank.

When the charge storage layer of the shared control gate type is a MONOS type including a nitride film, 0 V is connected to the bit lines BL0 and BL3 connected to the source sides of the memory cells MC11 and MC14 to be written, and connected to the drain side. 5V or 0V to the applied bit lines BL1 and BL4,
A low voltage of 0.8 V is applied to the word line WL1 connected to the gate of the select transistor ST, and a high voltage of 6 V is applied to the control gate lines CL1 and CL4 connected to the control gate of the second memory transistor MT2 to be written. The unselected left bit portion (first memory transistor M1) in the memory cells MC11 and MC14
T1) has a role of transmitting a desired channel current irrespective of the type of storage data in that portion, and therefore, the control gate lines CL0 and CL0 connected to the control gate of the first memory transistor MT1.
Appropriate voltage Vpass is applied to CL3. Due to these bias conditions, the memory cells MC11 and M
The programming is performed on the second memory transistor MT2 of C14.

On the other hand, the memory cell MC1 to be written
1 and other memory cells MC12 and M
13 is a memory cell MC12 to avoid erroneous writing.
Of the second memory transistor MT2 and the memory cell MC13
The voltage of the control gate line CL2 commonly connected to the first memory transistor is set to 0 V to block the channel current. Thereby, the two memory cells MC1
2, MC13 is not selected. The voltages applied to the control gate lines CL1, CL2,.
Selectively supplied by In addition, unselected word lines W
0V is applied to L2 to block the channel current. As a result, in the control gate sharing type bank 1B, programming of every 6 bits can be performed on the selected word line WL1.

One program operation is actually completed through three steps of data loading, writing, and verifying. Hereinafter, more detailed program control including the control of the peripheral circuits will be described with reference to the drawings of FIGS. FIGS. 13A to 13K are timing charts showing voltage changes of various signal lines during a program operation. These figures illustrate a case where high-level data “0” is stored in the second memory transistor MT2 of the memory cell M11 controlled by the control gate line CL1.

In the initial state, all the bit lines BL0, BL1,...
1, WL2,... Are held at 0V. As for the various control lines in FIG. 11, all the control signals are maintained at a low level except that the control signal SENSE is maintained at a high level to turn off the pMOS transistor M2.

In the data loading step, when the column selection signal CSL1 is set to the high level, the nMOS transistors M3 and M4 forming the column switch are turned on.
As a result, the high-level write data “0” of the data line I / O is transmitted to the node LAT1 of the latch circuit,
Low-level data of data auxiliary line I / O_ is transmitted to another node of the latch circuit. In this way, the data on the data line is input into the page buffer and held by the latch circuit.

Next, in a write step, the program signal PGM is raised from a low level to a high level, the nMOS transistor M0 is turned on, and high-level write data “0” is transferred to the selected bit line BL.
1 from the column latch circuit. Thereafter, a 0.8V select gate pulse is applied to the selected word line WL1, and at the same time, the selected control gate line CL is selected.
1 is applied with a 6 V write pulse. In addition, a voltage Vpa enough to turn on the channel is applied to another control gate line CL0 on the left of the selected control gate line CL1.
Apply ss.

In the selected memory cell, the bit line BL which has become high level due to the write data "0"
The voltage 5V of 1 becomes the drain voltage, the voltage 0V of the bit line BL0 becomes the source voltage, and the applied voltage 6V of the control gate line CL1 becomes the gate voltage. In addition, a channel is formed in the memory cell MC11 by the applied voltage 0.8V of the selected word line WL1 and the applied voltage Vpass of the adjacent control gate line CL0. Electrons supplied from the source (bit line BL0) into this channel are accelerated by the electric field between the source and the drain. At this time, the select gate voltage 0.8V applied to the selected word line WL1 changes near the boundary between the select transistor ST and the second memory transistor MT2.
The value is set to a value at which electrons traveling in the channel are sufficiently excited energetically. For this reason, the probability that electrons in the channel become hot electrons immediately before reaching the source end of the second memory transistor MT2 increases. Some of the hot electrons generated in this way are
The charge is efficiently injected into the charge storage layer CAM in the memory transistor MT2 from the source side. As a result, the threshold voltage Vth of the second memory transistor MT of the memory transistor MC11 changes from a low erase state to a higher state.

In the following verify step, first, a discharge pulse DIS is applied to turn on the nMOS transistor DM, and all the bit lines BL0 and BL
1, ... are discharged. After the discharge, all the bit lines enter a floating state again. Next, the precharge signal PR
By raising E0, the left bit line BL0 connected to the memory cell MC11 storing the bit to be read is charged to the power supply voltage V _CC . Then, the read target cell M
The word line WL1 and the control gate line CL1 connected to 11 are each raised to a predetermined voltage. Further, a voltage Von for sufficiently turning on the channel is applied to another control gate line CL0 connected to the read target cell MC11. Thereby, the read target cell MC
11 turns on, and the bit line BL1, which was floating at 0V, is charged to a voltage obtained by subtracting the threshold voltage Vth of the second memory transistor MT2 of the bit to be read from the applied voltage VcgR of the control gate line CL1. .

The charging voltage of bit line BL1 is transmitted to the gate of pMOS transistor M1 in the page buffer, and it is detected whether or not pMOS transistor M1 can be turned on with this gate voltage. Specifically, the word line WL
1 and the control gate line CL1 fall,
The detection signal SENSE of the read voltage is changed from the high level to the low level.

At this time, when the voltage VBL1 read to the bit line BL1 satisfies the following equation (1), the pMOS transistor M1 turns on.

[Number 1] _{VBL1 = VcgR -Vth <V CC -} | Vth (M1) | ... (1) where, (VCGR -Vth), as described above, the second memory from the applied voltage VCGR control gate line CL1 This is a charging voltage of the bit line BL1 obtained by subtracting the threshold voltage Vth of the transistor MT2. V _CC is the power supply voltage,
Vth (M1) is the threshold voltage of the pMOS transistor M1. When the pMOS transistor M1 is turned on, in the column latch circuit corresponding to the bit line BL1, the other node on the opposite side of the node LAT1 is pulled up to the power supply voltage V _CC , and the node LAT1 is changed from the high level to the ground potential 0.
It is reduced to V. Thus, it is detected that the writing is sufficient.

On the other hand, when the voltage VBL1 read to the bit line BL1 satisfies the following expression (2), the pMOS transistor M1 remains off.

[Number 2] _{VBL1 = VcgR -Vth> V CC -} | Vth (M1) | ... (2) in this case, since the pMOS transistor M1 is not turned on, the node LAT1 will remain at a high level. Therefore, in this case, it is detected that writing is not yet sufficient.

The above-described program operation including the steps of data loading, writing, and verifying is performed every three cells, that is, the second operation of MC11, MC14,.
This is executed in parallel with the memory transistor MT2.
At this time, for a cell to which high-level data “0” is not written, the node LAT on the write side of the column latch circuit becomes low level at the time of data loading. Is assumed to be Further, the program operation including the steps of data loading, writing and verifying is performed at the node LA of all the column latch circuits corresponding to the cells to be written in parallel.
This operation is repeated until T has a low level.

Although details are omitted, when a program operation is performed on the first memory transistor MT1 side in this circuit configuration, the column switch and the column latch circuit in the page buffer are one lower order. That is,
Data to be written to the first memory transistor MT1 of the memory cell M11 is input from the column switch controlled by the column selection signal CSL0 to the node LAT0, and is written into the memory cell MC11 via the bit line BL0. Also, in the verify read, the bit line BL0 is set to the floating state of 0 V, so that the data is read to the column latch circuit having the node LAT0.

FIG. 14 is a diagram showing program conditions for a control gate separated type memory cell array.
Here, a case where programming is performed on the second memory transistor MT2 on the right side of the memory cells MC11 and MC13 will be described as an example.

When the charge storage layer of the control gate separated type is a floating gate FG, 0 V is applied to the bit lines BL0 and BL2 connected to the source sides of the memory cells MC11 and MC13 to be written, and the bit connected to the drain side. 5 V or 0 V on lines BL1 and BL3,
A low voltage of 1.5 V is applied to the word line WL1 connected to the gate of the select transistor ST, and a high voltage of 12 V is applied to the control gate lines CLR1 and CLR3 connected to the control gate of the second memory transistor MT2 to be written. Memory cells MC11, MC1
3 has a function of transmitting a desired channel current to the unselected left-side bit portion (first memory transistor MT1) regardless of the type of data stored in that portion. Control gate line C connected to the control gate
Appropriate voltage Vpass is applied to LL1 and CLL3. Due to these bias conditions, the memory cell MC to be written is
11, the programming is performed on the second memory transistor MT2 of the MC13.

On the other hand, the memory cell MC1 to be written
1 and MC13, other memory cells MC12 and M
C14 controls the voltages of the control gate lines CLL2 and CLL4 to which the control gate of the first memory transistor MT1 is connected and the control gate lines CLR2 and CLR4 to which the control gate of the second memory transistor MT2 is connected in order to avoid erroneous writing. 0V
And block the channel current. As a result, the second
One of the memory cells MC12 and MC14 is not selected. The voltages applied to the control gate lines CLL and CLR are selectively supplied by the control circuit 5. Further, 0 V is applied to the unselected word line WL2 to block the channel current. As a result, in the control gate separated type bank 1A, the program can be performed every four bits for the selected word line WL1.

This control gate separated type bank 1A
, One program operation including data loading, writing, and verifying is performed under substantially the same control as in FIG.

Here, it is assumed that bits in word line units are pages and the page size is 512 bytes. In the two types of banks 1A and 1B described above, programming can be performed every 4 bits or every 6 bits in the word line direction. In the following, for ease of explanation, 8
It is assumed that programming is performed for each bit. Therefore,
The number of bits programmed simultaneously in one word is 64 By
te (= 512 Byte ÷ 8). Hereafter, this 64
The entire Byte program is called a program instruction. As shown in FIG. 15, the program instruction is obtained by repeating a combination of writing and verifying several times following data loading. As mentioned earlier, data loading is
This is the step of loading the program data into the column latch circuit connected to the bit line, and applying the write pulse to the bit to be written by changing the word line, control gate line and bit line to the voltage at the time of writing. And the verification is
This is a reading step for verifying whether or not the threshold voltage of the memory transistor has reached a desired value for the bit to be written. The number of repetitions of the write step and the verify step in the program instruction fluctuates depending on the number of bytes to be simultaneously programmed and the variation of the threshold voltage. I do.

Under the above assumption, a program time per page is calculated for a conventional nonvolatile memory device in which the memory cell array is not divided into a plurality of banks as in the present invention. In this conventional nonvolatile memory device, a program command consisting of data loading, writing, verifying, writing, and verifying is executed for 64 bytes that are provided every 8 bits in the word line direction. continue,
A similar program instruction is executed for the next 64 bytes. By repeating the program instruction for 64 Bytes simultaneously eight times, one page (512
Byte) is completed.

FIG. 16 illustrates a program procedure of the conventional nonvolatile memory device. In this figure, the data load is represented by "L" and its time is assumed to be 4 μs. Writing is represented by “W” and the time is 10 μs
Assume that Verify is represented by "V", and its time is assumed to be 10 μs. As a result, the programming time for one page is 352 μs (= (4 μs + 10 μs + 10 μs + 1)
0 μs + 10 μs) × 8). The program speed in this case is 1.45 MByte / s (= 512 Byte /
352 μs). This program speed does not meet the required speed for a memory card application requiring a minimum of 2 to 3 MByte / s.

Hereinafter, several embodiments of the program operation procedure in the nonvolatile memory device of the present invention, which can perform a higher-speed program when the programming speed of the conventional nonvolatile memory device is used as a reference, will be described. In the nonvolatile memory device according to the present invention, the memory cell array is divided into a plurality of banks, and the execution of the program instruction is performed while shifting the time between the banks. Here, the concept of “stage” is introduced as a unit of the shift. The stage is a single operation or a combination of a plurality of operation steps such as data loading, writing, and verifying.

First Program Operation In the first program operation, data loading is performed in the first program operation.
, And two repetitions of write and verify are defined as a second stage, and the first and second stages constitute one program instruction.

Here, page 1 is stored in bank BK1 of FIG.
, And in parallel with this, page 2 is programmed in the bank BK2. FIG. 17 shows a conceptual diagram of the program procedure in that case. First, a set of bits scattered every 8 bits in the page 1 of the bank BK1 (hereinafter, a set of bits)
In the figure, the first 64 bytes is "64 bytes"
) Is executed. At the same time as the start of the first write W of this program instruction, the bank B
The data load L is started for the first 64 bytes in page 2 of K2. Then, the first 6 in bank BK2
The first write W of 4 Bytes is performed by the first write W of the bank BK1.
At the same time as the end of the last verify V of 64 bytes. At the same time, at the same time, a set of bits shifted by one bit from the first 64 bytes of the bank BK1 (hereinafter referred to as a second 64 bytes;
The data load L is started. Thereafter, the first write W of the second 64 bytes in the bank BK1 is started at the same time as the end of the last verify V of the first 64 bytes in the bank BK2. At the same time, data loading is started for the second 64 bytes in the bank BK2.

The same operation is performed for the third to eighth 64 bytes.
Is repeatedly executed. As a result, all bits (512 bytes) of page 1 and all bits (51 bytes) of page 2
Execution of the program instruction of 2 bytes) is completed.

The total time of this program operation is 644 μm
s, which is 322 μs when converted to the program time per page. The program time per page was reduced by 30 μs as compared with FIG.

Second Program Operation In the second program operation, data loading, writing, verifying, writing, and verifying are each performed by one.
One program instruction is composed of the first to fifth stages.

Here, page 1 is stored in bank BK1 of FIG.
, And in parallel with this, page 2 is programmed in the bank BK2. FIG. 18 shows a conceptual diagram of the program procedure in that case. First, a program instruction is executed for the first 64 bytes of the bank BK1. Simultaneously with the start of the first write W of this program instruction,
The data load L is started for the first 64 bytes of the bank BK2. That is, the first 64 By of the bank BK1
1 stage (10 μs) for te program instruction
The program instruction of the first 64 bytes of the bank BK2 is shifted later. 1 stage (10μs)
Is passed, the first write W of the first 64 bytes in the bank BK2 is transferred to the first 64 bytes of the bank BK1.
Starts at the same time as the first verify V.

Thereafter, the first 64 bytes of the bank BK1
When the program instruction for e is completed, the column latch circuit is opened for the first time. Therefore, simultaneously with the end of the program instruction, the second 64 bytes of bank BK1
Start loading data. Thereafter, the second stage of the bank BK2 is synchronized with the start of the second stage (write W) of the second 64 bytes of the bank BK1 or the end of the program instruction of the first 64 bytes of the bank BK2, whichever is later. The 64-byte data load L is started. In the figure, the number of repetitions of write and verify in the program instruction is unified to two times, and the start of the second stage (write W) of the second 64 bytes of the bank BK1,
The end of the first 64 byte program instruction in bank BK2 is the same. However, in practice, the number of repetitions may be one, three, or four or more. Therefore, unless the data load L of the second 64 bytes of the bank BK2 is started in synchronization with the later one, a regular operation cannot be performed thereafter. The above-described control of synchronizing to the slower one is for guaranteeing this regular operation.

The same operation is performed for the third to eighth 64 bytes.
Is repeatedly executed. As a result, all bits (512 bytes) of page 1 and all bits (51 bytes) of page 2
Execution of the program instruction of 2 bytes) is completed.

The total time of this program operation is 410 μ
s, which is 205 μs in terms of the program time per page. The program time per page was reduced by 147 μs as compared with FIG.

Third Program Operation The third program operation is a modification of the second program operation. Here, data loading, writing, verifying, writing, and verifying are each one stage.

Similarly to the first and second program operations, page 1 is programmed in bank BK1 in FIG. 2, and page 2 is programmed in bank BK2 in parallel. Figure 1 shows a conceptual diagram of the program procedure in that case.
It is shown in FIG.

In the above-described first and second program operations, the data load time was 4 μs, which was shorter than the write or verify time 10 μs. However, if the writing or verifying time is shortened and becomes shorter than the data load time, in the first and second program operations described above, a standby time for writing and verifying with a large number of repetitions is generated, and the entire program time is shortened. Disadvantaged.

For such a reason, in the third program operation, data of one page is first loaded over 30 μs. However, in order to perform page batch data loading in the case of 2-bit / cell storage, for example, FIG.
In the circuit configuration shown in FIG. 1, another page buffer is required. Here, there are two types of program instructions. Program instruction 1 is applied to the first 64 bytes, and includes data load, write, verify, write,
Verify each stage as one,
The fifth stage forms one program instruction.
The program instruction 2 is applied to the second to eighth 64 bytes, and each of write, verify, write, and verify is one stage, and these sixth to ninth stages constitute one program instruction.

First, in the first 30 μs, the data loading of page 1 (512 bytes) of the bank BK1 is performed collectively. Then, in the next 30 μs,
Data loading of page 2 (512 bytes) of the bank BK2 is performed at once. The execution of the second to fifth stages (two repetitions of the write W and the verify V) of the bank BK1 is started from the end of the data loading of the bank BK2. Further, in synchronization with the end of the second stage in the middle, the execution of the second to fifth stages (two repetitions of write W and verify V) of the bank BK2 is started. Thereafter, when the program instruction 1 is completed for the first 64 bytes of the bank BK1, the column latch circuit is opened for the first time. Therefore, at the same time as the end of the program instruction 1, the writing of the second 64 bytes of the bank BK1 is started.

Thereafter, the second 64 Byte of the bank BK1 is
Start of the 7th stage (verify V) of e
First 64 byte program instruction 1 of bank BK2
, The writing W of the second 64 bytes of the bank BK2 is started in synchronization with the later of the end of the writing. In the figure, the number of repetitions of write and verify in the program instruction is unified to two, the start of the seventh stage (verify V) of the second 64 bytes of bank BK1, and the end of the first 64 bytes of program instruction of bank BK2. Is the same. However, in practice, the number of repetitions may be one, three, or four or more.
Therefore, unless the write W of the second 64 bytes of the bank BK2 is started in synchronization with the later one, a regular operation cannot be performed thereafter. The above-described control of synchronizing to the slower one is for guaranteeing this regular operation.

The same operation is performed for the third to eighth 64 bytes.
Is repeatedly executed. As a result, all bits (512 bytes) of page 1 and all bits (51 bytes) of page 2
Execution of the program instruction of 2 bytes) is completed.

The total time of this program operation is 390 μm
s, which is 195 μs when converted to the program time per page. The program time per page is reduced by 157 μs as compared with FIG.

Fourth Program Operation In the fourth program operation, as shown in FIG. 20, a nonvolatile memory device in which a memory cell array is divided into eight banks and a row decoder and a column latch circuit are provided in each bank. Applied to Data loading, writing,
Verify, write, and verify are each one stage, and these first to fifth stages constitute one program instruction.

FIG. 21 shows a conceptual diagram of a program operation for the first 64 bytes. Other second to eighth 64B
Each of the program operations of “yte” in FIG.
The illustration is omitted because it is the same as.

First, the first 64 bytes of the bank BK1
Execute the program instruction for. At the same time as the start of the first write W of the program instruction, the data load L is started for the first 64 bytes of the bank BK2. That is, the first 64 Byte program instruction of the bank BK2 is started after being shifted by one stage (10 μs) from the first 64 Byte program instruction of the bank BK1. Similarly, the first 64-byte program instruction of the bank BK3 is shifted by one stage (10 μs) after the first 64-byte program instruction of the bank BK2. Such a control of simply shifting the program instruction by one stage at a time is possible because each of the eight banks has a column latch circuit, so that there is no need to wait for the column latch circuit to open. Was.

The same operation is repeatedly executed for the first 64 bytes in the third to eighth banks. Thus, the execution of the program instruction of 512 bytes, which is the sum of the first 64 bytes of page 1 to page 8, is completed. The above operation is performed for the remaining second to eighth 64 bytes.
For 8 banks totaling 4096
Byte program operation is completed.

The program time per 512 bytes corresponding to one page of this program operation is 120 μs.
Is calculated. The program time per page was reduced by 232 μs as compared with FIG.

Although the fourth program operation has been described using an 8-bank memory cell array, in the case of FIG. 21, the time required for completing the execution of the program instruction for one 64 Byte is 50 μs, and The program operation starts in the same bank after 70 μs
(= 120 μ−50 μs) has elapsed. Therefore, the empty time of the column latch circuit is as long as 70 μs. Therefore, for example, a half four-bank configuration can be adopted. Even in this case, the column latch circuit does not wait (the idle time of the column latch circuit: 30 μm).
s) The program time per page is 120 μs, which is the same as in the above-described eight-bank configuration.

Fifth Program Operation The program instruction in the present invention may include data loading and writing steps, and verification is not necessarily required. This is a case where a desired threshold voltage can be obtained by one writing depending on the structure of the memory transistor and the like, and high writing accuracy is guaranteed. In the fifth program operation, this verify is omitted. Therefore, data loading and writing are each performed in one stage, and a program instruction is composed of these two first and second stages.

Here, as shown in FIG. 22, the memory cell array is divided into four banks. Each bank includes a column latch circuit and a row decoder. Also, the page size of each bank is twice the page size in the other program operation described above, that is, 1024 bytes (=
512 bytes × 2). Since the number of bytes to be written simultaneously is 128 bytes, which is twice that of other program operations, the data load time is also doubled to 8 μs.
Becomes

FIG. 23 shows a conceptual diagram of a program operation for the first 128 bytes. Other second to eighth twelfth
Since each program operation of 8 bytes is the same as that of FIG. 23, it is not shown.

First, the first 128 bytes of the bank BK1
e, data load L (8 μs) and write W (1
0 μs). At the same time as the start of writing W of this program instruction, the bank BK
Data load L is started for the first 128 bytes of the second. That is, the first 128-byte program instruction of the bank BK2 is started after being shifted by one stage (10 μs) with respect to the first 128-byte program instruction of the bank BK1. Similarly, the first 12
One stage (10
μs) to be shifted to the first 128 bytes of the bank BK3.
Start the program instruction of e. Also, the first 128-byte program instruction of bank BK3 is shifted by one stage (10 μs) after the first 1-byte program instruction of bank BK4.
Start a 28-byte program instruction. Such control of simply shifting the program instruction by one stage at a time is possible because each of the four banks has a column latch circuit, so that there is no need to wait for the column latch circuit to open. Was.

Thus, the execution of the program instruction of 512 bytes, which is the sum of the first 128 bytes of page 1 to page 4, is completed. The above operation is performed for the remaining second to second
By repeating sequentially for the eighth 128 bytes,
The program operation of a total of 8192 bytes in four banks is completed.

The program time per 512 bytes corresponding to one page of this program operation is calculated as 48 μs. On the other hand, in FIG. 16, if one program instruction has a two-stage configuration of data loading and writing,
The program time for one page is 112 μs.
Therefore, as compared with the case where the program instructions are sequentially executed as shown in FIG. 16, the program time per page is reduced by 64 μs by the fifth program operation.

[0111]

According to the present invention, for each sub-array constituting a memory cell array, parallel programming can be performed on a part of the electrically divided sub-arrays in the same row. Therefore, several program operations corresponding to the number of divisions are required to complete a one-line program. At this time, since the execution timing of the program operation is shifted between the sub-arrays, the total program time is reduced. As described above, the program time of the so-called virtual ground type memory cell array is greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main configuration of a nonvolatile memory device according to an embodiment.

FIG. 2 is a block diagram illustrating a first example of a bank configuration of the nonvolatile memory device according to the embodiment.

FIG. 3 is an equivalent circuit diagram of a control gate separated bank according to the embodiment;

FIG. 4 is a schematic cross-sectional view in a word line direction (row direction) of a control gate separation type bank according to the embodiment.

FIG. 5 is a plan view of a part of the control gate separated bank according to the embodiment.

FIG. 6 is an equivalent circuit diagram of a shared control gate bank according to the embodiment.

FIG. 7 is a schematic cross-sectional view in the row direction of the shared control gate bank according to the embodiment.

FIG. 8 is a plan view of a part of the shared control gate bank according to the embodiment.

FIG. 9 is a diagram for describing source side implantation in which the memory cell according to the embodiment can operate.

FIG. 10 is a cross-sectional view showing a specific structure example of the MONOS type memory transistor according to the embodiment.

FIG. 11 is a circuit diagram including a specific configuration of a part of an input / output circuit and a charge circuit in the nonvolatile memory device according to the embodiment;

FIG. 12 is a diagram showing program conditions for a shared control gate memory cell array according to the embodiment.

FIGS. 13A to 13K are timing charts showing voltage changes of various signal lines during a program operation for the shared control gate memory cell array according to the embodiment;

FIG. 14 is a diagram showing program conditions for a control gate separated type memory cell array according to the embodiment.

FIG. 15 is an explanatory diagram illustrating one program instruction.

FIG. 16 is an explanatory diagram illustrating a program procedure of a conventional nonvolatile memory device used as a comparison object of the present invention.

FIG. 17 is a conceptual diagram showing a procedure of a first program operation according to the embodiment.

FIG. 18 is a conceptual diagram showing a procedure of a second program operation according to the embodiment.

FIG. 19 is a conceptual diagram showing a procedure of a third program operation according to the embodiment.

FIG. 20 is a block diagram illustrating a second bank configuration example of the memory cell array according to the embodiment;

FIG. 21 is a conceptual diagram showing a procedure of a fourth program operation according to the embodiment.

FIG. 22 is a block diagram showing a third bank configuration example of the memory cell array according to the embodiment.

FIG. 23 is a conceptual diagram showing a procedure of a fifth program operation according to the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Column decoder, 4 ... Input / output circuit, 5 ... Control circuit, 6 ... Charge circuit, 10a, 10b ... Gate dielectric film, 11a, 1
1b: bottom dielectric film, 12a, 12b: nitride film, 13
a, 13b: top dielectric film; 14: single-layer dielectric film;
CS: column selection circuit, SA: sense amplifier, WR: write circuit, CLH: column latch circuit, I / OBUF
... I / O buffers, MC11 to MC14, MC21 to M
C24: memory cell, MT1: first memory transistor, MT2: second memory transistor, ST: select transistor, WL, WL1, WL2: word line, BL
0 to BL4... Bit lines, CLL1 to CLL4, CLR1
~ CLR4, CL1 ~ CL4 ... control gate lines,
CAM: charge storage layer, INV1, INV2: inverter, M1 to M5, DM, PM0 to PM2: MOS transistor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/792 F-term (Reference) 5B025 AA03 AB01 AC01 AD04 AD05 AE05 5F083 EP02 EP24 EP34 EP42 EP44 EP49 EP75 GA15 JA04 LA02 PR37 ZA20 5F101 BA01 BA29 BB03 BC02 BD33 BE05 BH09

Claims (13)

[Claims] 1. A memory cell array comprising: a memory cell array; and a peripheral circuit for operating the memory cell array. The memory cell array includes a plurality of sub-arrays having memory cells arranged in a matrix. A memory transistor having charge storage means and a channel forming region and cascaded between memory cells in the same row; and a control gate capacitively coupled to a channel forming region of the memory transistor, wherein the peripheral circuit comprises the control gate To electrically divide each of the plurality of sub-arrays every predetermined number of memory cells in the row direction, and to input data of a predetermined bit unit to be simultaneously written to the plurality of memory cells selected by the division. The first stage, which is extracted from the The program operation and a second stage to write over de data in the corresponding sub-array, the nonvolatile semiconductor memory device comprising a control circuit that executes in a state of being shifted to stage unit among a plurality of sub-arrays. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said control circuit performs writing in said second stage and reads and verifies the written data. 3. The nonvolatile semiconductor memory according to claim 1, wherein said program operation includes, in addition to said first and second stages, a third stage for reading and verifying data after writing by said second stage. apparatus. 4. The control circuit according to claim 3, wherein, in one program operation, after the first stage, the second and third stages are repeated a plurality of times until a verification result is sufficiently written. Nonvolatile semiconductor memory device. 5. A data holding circuit for holding the write data on a row-by-row basis is arranged in each of the sub-arrays in the peripheral circuit, and the control circuit controls the data holding circuit, and
2. The nonvolatile semiconductor memory device according to claim 1, wherein said first stage is executed at a different timing for one sub-array. 6. A data holding circuit that includes a stage for reading and verifying data after writing in the program operation, holding the write data at the time of writing, and holding the read data at the time of the verification, A verification circuit for comparing a holding voltage of the data holding circuit to a voltage having a larger amplitude when the result of comparison is sufficient for comparison with a threshold value is provided for each of the sub-arrays in the peripheral circuit. 2. The nonvolatile semiconductor memory device according to 1. 7. The nonvolatile semiconductor memory device according to claim 1, wherein said control gate also serves as a gate of said memory transistor and is shared between memory cells in the same column. 8. A bit line, which is arranged between each channel forming region of the plurality of memory transistors cascaded in the row direction and is made of a semiconductor impurity region of a conductivity type opposite to the channel forming region, and each memory cell in the same row. A word line capacitively coupled to a part of a channel formation region between a memory transistor and one of the bit lines via a single-layer dielectric film; and a word line formed in each of the memory cells. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising a select transistor that controls a channel in a part of the channel forming region that is capacitively coupled. 9. Two memory transistors sharing a channel forming region are formed in one memory cell, and the select transistor sharing a channel forming region with the two memory transistors is formed between the two memory transistors. The nonvolatile semiconductor memory device according to claim 8. 10. A memory cell array and a peripheral circuit for operating the memory cell array, wherein the memory cell array is composed of a plurality of sub-arrays having memory cells arranged in a matrix, and each of the memory cells is A memory transistor having charge storage means and a channel forming region, cascaded between memory cells in the same row, and a control gate capacitively coupled to the channel forming region of the memory transistor. The method includes the following steps: driving the control gate to electrically divide each of the plurality of sub-arrays every predetermined number of memory cells in a row direction; Extract data of a predetermined bit unit to be written simultaneously to memory cells from input data. And shifting a program operation including a first stage for loading data into a predetermined location and a second stage for writing data loaded in the first stage into a corresponding sub-array in units of a plurality of sub-arrays. A method for programming a nonvolatile semiconductor memory device, the method being executed in a state where the nonvolatile semiconductor memory device is executed. 11. The programming method for a nonvolatile semiconductor memory device according to claim 10, wherein in the second stage, writing is performed, and data after the writing is read and verified. 12. The nonvolatile memory according to claim 10, wherein said program operation step includes, in addition to said first and second stages, a third stage for reading and verifying data after writing by said second stage. A method for programming a semiconductor storage device. 13. The nonvolatile memory according to claim 10, wherein in said one step of said program operation, after said first stage, said second and third stages are repeated a plurality of times until a verification result is sufficiently written. A method for programming a semiconductor storage device.