JP2004280965A - Nonvolatile semiconductor memory device and its data read method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To securely read data at a high speed in a nonvolatile semiconductor memory device having a non-conductive trap gate. <P>SOLUTION: Source/drain regions of cell transistor Mi and an adjacent cell transistor Mi-1 or Mi+1 are electrically connected in common by a column line SDLi or SDLi+1. Column selecting means (P/B1-P/B9)apply reference voltage (0V) to a selected column line, and set read-out voltage states (BL) to the other column lines. Data D of a plurality of bits are read simultaneously from a plurality of column lines being adjacent the column line to which the reference voltage (0V) is applied, but, at the time, since a current is not made to flow in a cell transistor (e.g. M3, M7) not to be read and not connected to the column line to which the reference voltage (0V) is applied, the data D can be surely read at high speed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory device in which memory transistors storing a plurality of bits of data are arranged in rows and columns in a non-conductive trap gate, and to a data reading method thereof.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, an EPROM (Erasable and Programmable Read Only Memory) having an FG (Floating Gate) type memory transistor has been known as a kind of nonvolatile memory device (for example, see Patent Document 1).
The nonvolatile memory described in Patent Document 1 has a conductive floating gate and a control gate above a well between a source region and a drain region or above a surface portion of a semiconductor substrate (hereinafter, referred to as a channel formation region). . The floating gate is embedded in the insulating film, and the control gate is formed on the insulating film. The non-volatile memory stores 1-bit data for each memory cell in accordance with whether or not charge is injected into the floating gate, or the amount of charge injected.
However, if a slight defect exists in the gate oxide film immediately below the floating gate formed by thermally oxidizing the channel formation region, most of the accumulated electrons in the floating gate are transmitted through the defect because the floating gate is conductive. It may disappear on the substrate side. Therefore, the FG type nonvolatile memory has a problem that its reliability cannot be increased.
[0003]
Separately from the FG type nonvolatile memory, a non-conductive charge trap gate is provided instead of the floating gate, and charges are locally trapped on the source side and the drain side of the trap gate to store 2-bit data. A new type of non-volatile memory has been proposed (for example, see Non-Patent Document 1).
In the nonvolatile memory described in Non-Patent Document 1, since the trap gate is non-conductive, the ratio of the electrons that are lost among the locally stored electrons even if a defect exists in the gate oxide film. Has the advantage of being extremely low and therefore high in reliability.
[0004]
In addition, as an array configuration of a memory cell that stores 2-bit data, a column line commonly connecting a source or a drain of a transistor column is shared by two adjacent transistor columns in a row direction, and one column is read out in four read cycles. 2. Description of the Related Art A non-volatile memory that reads all bit data in a row is known (for example, see Patent Document 2).
[0005]
Hereinafter, the page reading method described in Patent Document 2 will be described with reference to the drawings.
FIGS. 10A and 10B are diagrams for explaining the operation of the memory cell array at the time of the first page read for reading the first 8-bit data. FIGS. 11A and 11B are diagrams for explaining the next 8 bits. FIG. 11 is a diagram illustrating an operation of the memory cell array at the time of a second page read for reading bit data.
Here, two bits of data are stored in the respective trap gates of the eight memory transistors M1 to M8, and a total of 16 bits of data is read from nine column lines (source / drain lines) SDL1 to SDL9. explain. Data read / hold circuits P / B1 to P / B9 called page buffers are connected to the source / drain lines SDL1 to SDL9, respectively.
[0006]
In the first half of the first page read (hereinafter referred to as read cycle (1)), as shown in FIG. 10A, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = 0 V by the respective page buffers. BL, F, BL, 0 V, BL, F, BL, 0 V are set. Here, “0V” means a reference voltage state, “F” means an electrically floating state, and “BL” means a read voltage state. As a result, the presence / absence of a current corresponding to the electric charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 10A is determined by the page buffers P / B2, P / B4, P / B6, P / Detected by B8. That is, assuming that the storage data on the left side of the diagram of the trap gate of the memory transistor Mj (j = 1, 2,..., 8) is Dj (SD1) and the storage data on the right side is Dj (SD2), the cell transistors M1, M4, In M5 and M8, data D1 (SD1), D4 (SD2), D5 (SD1), and D8 (SD2) on the source / drain line side in the reference voltage state (0 V) are stored in page buffers P / B2 and P / B4, respectively. , P / B6, and P / B8, and are held.
[0007]
In the latter half of the first page read, as shown in FIG. 10B, the states of the source / drain lines SDL1 to SDL9 are one by one in one direction (rightward in the figure) from the state of the read cycle (1). Will be shifted. That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = BL, 0V, BL, F, BL, 0V, BL, F, BL by the respective page buffers. As a result, the presence / absence of a current corresponding to the charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 10B is determined by the page buffers P / B1, P / B3, P / B5, and P / B. Detected by B7. That is, in the cell transistors M1, M2, M5, and M6, the data D1 (SD2), D2 (SD1), D5 (SD2), and D6 (SD1) on the source / drain line side in the reference voltage state (0 V) are respectively paged. The data is read and held by the buffers P / B1, P / B3, P / B5, and P / B7.
[0008]
By the read cycles (1) and (2), the stored data of one page consisting of a total of 8 bits is read and held in the eight page buffers P / B1 to P / B8, whereby the first page data is stored. The read ends. Thereafter, by appropriately selecting a page buffer, the held data is output to an output bus (not shown). By using a plurality of output data buses, it is possible to output a plurality of data simultaneously.
[0009]
Next, a second page read operation is performed. The second page read operation is executed by read cycles (3) and (4).
In the first half of the second page read (read cycle (3)), the states of the source / drain lines SDL1 to SDL9 are further shifted one by one as shown in FIG. You. That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = F, BL, 0V, BL, F, BL, 0V, BL, F by the respective page buffers. As a result, the presence / absence of a current corresponding to the charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 11A is determined by the page buffers P / B2, P / B4, P / B6, and P / B. Detected by B8. That is, in the cell transistors M2, M3, M6, and M7, the data D2 (SD2), D3 (SD1), D6 (SD2), and D7 (SD1) on the source / drain line side in the reference voltage state (0 V) are respectively paged. The data is read out and held by buffers P / B2, P / B4, P / B6, and P / B8.
[0010]
In the latter half of the second page read (read cycle (4)), as shown in FIG. 11B, the state of the source / drain lines SDL1 to SDL9 is further shifted one by one as compared with the state in the read cycle (3). You. That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = BL, F, BL, 0V, BL, F, BL, 0V, BL by the respective page buffers. As a result, the presence / absence of a current corresponding to the charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 11B is determined by the page buffers P / B3, P / B5, P / B7, P / Detected by B9. That is, in the cell transistors M3, M4, M7, and M8, the data D3 (SD2), D4 (SD1), D7 (SD2), and D8 (SD1) on the source / drain line side in the reference voltage state (0 V) are paged, respectively. The data is read and held by buffers P / B3, P / B5, P / B7, and P / B9.
[0011]
By the read cycles (3) and (4), one page of stored data consisting of a total of 8 bits is read and held in the eight page buffers P / B2 to P / B9, whereby the second page The read ends. Thereafter, by appropriately selecting a page buffer, the held data is output to an output bus (not shown).
[0012]
The order of the four types of read cycles is as follows from (1) → (2) → (3) → (4).
(1) → (2) → (4) → (3),
(2) → (1) → (3) → (4),
(1) → (4) → (2) → (3),
(1) → (4) → (3) → (2),
(4) → (1) → (2) → (3),
(4) → (1) → (3) → (2)
Can be changed to any of
[0013]
[Patent Document 1]
Registered Patent No. 3104319
[Patent Document 2]
JP-A-2001-118390 (page 6, FIG. 8)
[Non-patent document 1]
U.S. Patent (No .: US6011725), "Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Semiconductor Utilizing Asymmetrical Charging Trap"
[0014]
[Problems to be solved by the invention]
In a non-volatile memory, the peripheral circuits of the memory are turned off in a standby state in order to reduce power consumption, and then when the memory circuit is driven, immediately after the drive, the source / drain line remains in a floating state while the potential of the source / drain line is low. May be.
Further, even in the normal operation, the source / drain line may change from (0 V) to the floating state (F) depending on the transition of the state of the source / drain line. For example, when the order of the page read operation in Patent Document 2 changes in the order of the read cycle (1) → (2) → (4) → (3) included in the above-described modification, the bias state is changed as shown in FIG. The state shown in FIG. 11B may transition to the state shown in FIG.
In such a case, paying attention to the source / drain line DL6 which was in the reference voltage state (0 V) in FIG. 10B, the source / drain line DL6 transitions to the floating state (F) in FIG. 11B. Therefore, a floating state at a low voltage of approximately 0 V is obtained. Therefore, the source / drain line SDL6 is charged from the low potential to the read bit line voltage by the current flowing through the two memory transistors M5 and M6 on both sides thereof. In a large-capacity memory array, since the parasitic capacitance of each source / drain line is large, it takes time until the potentials of the source / drain lines SDL4 and SDL7 to be read are stabilized. If the data reading of the cell transistors M4 and M7 is started during a period in which the potential is not stabilized for high-speed reading, even if no current flows through the cell transistor from which the data is to be read, the source / drain Due to the current temporarily flowing to charge the parasitic capacitance of the line SDL6, it is determined that the current flows in the transistors M4 and M7, and erroneous data may be read.
In order to avoid this malfunction, in the nonvolatile memory described in Patent Document 2, it is necessary to wait until the bias voltage of the source / drain lines is stabilized in a readable state, and as a result, reading at high speed is hindered. Have been.
[0015]
A first object of the present invention is to provide a nonvolatile semiconductor memory device of a type in which a source / drain region reads data through a column line which is electrically connected in common by two adjacent transistor columns. An object of the present invention is to provide a data reading method capable of reading data.
A second object of the present invention is to provide a non-volatile semiconductor memory device having a configuration enabling high-speed and reliable data reading.
[0016]
[Means for Solving the Problems]
A nonvolatile semiconductor memory device according to the present invention achieves the second object, and is formed in a matrix on a semiconductor substrate, and is formed by stacking insulating materials including a non-conductive trap gate. A plurality of memory transistors each having a gate stack, a control gate on the gate stack, and first and second source / drain regions spaced apart below the gate stack; A plurality of word lines commonly connected to each other, the first source / drain region in each column, and the second source / drain region in another column adjacent to the first source / drain region. A plurality of column lines that electrically connect the drain region in common; a row selection unit that selects one of the plurality of word lines; and a column line selected from the plurality of column lines; Column selection means for applying a reference voltage to the selected column line and applying a read voltage to all other column lines, and in the row selected by the row selection means, the reference voltage is applied by the column selection means. Of the trap gate on the column line side to which the reference voltage is applied, for a memory transistor connected between the column line to which the reference voltage is applied and the column line to which the read voltage is applied adjacent to the column line. The storage data corresponding to the charges accumulated in the local area is read from the column line to which the read voltage is applied.
[0017]
A method for reading data of a nonvolatile semiconductor memory device according to the present invention achieves the first object, in which an insulating material including a non-conductive trap gate formed in a matrix on a semiconductor substrate is laminated. And a plurality of memory transistors each having a gate stack, a control gate on the gate stack, and first and second source / drain regions separated below the gate stack. A plurality of word lines that commonly connect control gates for each row, the first source / drain regions in each column, and the word lines in other columns adjacent to the first source / drain regions. A plurality of column lines electrically connecting the two source / drain regions electrically in common, the method comprising: A first step of selecting a column line from among the plurality of column lines, applying a reference voltage, and applying a read voltage to all other column lines, and selecting one of the plurality of word lines. A second step of applying a read gate voltage; and in the row selected by the row selection means, a column line to which a reference voltage is applied by the column selection means, and the read voltage is applied adjacent to the column line. A memory cell connected between the column line and the column line to which the read voltage is applied, the storage data corresponding to the charge accumulated in the local portion of the trap gate on the column line side to which the reference voltage is applied; And a third step of reading from the first row. The first to third steps are repeated while shifting the selected column line one column at a time in a read cycle in the same direction.
[0018]
In the nonvolatile semiconductor memory device according to the present invention, all of the first source / drain regions of one transistor row in the column direction in the memory cell array and the first source / drain regions are provided as in the so-called virtual ground array structure. One column line is commonly connected to all of the second source / drain regions in another column adjacent to the side, and are collectively biased via this column line.
The row selecting means selects one of the plurality of word lines.
The column line selecting means selects a column line from a plurality of column lines, applies a reference voltage to the selected column line, and applies a read voltage to all other column lines.
Thereby, in the row selected by the row selecting means, the memory transistor connected between the column line to which the reference voltage is applied by the column selecting means and the column line adjacent to the column line and to which the read voltage is applied. Is read out. At this time, stored data corresponding to the electric charge accumulated in the local portion of the trap gate on the column line side to which the reference voltage is applied is read from the column line to which the read voltage is applied.
In this read control, when a column line other than the column line to which the reference voltage is applied includes a column line that is not adjacent to the column line to which the reference voltage is applied, the read voltage is also applied to the column line. . Therefore, no voltage is applied between the source and the drain of the memory transistor to be read out on both sides thereof. Accordingly, the non-read target memory transistor does not turn on, and the current caused by the non-read target memory transistor is adjacent to the column line to which the reference voltage is applied, and is applied to the column line from which data is to be read. It does not flow accidentally.
[0019]
In the data read method of the present invention, the above-described read control is repeated while shifting the selected column line one column at a time in a read cycle in the same direction.
Therefore, the relative potential relationship between the column line to which the reference voltage is applied and the column line to which the read voltage is applied is maintained in any of the repeated read cycles. As a result, the non-read target memory transistor does not turn on, and the current caused by the non-read target memory transistor is adjacent to the column line to which the reference voltage is applied, and is applied to the column line from which data is to be read. It does not flow accidentally.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a nonvolatile semiconductor memory device and a data reading method thereof according to the present invention will be described with reference to the drawings, taking a nonvolatile memory having a MONOS cell transistor having an N-type channel conductivity as an example.
In the preferred embodiment described below, a column line is selected every four columns and a reference voltage is applied, but it is not always necessary to select every four columns. The present invention can be similarly applied to the case where a column line is selected between four or more unselected columns, the selected column line is set to a reference voltage, and the unselected column lines are set to a read voltage. The present invention is also applicable to a case where only a specific column of the cell array is selected, the selected column is set as a reference voltage, and the other columns are set as read voltages. Further, the present invention can be similarly applied to a case where a plurality of read modes in which the number of column lines selected in one read is different are mixed.
[0021]
FIG. 1 is a schematic configuration diagram of the nonvolatile memory according to the present embodiment. FIG. 2A is a bird's-eye view of a MONOS type cell transistor capable of storing two bits as viewed from a cross section in the row direction, and FIG. 2B is an equivalent circuit diagram of the cell transistor.
1 of the nonvolatile memory 1 is roughly divided into a memory cell array 2 in which a plurality of cell transistors M are arranged in a matrix, and a page buffer group 3 as a read circuit for reading data from the memory cell array 2. . The page buffer group 3 has a function of selecting a column in addition to a function as a readout circuit, and constitutes an embodiment of the “column selecting means” of the present invention.
[0022]
In the cell transistor M shown in FIG. 2A, an element isolation insulating layer 21 is formed on a surface of a silicon substrate 20 (more specifically, a P well). The element isolation insulating layer 21 is formed by a LOCOS method in the illustrated example. Source / drain regions SD1 and SD2 are formed apart from each other on the surface of the substrate between the element isolation insulating layers 21. The source / drain regions SD1 and SD2 are connected at the lower surface of the element isolation insulating film 21, and are shared by adjacent cell transistors. The substrate surface portion where the source / drain regions SD1 and SD2 are not formed is the channel forming region 22. An ONO film 23 is formed on the channel forming region 22, on the ends of the source / drain regions SD1 and SD2 on both sides thereof, and on the element isolation insulating layer 21, and has a word line WL having a function of a control gate which is long in the row direction. Are formed on the ONO film 23.
[0023]
The ONO film 23 has a structure in which a first insulating film 23A, a second insulating film 23B functioning as a trap gate TG, and a third insulating film 23C are sequentially stacked from the substrate side. Note that these insulating films 23A to 23C are difficult to be called complete insulating films because electric charges are moved by an electric field applied at the time of writing or erasing, but are used as insulating films in a steady state such as charge retention. Since it functions, it is called an insulating film for convenience.
The first insulating film 23A is made of silicon oxide formed by thermally oxidizing the substrate surface, or silicon oxynitride (oxnitride) formed by nitriding silicon oxide.
The second insulating film 23B as the trump gate TG is made of silicon nitride, and can hold charges in a bulk trap in silicon nitride or a deep trap formed near a boundary with another insulating film.
The third insulating film 23C is made of, for example, silicon oxide formed by thermally oxidizing the surface of the second insulating film 23B, or HTO (High Temperature Chemical Vapor Deposited Oxide) formed by CVD.
With the above configuration, the cell transistor M has a trap-gate TG embedded in an insulating film such as a silicon oxide film, and has a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure as a whole.
[0024]
The MONOS type cell transistor utilizes the difference in band gap between the silicon nitride film and the silicon oxide film (that is, the insulating films 23B and 23A and the insulating films 23B and 23C) to form the trap gate TG (the second insulating film). 23B) can be trapped and held. The trap gate TG is made of a non-conductive material such as an insulator or a dielectric, and the charge injected into the trap gate TG can hardly move in the trap gate TG. Therefore, it is possible to distinguish between a case where charges are injected near the first source / drain region SD1 and a case where charges are injected near the second source / drain region SD2, and record 2-bit data. can do.
[0025]
Note that the structure of the cell transistor M illustrated in FIG. 2A is an example and is not limited thereto. For example, the element isolation insulating layer 21 may be one in which an insulating film is embedded in a trench formed by, for example, an STI (Shallow Trench Isolation) method. If there is a sufficiently thick interlayer insulating film between the word line WL and the source / drain region SD1 or SD2, the element isolation insulating layer 21 itself can be omitted. In addition, a non-MONOS-type trap gate may have a non-conductive trap gate. Further, the channel conductivity type of the cell transistor M may be P-type.
[0026]
As described above, the trap gate TG is non-conductive, and an equivalent circuit of a cell transistor that stores 2-bit data is as shown in FIG. That is, separate memory transistors are formed in the first trap gate region TSD1 near the first source / drain region SD1 and the second trap gate region TSD2 near the second source / drain region SD2, The portion where charge injection is not performed during that period is equivalent to a normal MOS transistor. In a read or program (write) operation to be described later, one of the first and second source / drain regions SD1 and SD2 is used as a source region or a drain region. Are referred to as a source / drain region SD1 and a second source / drain region SD2.
[0027]
Although the memory cell array 2 shown in FIG. 1 shows a cell group of 2 rows × 8 columns for convenience, the illustrated configuration is repeated in an actual memory cell array.
In FIG. 1, two word lines WL0 and WL1 extending in the row direction are arranged, and nine source / drain lines SDL1 to SDL9 crossing the word lines and extending in the column direction are arranged. The source / drain lines constitute an embodiment of a “column line” in the present invention.
The control gates of the cell transistors M1 to M8 are connected to the word line WL0. The source and drain terminals of the cell transistors M1 to M8 are commonly connected to adjacent cell transistors, and the source and drain lines SDL1 to SDL9 are commonly connected to the source and drain terminals. Similarly, the control gates of the cell transistors M11 to M18 are respectively connected to the word line WL1, and the source and drain terminals of these cell transistors are also connected to the adjacent cell transistor in common, and the common source and drain lines SDL1 to SDL9 are connected thereto. Is connected. Therefore, in all the cell transistors, the control gate is connected to the word line, and the source and drain terminals are connected to the source and drain lines, respectively.
A row decoder (R.DEC) 4 is connected to the word lines WL0 and WL1 as an embodiment of "row selecting means" for applying a read gate voltage or the like.
[0028]
The odd-numbered source / drain lines SDL1, SDL3,..., SDL9 are connected to the odd-numbered page buffers P / B1, P / B3,. Is done. Also, the even-numbered source / drain lines SDL2, SDL4,..., SDL8 are connected to the even-numbered page buffers P / B2, P / B4,. Connected respectively. These page buffers P / B1 to P / B9 apply a read voltage to apply a read voltage to a connected source / drain line in accordance with a 2-bit control signal (scanA0, scanA1) so as to function as a bit line. One of a state (BL) and a reference voltage state (0 V) to which 0 V as a read reference voltage is applied. Each of the page buffers P / B1 to P / B9 is connected to a line for supplying a read voltage RBiasV (for example, 1 V) and a line for supplying a ground potential GND (0 V) as a reference voltage.
[0029]
In order to control the read voltage state (BL) and the reference voltage state (0 V), four signal lines such as a control signal scanA0, its inverted signal scanA0X, a control signal scanA1, and its inverted signal scanA1X are provided. ing. For these four signal lines, the page buffers P / B1 to P / B9 are connected by the same combination of lines for every four. That is, the page buffers P / B1, P / B5 and P / B9 are connected to the lines of the signals scanA0X and scanA1X, the page buffers P / B2 and P / B6 are connected to the lines of the signals scanA0 and scanA1X, and the page buffers P / B B3 and P / B7 are connected to wirings of signals scanA0X and scanA1, and page buffers P / B4 and P / B8 are connected to wirings of signals scanA0 and scanA1.
Further, a signal LD for giving a read timing when the applied voltage is stabilized to the page buffers P / B1 to P / B9, and the read data are transferred to the odd-numbered page buffer group and the even-numbered page buffer group, respectively. The wiring is connected so as to be able to supply the clock φ to be shifted.
[0030]
Next, an outline of each operation of programming, erasing, and reading of the nonvolatile memory capable of storing two bits will be described, and then the reading operation will be described in detail including control by the reading circuit.
FIGS. 3A to 3E are diagrams for explaining respective operations of programming, erasing, and reading. The black circles in the figure indicate a set of accumulated electrons. Hereinafter, the voltage applied to the first source / drain region SD1 is applied to V (SD1), the voltage applied to the second source / drain region SD2 is applied to V (SD2), and the control gate CG (word line WL) is applied. The voltage applied is Vg.
In the data programming (writing), as shown in FIG. 3A, for example, Vg = 10 V, V (SD1) = 0 V, V (SD2) = 6 V, and the vicinity of the second source / drain region SD2 Is injected into the second trap gate region TSD2 close to the second source / drain region SD2.
[0031]
At the time of data erasure, as shown in FIG. 3B, Vg = −6 V is applied to the control gate CG, and 5 V is applied to one or both of the two source / drain regions SD 1 and SD 2, and an FN (Fowler-Nordheim) tunnel is applied. Electrons are extracted from the trap gate TG by utilizing the phenomenon. At the same time, the charge in the trap gate TG is neutralized by injecting hot holes generated near the source / drain regions SD1 and / or SD2 to which 5V is applied into the trap gate TG. FIG. 3B shows a case of one-sided erasing of the second trap gate region TSD2. At this time, the other first source / drain / region SD1 to which 5 V is not applied is in an electrically open state (open).
[0032]
At the time of data reading, a voltage having a voltage magnitude opposite to that at the time of programming is applied between the first and second source / drain regions SD1 and SD2. FIGS. 3C and 3D show that, when detecting whether electrons are trapped in the second trap gate region TSD2, FIG. 3E shows that electrons are present in the first trap gate region TSD1. The case where it is detected whether or not is trapped is shown.
To read the state of the second trap gate region TSD2, for example, Vg = 3V, V (SD1) = 1.0V, and V (SD2) = 0V are applied. Here, as shown in FIG. 3C, when electrons exist in the second trap gate region TSD2 near the second source / drain region SD2 ("0" data storage state), the channel below the gate becomes the second channel. The channel current does not flow without connecting to the source / drain region SD2 of No. 2. Conversely, as shown in FIG. 3D, if there is no electron in the second trap gate region TSD2 near the second source / drain region SD2 ("1" data storage state), the channel becomes the second. A connection channel current flows to the source / drain region SD2. Therefore, whether or not electrons are accumulated in the second trap gate region TSD2 can be detected by turning on and off the cell transistor, that is, by detecting the presence or absence of a channel current. The presence or absence of the channel current can be detected, for example, by examining a change in the potential of the second source / drain region SD2 to which a read voltage of 1.0 V is applied.
[0033]
When reading the state of the first trap gate region TSD1, as shown in FIG. 3E, Vg = 3V, V (SD1) = 0V, and V (SD2) = 1.0V, the first and second states are set. The voltage is switched between the source and drain regions as shown in FIGS. 3C and 3D. When electrons are not accumulated in the first trap gate region TSD1, even if electrons exist in the second trap gate region TSD2, the channel becomes the same state as the transistor whose pinch is turned off, and the second source A channel current flows due to a depletion layer extending between the drain region SD2 and the substrate. On the other hand, although not particularly shown, when electrons are accumulated in the first trap gate region TSD1, as in the case of FIG. 3C, the channel is not connected and no channel current flows. In such a voltage applied state, it is determined whether or not electrons are accumulated in the first trap gate region TSD1 near the first source / drain region SD1 functioning as a source. Can be detected regardless of the presence of electrons.
[0034]
FIGS. 4A to 4D are diagrams showing a state where 2-bit data is recorded in the nonvolatile memory. In the figure, black circles indicate a set of accumulated electrons.
FIG. 4A shows data “11” in a state where electrons are not captured in any of the first and second trap gate regions TSD1 and TSD2. FIG. 4B shows data “01” in a state where electrons are captured in the second trap gate region TSD2. FIG. 4C shows data “00” in a state where electrons are captured in both the first and second trap gate regions TSD1 and TSD2, and FIG. 4D shows the first data. Data “10” is shown in a state where electrons are captured in the trap gate region TSD1.
[0035]
Next, the read operation will be described in more detail.
The read gate voltage Vg (for example, 3.0 V) is applied to the gate of the cell transistor M by the row decoder 4. The read buffer RBiasV (for example, 1....) Is applied to one of two source / drain lines SDLi (i = 1, 2,..., 9) connected to both sides of the cell transistor M by the page buffer shown in FIG. 0V), and a reference voltage (ground potential: 0 V) is applied to the other (SDLi + 1 or SDLi-1). Then, the stored data is read by the page buffer P / Bi connected thereto via the source / drain line SDLi to which the read voltage is applied.
As described above, each of the page buffers P / B1 to P / B9 has a function of appropriately applying the read voltage RBiasV or the reference voltage (0 V) to the connected source / drain lines, and the read voltage RBiasV and the reference voltage (0 V). It has a function of reading and holding stored data of a cell transistor connected between a source and a drain in response to a signal LD. Then, the held stored data is output to an output data bus (not shown) under the control of the clock φ.
[0036]
In the memory cell array 2 shown in FIG. 1, eight cell transistors M1 to M8 are connected to each word line, for example, the word line WL0. Therefore, assuming that the word line WL0 is selected, a total of 16 bits of stored data can be read. Further, the page buffer is divided into two systems of an odd-numbered stage and an even-numbered stage, and the page buffers are connected to each other so that data can be shifted in each system. Therefore, as for the 16-bit stored data in the eight cell transistors, eight bits are read out for each system, held, and output from the last page buffer after the shift. In FIG. 1, 8-bit data Dout0 is output from the last page buffer P / B9 in the odd-numbered stage, and 8-bit data Dout1 is output from the last page buffer P / B8 in the even-numbered stage.
However, as described later, when one word line is selected, only 4-bit data can be read at the same time by controlling each source / drain line. Therefore, in practice, 8-bit data is read in two cycles, and this is repeated twice, so that 16-bit data of eight cell transistors is read in four cycles in total.
[0037]
Note that the number of cell transistors connected to one word line is not limited to eight. Preferably, as in the example shown in FIG. 1, eight cell transistors constitute a cell transistor unit. The example of FIG. 1 mainly shows the first cell transistor unit UNIT1. A second cell transistor UNIT2 having a similar configuration is arranged on the output side (the right side in FIG. 1), and similarly, a required number of cell transistor units are arranged sequentially in the row direction. The source / drain line SDL9 and the page buffer P / B9 shown in FIG. 1 are shared with the first source / drain line and the page buffer of the second cell transistor unit UNIT2. As described above, nine source / drain lines and nine page buffers are allocated to each cell transistor unit functionally, and the source / drain line and the page buffer located at the boundary between the units are two adjacent ones. Since the units are shared among the units, if the total number of units is N, the actual number of source / drain lines and page buffers is 8N + 1.
[0038]
As described above, in the read operation of this embodiment, all the bit data stored in the memory cell group in one row are read by four read operations. Hereinafter, these four read operations are referred to as a read cycle (1), a read cycle (2), a read cycle (3), and a read cycle (4). Thereafter, the first page read for reading the 8-bit data is executed by the read cycles (1) and (2), and the second page read for reading the other 8-bit data is executed by the read cycles (3) and (4). It is assumed that page read is executed.
[0039]
FIG. 5A is a chart showing voltage states of source / drain lines in read cycles (1) to (4), and FIG. 5B is a chart showing transistors from which data is read.
FIGS. 6A and 6B are diagrams for explaining the operation of the memory cell array during the first page read, and FIGS. 7A and 7B are diagrams illustrating the operation of the memory cell array during the second page read. It is a figure explaining an operation.
In the read cycle (1), as shown in FIG. 6A, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = 0 V, BL, BL, BL, 0 V, BL, BL, BL, 0V state. Here, “0V” means a reference voltage state, and “BL” means a read voltage state. As a result, the presence / absence of a current corresponding to the charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 6A is determined by the page buffers P / B2, P / B4, P / B6, and P / B. Detected by B8. That is, in the cell transistors M1, M4, M5, and M8, the data D1 (SD1), D4 (SD2), D5 (SD1), and D8 (SD2) on the source / drain line side in the reference voltage state (0 V) are respectively stored in the page. The data is read and held by buffers P / B2, P / B4, P / B6, and P / B8. In the read cycle (1), the stored data is read via the even-numbered source / drain lines SDL2, SDL4, SDL6, and SDL8 which have been brought to the read voltage state (BL), but the odd-numbered source / drain The read voltage state (BL) is also set to the source / drain lines SDL3 and SLD7 to which the reference voltage state (0 V) is not applied. Therefore, the potentials of the even-numbered source / drain lines do not change in accordance with the cell transistors at both ends of the source / drain lines SDL3 and SLD7, that is, the storage data of M2 and M3 and M6 and M7.
[0040]
In the read cycle (2), as shown in FIG. 6B, the states of the source / drain lines SDL1 to SDL9 are shifted one by one (rightward in the drawing) from the state in the read cycle (1). You. That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = BL, 0V, BL, BL, BL, 0V, BL, BL, BL by the respective page buffers. As a result, the presence / absence of a current corresponding to the electric charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 6B is determined by the page buffers P / B1, P / B3, P / B5, and P / B. Detected by B7. That is, in the cell transistors M1, M2, M5, and M6, the data D1 (SD2), D2 (SD1), D5 (SD2), and D6 (SD1) on the source / drain line side in the reference voltage state (0 V) are respectively paged. The data is read and held by the buffers P / B1, P / B3, P / B5, and P / B7. In the read cycle (2), the storage data is read via the odd-numbered source / drain lines SDL1, SDL3, SDL5, and SDL7 which have been brought into the read voltage state (BL), but the even-numbered source / drain lines are read. The read voltage state (BL) is also set to the source / drain lines SDL4 and SLD8 (and the last source / drain line SDL9) to which the reference voltage state (0 V) is not applied. Therefore, the potentials of the odd-numbered source / drain lines do not fluctuate in accordance with the cell transistors at both ends of the source / drain lines SDL4 and SLD8, that is, M3 and M4, and M7 and M8.
[0041]
By the read cycles (1) and (2), the stored data of one page consisting of a total of 8 bits is read and held in the eight page buffers P / B1 to P / B8, whereby the first page data is stored. The read ends. Thereafter, by appropriately selecting a page buffer, the held data is output to an output bus (not shown). By using a plurality of output data buses, it is possible to output a plurality of data simultaneously.
[0042]
Next, a second page read operation is performed. The second page read operation is executed by read cycles (3) and (4).
In the read cycle (3), as shown in FIG. 7A, the states of the source / drain lines SDL1 to SDL9 are shifted one by one more than in the read cycle (2). That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = BL, BL, 0V, BL, BL, BL, 0V, BL, BL by the respective page buffers. As a result, the presence / absence of a current corresponding to the electric charge stored in the portion of the memory cell corresponding to the bit indicated by the circle in FIG. 7A is determined by the page buffers P / B2, P / B4, P / B6, and P / B. Detected by B8. That is, in the cell transistors M2, M3, M6, and M7, the data D2 (SD2), D3 (SD1), D6 (SD2), and D7 (SD1) on the source / drain line side in the reference voltage state (0 V) are respectively paged. The data is read out and held by buffers P / B2, P / B4, P / B6, and P / B8. In the read cycle (3), the storage data is read via the even-numbered source / drain lines SDL2, SDL4, SDL6, and SDL8 which have been brought into the read voltage state (BL), but the odd-numbered source / drain The read voltage state (BL) is set to the source / drain lines SLD1, SDL5, and SLD9 to which the reference voltage state (0 V) is not applied. Therefore, the potentials of the even-numbered source / drain lines do not change according to the data stored in the cell transistors M1, M4, M5 and M8.
[0043]
In the read cycle (4), as shown in FIG. 7B, the states of the source / drain lines SDL1 to SDL9 are further shifted one by one as compared with the state in the read cycle (3). That is, the source / drain lines SDL1 to SDL9 are set to SDL1 to SDL9 = BL, BL, BL, 0V, BL, BL, BL, 0V, BL by the respective page buffers. As a result, the presence / absence of a current corresponding to the charge stored in the portion corresponding to the bit indicated by the circle of the memory cell in FIG. 7B is determined by the page buffers P / B3, P / B5, P / B7, P / Detected by B9. That is, in the cell transistors M3, M4, M7, and M8, the data D3 (SD2), D4 (SD1), D7 (SD2), and D8 (SD1) on the source / drain line side in the reference voltage state (0 V) are paged, respectively. The data is read and held by buffers P / B3, P / B5, P / B7, and P / B9. In the read cycle (4), storage data is read through the odd-numbered source / drain lines SDL3, SDL5, SDL7, and SDL9 that have been brought into the read voltage state (BL), but the even-numbered source / drain lines are read. The read voltage state (BL) is set to the source / drain lines SDL2 and SLD6 to which the reference voltage state (0 V) is not applied. Therefore, the potentials of the odd-numbered source / drain lines do not fluctuate according to the cell transistors at both ends of the source / drain lines SDL2 and SLD6, that is, M1 and M2 and M5 and M6.
[0044]
By the read cycles (3) and (4), one page of stored data consisting of a total of 8 bits is read and held in the eight page buffers P / B2 to P / B9, whereby the second page The read ends. Thereafter, by appropriately selecting a page buffer, the held data is output to an output bus (not shown). By using a plurality of output data buses, it is possible to output a plurality of data simultaneously.
[0045]
In the above four types of read cycles (1) to (4), a set of (0V, BL, BL, BL) states that are repeatedly set to four adjacent source / drain lines is one for each read cycle. It is understood that the state is shifted to the right by each state. Among the above four source / drain lines, there are three source / drain lines in a read voltage state (BL), but since reading is actually performed via two of the two at both ends, 2-bit storage data Are read at the same time. In addition, since the read voltage state (BL) is also set on the source / drain line between the two source / drain lines where reading is actually performed, the cells on both sides are not turned on. To prevent fluctuation of read data.
[0046]
The order of the four types of read cycles is as follows from (1) → (2) → (3) → (4).
(1) → (2) → (4) → (3),
(2) → (1) → (3) → (4),
(1) → (4) → (2) → (3),
(1) → (4) → (3) → (2),
(4) → (1) → (2) → (3),
(4) → (1) → (3) → (2)
May be changed.
In any case, at least four source / drain lines are set to the read voltage state (BL) for each unit in the odd-numbered source / drain lines, and similarly, for each unit in the odd-numbered source / drain lines. , At least four source / drain lines are set to the read voltage state (BL). In any of the above modifications, the set of (0V, BL, BL, BL) states set in units of four source / drain lines is appropriately moved, so that all the cell transistors are changed. Can be read.
[0047]
FIG. 8 shows a circuit example of a page buffer used in the present embodiment. FIGS. 9A to 9D show timing charts of various control signals.
The page buffer P / Bi shown in FIG. 8 is a page buffer coupled to the source / drain line SDLi at the ith position. As described above, the page buffer divides one row into four parts and reads the data. Each page buffer is divided into four sectors by scan addresses scanA0 to scanA1, that is, a first sector composed of every fourth source / drain line group and a second sector composed of a source / drain line group adjacent to one of the first sectors. One of a sector, a third sector including a source / drain line group adjacent to one side of the second sector, and a fourth sector including a source / drain line group adjacent to one side of the third sector is selected. I do.
[0048]
The page buffer P / Bi illustrated in FIG. 8 includes five NMOS transistors N1 to N5, an inverter 30, a two-input AND gate 31, and a shift register (S / R) 32.
The transistor N1 is connected to the input terminal of the held data of the shift register 32. The transistor N1 is turned on in response to a signal LD for controlling data retention, and inputs the determined data PBouti of the source / drain lines to the shift register 32. The signal LD simultaneously instructs access in the next read cycle and start of potential determination (hereinafter, this series of operations is referred to as scanning).
The shift register 32 is provided for each page buffer, but as a whole, the shift registers are connected in series. That is, the data input terminal (Din) of the shift register 32 shown in FIG. 8 is connected to the data output terminal (Q) of the preceding shift register (not shown), and the data output terminal (Q) of the shift register 32 shown in FIG. Is connected to a data input terminal (Din) of a shift register of a latter stage not shown.
[0049]
Transistors N2 and N3 are connected in parallel between the holding node 33 for the determined data PBouti and the i-th source / drain line SDLi. A transistor N4 is connected between the i-th source / drain line SDLi and a supply line of the ground potential GND as a reference voltage, and a transistor N5 is connected between the i-th source / drain line SDLi and a supply line of the read voltage RBiasV. Is connected. An AND gate 31 and an inverter 30 are connected between four address lines for supplying scan addresses scanA0 to scanA1 and the gate of the transistor N5. The two inputs of the AND gate 31 are connected to any two of the four address lines in a different combination for each sector. That is, the connection portion surrounded by the broken line in FIG. 8 differs for each sector, that is, for each of the four page buffers as shown in FIG. FIG. 8 illustrates a case where the scan addresses are connected to scan addresses scanA0 and scanA1.
[0050]
A node 34 at the connection point between the AND gate 31 and the inverter 30 is connected to the gate of the transistor N4. The node 34 is further connected to the gate of the transistor N3 of the preceding page buffer P / Bi-1 and the gate of the transistor N2 of the subsequent page buffer P / Bi + 1 (not shown). In FIG. 8, the potential of the node 34 is represented by Bi. The purpose of transmitting the potential Bi to the page buffers on both sides is that when the potential Bi is at a high level and the transistor N4 is turned on and the source / drain line SDLi is in the reference potential state (0 V), the transistor N2 in the page buffer on both sides is used. Alternatively, one of N3 is turned on, and the data of the corresponding source / drain line SDLi-1 or SDLi + 1 is transmitted to the node 33, and is determined as read data.
The interconnection relationship between the page buffers is the same in the page buffers in the preceding and subsequent stages. Therefore, the gate of the transistor N2 shown in FIG. 8 is connected so that the potential Bi-1 of the node 34 of the preceding page buffer can be applied, and the gate of the transistor N3 shown in FIG. 8 is connected to the potential of the node 34 of the following page buffer. Bi + 1 is connected so as to be able to be applied.
Note that the signal of the potential Bi in the page buffer of the selected column, that is, the column supplying the reference potential GND (= 0 V) corresponds to the “first control signal” of the present invention, and supplies the unselected column, that is, the read voltage RBiasV. The signal of the potential Bi in the column page buffer corresponds to the “second control signal” of the present invention.
[0051]
In the initial state, since the signal LD holds the low level “L”, the transistors N1 are turned off in all the page buffers.
When the scan address transits at time t1 shown in FIG. 9A, one of the first to fourth sectors is selected to the reference voltage state (0 V) according to the address, and the remaining three sectors are set to the read voltage state. (BL) is selected. Assuming that the page buffer P / Bi shown in FIG. 8 is set to the reference voltage state (0 V), the potential Bi of the output node 34 of the AND gate 31 becomes high level "H", the transistor N4 is turned on, and the transistor N5 Is turned off. Therefore, the ground potential (GND: 0 V) is transmitted to the source / drain line SDLi.
At this time, in the two page buffers on both sides, the transistor N4 is turned off and the transistor N5 is turned on according to the input scan address, and the read voltage RBiasV is transmitted to the corresponding source / drain lines SDLi-1 and SDLi + 1. At the same time, the transistor N2 or N3 is turned on in each of the adjacent page buffers by the voltage Bi transmitted from the page buffer P / Bi in FIG. 8 in which the reference voltage state (0 V) is selected, and the node 33 is connected to the source Connected to drain line.
[0052]
When the word line potential of the selected row rises after the transition of the scan address, the storage bit data on the source side of two adjacent cell transistors using the source / drain line SDLi as a common source line shown in FIG. In the case of "data", a cell current flows through a source / drain line of the two adjacent source / drain lines SDLi-1 and SDLi + 1 to which a cell transistor storing the "0" data is connected, and the potential of the node 33 Fluctuates. The time when this potential is sufficiently stabilized including the variation is defined as the access time t. _AA Then, as shown in FIG. 9B, the access time t _AA At time t2 after the above, the pulse of the signal LD rises. As a result, the transistor N1 is turned on, and the fixed data PBouti-1 and PBouti + 1 at the node 33 are binary data in which "0" indicates that there is a potential change in the node 33 and "1" indicates that there is no potential change in the node 33. Is taken into the shift register 32. When the pulse of the signal LD falls, the transistor N1 turns off, and the next address transition starts at time t3. During the next access time, the shift register 32 performs data shift under the control of the clock shown in FIG.
This series of operations is performed simultaneously in two of the four sectors, and one read cycle is completed.
[0053]
Then, after shifting the selection of the sector by one source / drain line, the next read cycle is executed by the same procedure, whereby 8-bit data is read by the first page read.
Similarly, by repeating the sector selection shift and the reading twice more, 8-bit data is read by the second page reading.
By the above-described page read, the output data Dout shown in FIG. 9D is sequentially discharged to one or a plurality of data buses for each quarter row.
[0054]
In the above page read, the access time t for setting the potential and determining the data is t _AA And the data shift and discharge times overlap, and the effective one read cycle time is (t _AA + Α). At this time, in this embodiment, of the source / drain lines between the source / drain lines from which data is read, one out of four source / drain lines which are not set to the reference voltage state (0 V) is set to the read voltage state (BL). ), The potential of the source / drain line from which data is read is quickly determined, and the access time t _AA Has the advantage of being shorter. As a result, high-speed and highly reliable page reading can be performed.
[0055]
In the above description, one out of four source / drain lines is held in the read voltage state (BL) in order to quickly determine the potential. This is a preferred embodiment because the source-drain voltage of the cell transistor that does not perform reading is set to 0V. However, in order to achieve the same purpose, it is not necessary to apply exactly the same voltage as the readout voltage RViasV to one out of four source / drain lines, and this applied voltage is applied to the cell transistor regardless of the presence or absence of the accumulated charge. Any voltage may be used as long as the voltage is close to the read voltage RViasV so that the voltage between the source and the drain is reduced to such an extent that does not turn on.
[0056]
【The invention's effect】
According to the present invention, in a nonvolatile semiconductor memory device of a type in which source / drain regions read data via column lines electrically connected in common by two adjacent transistor columns, data is read quickly and reliably. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a nonvolatile memory according to an embodiment.
FIG. 2A is a bird's-eye view of a MONOS type cell transistor capable of storing two bits as viewed from a cross section in a row direction, and FIG. 2B is an equivalent circuit diagram of the cell transistor.
FIGS. 3A to 3E are diagrams for explaining respective operations of programming, erasing, and reading.
FIGS. 4A to 4D are diagrams showing a state where 2-bit data in a nonvolatile memory is recorded.
FIG. 5A is a chart showing voltage states of source / drain lines in read cycles (1) to (4), and FIG. 5B is a chart showing transistors from which data is read.
FIGS. 6A and 6B are diagrams illustrating the operation of the memory cell array at the time of the first page read;
FIGS. 7A and 7B are diagrams illustrating the operation of the memory cell array at the time of the second page read.
FIG. 8 is a circuit diagram of a page buffer used in the embodiment of the present invention.
FIGS. 9A to 9D are timing charts of various control signals.
FIGS. 10A and 10B are diagrams illustrating an operation of a memory cell array in a first page read for reading first 8-bit data in a data read method described in Patent Document 2. FIG.
FIGS. 11A and 11B are diagrams illustrating the operation of a memory cell array at the time of a second page read for reading the next 8-bit data in the data read method described in Patent Document 2. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device, 2 ... Memory cell array, 3 ... Readout circuit as column selection means, 4 ... Row decoder as row selection means, 20 ... Semiconductor substrate or P well, 21 ... Element isolation insulating layer, 22 ... Channel formation region, 23 ONO film, 23A first insulating film, 23B second insulating film as trap gate TG, 23C third insulating film, 30 inverter, 31 AND gate, 32 shift Register, 33: Data determination node, 34: Node, M: Cell transistor, CG: Control gate, SD1, SD2: Source / drain region, SDL: Source / drain line as column line, WL: Word line, P / B ... page buffer, (BL) ... read voltage state, (0V) ... reference voltage state

Claims (6)

A gate stacked body formed in a matrix on a semiconductor substrate and formed by stacking insulating materials including a non-conductive trap gate, a control gate on the gate stacked body, and spaced apart below the gate stacked body A plurality of memory transistors each having first and second source / drain regions;
A plurality of word lines commonly connecting the control gates for each row;
A plurality of the first source / drain regions in each column and a plurality of the second source / drain regions in another column adjacent to the first source / drain region which are electrically connected in common. Column lines,
Row selection means for selecting one of the plurality of word lines;
A column selecting means for selecting a column line from among the plurality of column lines, applying a reference voltage to the selected column line, and applying a read voltage to all other column lines;
A memory transistor connected between a column line to which a reference voltage is applied by the column selection means and a column line adjacent to the column line and to which the read voltage is applied in a row selected by the row selection means. The non-volatile semiconductor memory device according to claim 1, wherein storage data corresponding to charges accumulated in a local portion of the trap gate on the column line side to which the reference voltage is applied is read from the column line to which the read voltage is applied. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said column selecting means selects a plurality of column lines separated by at least four columns among said plurality of column lines. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said column selecting means selects one column line for every four columns among said plurality of column lines. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said column selecting means shifts said selected column line one column at a time in each read cycle in the same direction. The column selection unit has a reference voltage node to which the reference voltage is supplied, a read voltage supply node to which the read voltage is supplied, and a data output node to receive read information,
The column selecting means,
Generating a first control signal, connecting the selected column line to the reference voltage node, interrupting a current path between the selected column line and the read voltage supply node, and selecting the selected column line according to the first control signal; Connecting a column line adjacent to the column line to the data output node;
A second control signal is generated, and a current path between a column line other than the selected column line and the reference voltage node is interrupted by the second control signal, and a column line other than the selected column is connected to the read voltage supply node. 2. The nonvolatile semiconductor memory according to claim 1, wherein a current path between the data output node and a column line that is not adjacent to the selected column line among column lines other than the selected column line is disconnected. apparatus. A gate stacked body formed in a matrix on a semiconductor substrate and formed by stacking insulating materials including a non-conductive trap gate, a control gate on the gate stacked body, and spaced apart below the gate stacked body A plurality of memory transistors each having first and second source / drain regions, a plurality of word lines commonly connecting the control gate for each row, and the first source / drain regions of each column And a plurality of column lines electrically connecting the second source / drain regions of another column adjacent to the first source / drain region side in common. A data reading method for a semiconductor memory device,
A first step of selecting a column line from among the plurality of column lines, applying a reference voltage, and applying a read voltage to all other column lines;
A second step of selecting one of the plurality of word lines and applying a read gate voltage;
A memory transistor connected between a column line to which a reference voltage is applied by the column selection means and a column line adjacent to the column line and to which the read voltage is applied in a row selected by the row selection means. A third step of reading stored data corresponding to charges accumulated in the local portion of the trap gate on the column line side to which the reference voltage has been applied, from the column line to which the read voltage has been applied,
A data reading method for a nonvolatile semiconductor memory device, wherein the first to third steps are repeated while shifting the selected column line one column at a time in a read cycle in the same direction.

Images