JP2002271289A - Transmission path testing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission path testing circuit which prepares two reception data, having a phase difference in proportion to the number of bits of frame bits and switches the two reception data according to a switching signal by a reception side frame pulse and a transmission side frame pulse, so that a circuit scale can be reduced. SOLUTION: A transmission path test circuit has a loop circuit for carrying out a transmission path test in a multiplexing transmitter for multiplexing a plurality of transmission signals to transmit. The loop circuit prepares two reception data, having a phase difference in proportion to the number of bits of frame bits and switches the two reception data, according to a switching signal by a reception side frame pulse and a transmission side frame pulse, and a loop is constituted in a state with the frame bits being passed for transmission and reception as they are, even for any phase difference between transmission and reception.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission line test circuit for performing a transmission line test in a multiplex transmission apparatus for multiplexing a plurality of transmission signals and transmitting the multiplexed transmission signal. The present invention relates to a transmission path test circuit that can significantly reduce the circuit scale even when the frame phases of received data and transmitted data are not always constant.

[0002]

2. Description of the Related Art Generally, in a multiplex transmission apparatus for multiplexing and transmitting a plurality of transmission signals, a transmission path test circuit for testing a transmission path using a loop circuit or the like is known. FIG. 8 is a configuration diagram of a transmission path test circuit in the multiplex transmission apparatus. As shown in FIG. 8, in the transmission path test circuit, a test signal generation unit 1 and a detection unit 3 are provided in a first device, and the first
Loop device connected to the second device via transmission line L
The circuit 2 is provided, and the PN pattern generated by the test signal generator 1 in the first device is inserted into the main signal and output to the transmission line L, and is looped back by the loop circuit 2 in the second device. The detecting unit 3 of the first device acquires a PN pattern from the main signal returned via the transmission line L, and performs an error check based on the acquired result. Next, a transmission path test circuit in the case where information such as alarm information is included in the transmission / reception frame bits will be described with reference to FIG. Here, if information such as alarm information is included in the transmission and reception frame bits, even if Loop is set during the test,
It is desired that the above-mentioned frame bits be monitored as usual between devices. As shown in FIG. 9, the transmission path test circuit includes a test signal generator 1 and a first
Frame INS unit 4, first frame DET unit 5, and detection unit 3
The second device connected to the first device via the transmission line L is provided with a second frame DET unit 6, a loop circuit 2, and a second frame INS unit 7, and the first device is connected to the first device. On the transmitting side of the device, the PN pattern generated by the test signal generator 1 is inserted into the main signal portion other than the frame bits, and the first frame INS unit 4 adds the frame bits to the main signal portion. The main signal output to the transmission line L and returned from the transmission line L by the loop circuit 2 from the transmission line L is returned to the main signal after the first frame DET unit 5 establishes frame synchronization. PN at detector 3
A pattern is obtained, and an error check is performed based on the obtained result. Then, in the second device, the signal from the transmission line L is transmitted to the second frame DET.
The unit 6 synchronizes the frame, the received data is shifted by the loop circuit 2 so as to match the received data with the frame phase of the transmitted data (the position of the frame bit matches), and the position other than the frame bit position of the transmitted data is shifted. The data part is replaced with a data part other than the frame bit position of the received data, and the second frame INS unit 7 adds a frame bit and transmits the data to the transmission path L (FIG. 1).
0).

Here, in the loop circuit 2, it is sufficient that the frame phase of the received data and the frame of the transmitted data always have a fixed relationship. Is not always constant. Therefore, the configuration of the loop circuit 2 is as shown in FIG. 11 in order to cope with the phase shift. FIG. 11 is a configuration diagram of a conventional Loop circuit 2. As shown in FIG. 11, the Loop circuit 2 includes an n-stage shift circuit 8 to which received data is input, a switching unit 9 connected to the n-stage shift circuit 8, a reception frame pulse and a transmission frame pulse (see FIG. 12), and a phase difference detection circuit 10 connected to the switching unit 9;
The first switch 11 that receives the transmission frame pulse and the transmission data and is connected to the switching unit 9
And a second switch 12 to which the transmission data and the Loop control signal are input and connected to the first switch 11. The operation of the loop circuit will be described. The n-stage shift circuit 8 is provided with a shift register group that allows the maximum phase difference between the frame phases of the reception data and the transmission data. Shift reception data corresponding to the phase difference is output. The shift reception data is input to the switching unit 9, and one shift reception data is selected by a select signal from the phase difference detection circuit 10. That is, the phase difference detection circuit 10 detects the phase difference of the transmission frame pulse with respect to the reception frame pulse, and in order to eliminate the phase difference (equalize the reception frame bit position and the transmission frame bit position). A select signal for obtaining shifted received data is generated. The first switch 11 is switched by the transmission frame pulse. When the transmission frame pulse is not output, the shift reception data from the switching unit 9 passes to the second switch 12, and the transmission frame pulse is output. When it is out, the transmission data (frame bit) passes through the second switch 12. Therefore, only the data portion of the frame bit of the transmission data is replaced with the reception data at that time. The second switch 12 is switched by the loop control signal. During a loop, the output from the first switch 11 is selected, and in a normal state, the transmission data is left as it is.

[0004]

However, in the above-mentioned conventional method, a loop can be performed regardless of the phase difference between transmission and reception, but a very large shift register circuit ( Since the n-stage shift circuit 8) is required, there is a problem that the circuit scale is increased. An object of the present invention is to solve such problems. That is, an object of the present invention is to prepare two reception data having a phase difference corresponding to the number of frame bits, and switch the two reception data with a switching signal based on a reception frame pulse and a transmission frame pulse. An object of the present invention is to provide a transmission line test circuit capable of greatly reducing the circuit scale.

[0005]

According to a first aspect of the present invention, there is provided a first apparatus for detecting a test signal generating unit, a first frame INS unit, and a first frame DET unit. And a second frame DET unit, a loop circuit, and a second unit connected to a second device connected to the first device via a transmission line.
The PN pattern generated by the test signal generator is inserted into the main signal portion other than the frame bits on the transmitting side of the first device, and the main frame INS is transmitted by the first frame INS unit. A frame bit is added to a signal portion and output to the transmission path. A signal from the transmission path is transmitted to the second frame DE in the second device.
The received data is shifted according to the frame phase of the transmission data so that the frame is synchronized in the T section and the position of the frame bit is matched in the Loop circuit, and the data portion other than the frame bit position of the transmission data is shifted. Is replaced with a data portion other than the frame bit position of the received data, a frame bit is added in the second frame INS unit, transmitted to the transmission path, and returned from the transmission path by the Loop circuit and returned. The main signal is
In the transmission path test circuit, after the frame is synchronized by the first frame DET unit on the receiving side in the first device, a PN pattern is obtained by the detection unit, and an error check is performed based on the obtained result. The Loop circuit has a phase difference equal to the number of bits of the frame bits.
Two pieces of received data are prepared, the two pieces of received data are switched by a switching signal based on the receiving side frame pulse and the transmitting side frame pulse, and a loop is performed with the frame bit passing through the transmitting side and the receiving side regardless of any phase difference between the transmitting and receiving sides. Is constituted.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a functional block diagram showing an embodiment of a transmission path test circuit according to the present invention. The basic configuration and operation of the transmission path test circuit according to the present invention are the same as those shown in FIG. That is, as shown in FIG. 1, the transmission path test circuit includes a first apparatus provided with a test signal generation unit 1, a first frame INS unit 4, a first frame DET unit 5, and a detection unit 3, A second frame DET is connected to a second device connected to the first device via a transmission line L.
A PN pattern generated by the test signal generation unit 1 in a main signal portion other than frame bits on the transmission side of the first device. Inserted into the first frame INS unit 4
The frame signal is added to the main signal portion and output to the transmission line L. On the receiving side, the main signal returned from the transmission line L by the loop circuit 2 ′ is
After the frame is synchronized by the first frame DET unit 5, the PN pattern is obtained by the detection unit 3 and an error check is performed based on the obtained result. In the second device, the signal from the transmission line L is frame-synchronized by the second frame DET unit 6, and the received data is converted to the frame phase of the transmitted data by the Loop circuit 2 '. The received data is shifted so as to match (the position of the frame bit coincides), the data portion other than the frame bit position of the transmission data is replaced with the data portion other than the frame bit position of the received data, and the second frame INS unit At 7, a frame bit is added and transmitted (see FIG. 10). In the transmission path test circuit shown in FIG. 1, only the configuration of the loop circuit 2 'is different, and therefore, the loop circuit 2' will be described below.

FIG. 2 is a block diagram of the loop circuit 2 '. As shown in FIG. 2, the Loop circuit 2 ′ includes a first shift circuit 13 to which first received data is input, and a first switch 14 connected to the first shift circuit 13.
A second shift circuit 15 connected to the first switch 14; a second switch 16 connected to the first switch 14 and the second shift circuit 15; Is input to the third shift circuit 17
And the third shift circuit 17 and the first switch 14
, A transmission frame pulse and the first reception frame pulse are input, and the first switch 14 and the third switch 1 are connected to the third switch 18.
A pulse check unit 19 connected to the second switch 1 and the second switch 1
And a fourth switch 21 connected to the second switch 16 while receiving the transmission frame pulse and the first transmission data. And a fifth switch 22 to which a loop control signal is input and connected to the fourth switch 21.

Next, the operation of each section in the loop circuit 2 'will be described. In FIG. 2, the first shift circuit 13 inputs and shifts the first received data, and the output is input to the first switch 14 as a first input. The first received data is also input to the first switch 14 as a second input, and is switched by a select signal from the pulse check unit 19.
The first reception data selected by the first switch 14 or the reception data shifted by one stage is input to the second switch 16 as a first input (second reception data), and at the same time, The received data input to the second shift circuit 15 and shifted in two stages by the second shift circuit 15 is input to the second switch 16 as a second input, and the received data switching signal generator It is switched by the select signal generated at 20. The third shift circuit 17 receives and shifts the first received frame pulse, inputs the first received frame pulse to the third switch 18 as a first input, and also inputs the second input to the third switch 18. The first received frame pulse is input as a signal, and is switched by a select signal from the pulse check unit 19. The pulse check unit 19 receives the first reception frame pulse and the transmission frame pulse and detects whether the two pulses overlap each other.
The result is output as a select signal for the first switch 14 and the third switch 18. Then, the second reception frame pulse selected by the third switch 18 is input to the reception data switching signal generation unit 20, and the transmission frame pulse is also input to the reception data switching signal generation unit 20. The received data switching signal generator 20 generates a select signal for the second switch 16 from these two signals, and switches the second switch 16. The third reception data selected by the second switch 16 is input to the fourth switch 21 as a first input, and the first transmission data is input to the fourth switch 21 as a second input. It is switched by the transmission side frame pulse. The third transmission data selected by the fourth switch 21 is input to the fifth switch 22 as a first input, and the first transmission data is also input as a second input to the fifth switch 22. It is switched by the Loop control signal and output as the second transmission data. The operation of each unit in the loop circuit 2 'is as described above.

Next, when the frame bit is 1 bit and there is a phase difference between transmission data and reception data, the above Loop
The signal flow in the circuit 2 'will be described. When the number of the frame bits is one or more, the state of the data and the frame pulse is as shown in FIG. Here, since the frame bit is 1 bit, the first, second, and third shift circuits 13, 1
5 and 17 are all one-stage shift circuits (if the number of bits is one or more, it is sufficient to prepare the number of stages of shift circuits; if five bits, the number of shift circuits is five). The first received data and the received data shifted by one stage in the first shift circuit 13 are combined with the pulse checker 1.
9 based on the select signal from the first switch 14
, One of them is selected.
It is determined that the received frame pulse and the transmitted frame pulse do not overlap in the pulse check unit 19, and the select signal for selecting the first received data is output from the pulse check unit 19, so that the second receive The data is the first received data (received data 2 = received data 1). Therefore, as the input of the second switch 16, the first received data and the received data obtained by shifting the first received data by one stage by the second shift circuit 15 are prepared. Next, either one of the first received frame pulse and the received frame pulse obtained by shifting the first received frame pulse by one stage by the third shift circuit 17 is selected by the third switch 18. The same reason as in the case of the received data described above (the first reception frame pulse and the transmission frame pulse are determined not to overlap by the pulse check unit 19, and the select signal for selecting the first reception frame pulse) Is output from the pulse check unit 19) from the third switch 18
Is output as the first received frame pulse.

[0010] Based on the first received frame pulse and the transmitted frame pulse, the received data switching signal generator 20
Generates a switching signal for the second switch 16.
The switching signal changes at the falling edge of the second received frame pulse (for example, it becomes “L”), so that the second switch 16 is not shifted by the second shift circuit 15. And outputs the received data.
Further, the switching signal from the received data switching signal generator 20 changes even at the falling edge of the transmission frame pulse.
(For example, "H"), whereby the second switch 1
Reference numeral 6 selects the reception data shifted by the second shift circuit 15 and outputs it as third reception data. FIG. 4 shows a time chart of the above signals.

Next, the fourth switch 21 selects and outputs the first transmission data only in the section of the transmission frame pulse based on the transmission frame pulse,
In the remaining section, the third received data from the second switch 16 is selected and output. Therefore, the third transmission data is as shown in the time chart of FIG. This means that the received data has been looped with the frame bits intact in accordance with the phase of the transmission data, and a loop has been formed with the frame bits passed through the transmission side and the reception side regardless of any phase difference between transmission and reception. Become. Then, when the above-mentioned Loop control signal comes, it may be output. Next, the flow of signals in the loop circuit 2 'when there is no phase difference between the transmission data and the reception data (when they match) will be described. That is, FIG.
As shown in (1), when the number of frame bits is one or more, the case where the transmission frame pulse and the first reception frame pulse slightly overlap each other applies to this description.

When the frame bit is 1 bit, there is a phase difference or there is only a match, so if it matches, it is sufficient to replace the frame bit. However, the following description will be made on the assumption that the frame bit is 1 bit or more. I do. Since the first reception frame pulse and the transmission frame pulse are determined to be coincident by the pulse check unit 19 (if the frame bit is 1 bit or more, it is determined that the coincidence is detected if any overlap is detected). , The pulse check unit 19
Outputs a select signal so as to select the received data shifted by the first shift circuit 13, so that the second received data output from the first switch 14 is the same as the shifted received data. Become. For the same reason, the second received frame pulse is a received frame pulse shifted by the third shift circuit 17. The subsequent operation is the same as described in the case where there is a phase difference, and a time chart of the signal state is shown in FIG.
(A). That is, the shifted first
The received data switching signal generator 20 generates a switching signal for the second switch 16 based on the received frame pulse (second received frame pulse) and the transmitted frame pulse. The switching signal changes at the falling edge of the second received frame pulse (for example, it becomes “L”), so that the second switch 16 is not shifted by the second shift circuit 15. And outputs the received data. Further, the switching signal from the received data switching signal generating unit 20 also changes at the falling edge of the transmission frame pulse (for example, becomes “H”), whereby the second switch 16 shifts the second shift. The received data shifted by the circuit 15 is selected and output as third received data.

Next, the fourth switch 21 selects and outputs the first transmission data only in the section of the transmission frame pulse based on the transmission frame pulse,
In the remaining section, the third received data from the second switch 16 is selected and output. This means that the received data has been looped with the frame bits intact in accordance with the phase of the transmission data, and a loop has been formed with the frame bits passed through the transmission side and the reception side regardless of any phase difference between transmission and reception. Become. The rest is Loop
What is necessary is just to output a control signal when it comes. FIG. 7B shows a state of a signal in the loop circuit shown in FIG. 1 when there is no phase difference between transmission data and reception data when frame bits are 1 bit or more (when they match). It is a time chart shown.

[0014]

As described above, according to the first aspect of the present invention, a phase difference having a phase difference equal to the number of frame bits is obtained.
Two pieces of received data are prepared, the two pieces of received data are switched by a switching signal based on the receiving side frame pulse and the transmitting side frame pulse, and a loop is performed with the frame bit passing through the transmitting side and the receiving side regardless of any phase difference between the transmitting and receiving sides. , The circuit scale can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of a transmission path test circuit according to the present invention.

FIG. 2 is a configuration diagram of a loop circuit shown in FIG. 1;

FIG. 3 is a time chart showing states of data and a frame pulse when a frame bit is 1 bit or more.

4 is a time chart showing a state of a signal in the loop circuit shown in FIG. 1 when a frame bit is 1 bit and there is a phase difference between transmission data and reception data.

5 is a time chart showing a state of a signal in the loop circuit shown in FIG. 1 when the frame bit is 1 bit and there is a phase difference between transmission data and reception data.

FIG. 6 shows a case where there is no phase difference between transmission data and reception data.
2 is a time chart showing a state of a signal in the loop circuit shown in FIG. 1 (when they match).

FIG. 7 shows a case where there is no phase difference between transmission data and reception data.
2 is a time chart showing a state of a signal in the loop circuit shown in FIG. 1 (when they match).

FIG. 8 is a configuration diagram of a transmission path test circuit in the multiplex transmission apparatus.

FIG. 9 is a configuration diagram of a transmission path test circuit in a case where information such as alarm information is included in transmission / reception frame bits.

10 is a time chart illustrating a state of a signal in the loop circuit illustrated in FIG. 9;

FIG. 11 is a configuration diagram of a conventional Loop circuit.

FIG. 12 is a time chart showing states of a reception frame pulse and a transmission frame pulse shown in FIG. 11;

[Explanation of symbols]

1. Test signal generation, 2 Loop circuit, 3 detection unit, 4 first frame INS unit, 5 first frame DET unit, 6 second
Frame DET section, 7 second frame INS section, 8 n-stage shift circuit, 9 switching section, 10 phase difference detection circuit, 11
First switch, 12 Second switch, 13 First switch
Shift circuit, 14 first switch, 16 second switch 15, 17 third shift circuit, 18 third switch, 19 pulse check unit, 20 received data switching signal generation unit, 21 fourth switch, 22 Fifth switch

Claims (1)

[Claims] A first apparatus is provided with a test signal generation unit, a first frame INS (registered trademark) unit, a first frame DET unit, and a detection unit, and is connected to the first apparatus via a transmission path. The connected second device is provided with a second frame DET unit, a loop circuit, and a second frame INS unit, and the transmitting side of the first device generates the test signal in a main signal portion other than frame bits. The PN pattern generated by the unit is inserted, a frame bit is added to the main signal part by the first frame INS unit, and the frame signal is output to the transmission line. The signal from the transmission line is The second frame DET unit synchronizes the received data with the frame phase of the transmission data so that the positions of the frame bits coincide with each other in the Loop circuit, and the reception data is shifted. The data part other than the position is replaced with a data part other than the frame bit position of the received data, the frame bit is added in the second frame INS part and transmitted to the transmission path. The returned main signal is the first frame DE on the receiving side in the first device.
After the frame is synchronized by the T unit, the PN
A transmission path test circuit in which a pattern is obtained and an error check is performed based on the obtained result, wherein the Loop circuit prepares two pieces of reception data having a phase difference of the number of the frame bits, Two received data are switched by a switching signal based on a receiving frame pulse and a transmitting frame pulse, and a loop is formed with frame bits passed to the transmitting side and the receiving side regardless of any phase difference between transmission and reception. Characteristic transmission line test circuit.