JP2002270819A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hererojunction bipolar transistor superior in high frequency characteristic, while a state in which the leakage between the base and the emitter is markedly small is maintained with high reproducibility. SOLUTION: A first insulation film 6, which has an opening part on the emitter 13 and covers a part of an outer base, is formed, and an emitter electrode 11 constituted of polycrystalline silicon is connected to the opening part. Sidewall-like second insulating films 8, which cover the upper face of the first insulating film 6 and cover the outer periphery of the side of the emitter electrode 11, are formed, and a third insulation film 10 which covers the whole outer periphery of the second insulation films 8 and the side of the first insulating film 6 is formed. The distance between the emitter 13 and a heavily-doped region 9 of the outer base is regulated in width at the base of the second insulating film 8 and is kept constant. The dummy pattern of the emitter electrode 11 is used for forming the second insulating film 8, so that a manufacturing method with small dispersion in width and superior reproducibility can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a bipolar transistor and a method for manufacturing the same.
In particular, the present invention relates to a semiconductor device including a heterojunction bipolar transistor in which a base layer is formed by an epitaxial method, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As a prior art, for example, there is a bipolar transistor structure as shown in FIG. FIG. 7 (A)-
(C) schematically shows the manufacturing process. Hereinafter, the prior art will be described with reference to this example.

[0003] As shown in FIG.
Is provided with a sub-collector layer 22 of the first conductivity type, a collector layer is formed thereon, and the element is separated by a field oxide film 23 to form a collector 24. Subsequently, as shown in FIG. 7B, a base layer 25 including a second conductivity type epitaxial film is formed on the collector 24 and the surrounding field oxide film 23.
Then, an insulating film 26 is formed on the entire surface of the substrate, and the insulating film 26 in the region where the emitter is to be formed is etched to form an opening 60. Separately, the insulating film 26 and the field oxide film 23 in the region where the collector electrode is formed are formed.
Is etched to form an opening 61. After this, FIG.
As shown in (C), an emitter electrode 27 made of polycrystalline silicon is formed by film formation and patterning so as to fill the opening 60, and the insulating film 26 on the base layer 25 located outside the emitter electrode 27 is removed by etching. I do. At the same time, the opening 61
Then, a collector electrode 28 made of polycrystalline silicon is formed. Subsequently, the emitter 29 is formed by thermal diffusion of the dopant from the polycrystalline silicon of the emitter electrode 27. Here, a region immediately below the emitter 29 of the base layer 25 is called an intrinsic base 50. A region of the base outside the intrinsic base 50 is called an external base, and functions as a base extraction electrode for connecting a base electrode 33 to be formed later. Almost the entire region of the external base is ion-implanted with a dopant of the second conductivity type using the emitter electrode 27 as a mask, thereby forming a high-concentration region 30 in the external base. Part of the external base remains as a low density region 55 between the intrinsic base 50 and the high density region 30.

When the behavior of carriers such as electrons in the operation of a bipolar transistor is qualitatively expressed by an example of a transistor shown in FIG.
Carrier flowing vertically through the intrinsic base 50 (minority carriers for the base) and carriers moving horizontally in the external base regions 55 and 30 from the emitter 29 to the base electrode 33 (electron diffusion current and hole diffusion). It is roughly divided into two directions of current flow. The former corresponds to the collector current, and the latter corresponds to the base current. The current amplification factor in the common emitter operation is defined by a value obtained by dividing the collector current by the base current. In order to increase this, the dopant concentration of the emitter 29 is made higher than the dopant concentration of the base layer 25, and the film thickness of the base layer 25 is increased. The base current is relatively reduced by reducing the thickness.

When a heterojunction bipolar transistor is formed by providing a step in the band gap between the emitter 29 and the base layer 25, the difference in band gap has the effect of relatively suppressing the diffusion current of majority carriers in the base layer 25. Since the base current can be further reduced, there is no fear that even if the dopant concentration of the base layer 25 is increased, the current amplification factor of the common emitter is significantly reduced due to the increase. For this reason, in the heterojunction bipolar transistor, a measure is taken to increase the dopant concentration of the base layer 25 and to reduce the base resistance of the entire device as low as possible. However, since the dopant concentration of the emitter 29 is further increased, the emitter-base junction becomes a high-concentration junction, which causes a problem that the leakage current between the emitter and the base increases. There is a limit to increasing the dopant concentration of the intrinsic base 50 in contact.

Therefore, in order to reduce the resistance at the base extraction electrode portion and reduce the base resistance of the entire device, ions are implanted into a part of the external base region to lower the resistance.
A high concentration region 30 is formed. In the example of FIG. 6, ion implantation is performed using the emitter electrode 27 as a mask, so that the emitter 29 and the high concentration region 30 of the external base are formed.
The low-concentration region 55 can be left between them. At this time, it is necessary to pay attention that if the ion-implanted low-concentration high-concentration region 30 and the high-concentration emitter 29 come into contact with each other due to redistribution of the dopant due to thermal diffusion, the above-described emitter-base leakage current will be caused. is there.
In FIG. 6, the insulating film 26 in contact with the surface of the base layer 25 is formed by plasma C instead of silicon oxidation.
When formed by a film forming process such as VD, the number of defects existing at the interface between the base layer and the insulating film increases, and the emitter 2
Carriers may move via defects between the high concentration region 9 and the high concentration region 30 of the external base, and may become another significant path of leakage current between the emitter and the base. Such a leak current is naturally undesirable for circuit operation.

In order to improve high-frequency performance, there is a tendency that the planar dimension is made finer and the dopant concentration of the emitter and the base is designed to be higher, and it has become a serious problem to suppress the above-mentioned leakage current. Therefore, it must be designed so that the emitter region 29 and the high-concentration region 30 of the external base do not come into contact with each other in planar dimensions. However, since the base resistance increases as the distance between them increases, the device characteristics are not stable unless the distance is manufactured constant. The important part is enlarged in FIG. 8 and will be described in detail with reference to FIG. In FIG. 8, design distances between the emitter 29 and the high concentration region 30 of the external base are A and A ′ shown in the figure. The boundary of the ion-implanted region forming the high-concentration region 30 of the external base is defined by photolithography for forming the emitter electrode 27. What is photolithography for forming an opening in the insulating film 26 that determines the position of the emitter 29? Positioning is performed in another process. From this, distances A, A '
Is fluctuated due to misalignment between two photolithography steps, and it is difficult to make A and A 'equal and a predetermined value.

The actual distance between the emitter 29 and the high-concentration region 30 of the external base is influenced by the heat treatment at the time of the formation, and the dopant is spread by a predetermined distance. In FIG. 8, the spread of the emitter 29 is represented by B and B ′.
, The extent of the high density region 30 of the external base is indicated by C and C ′. Diffusion by heat treatment depends on the material and crystallinity of the semiconductor layer and heat treatment conditions, but may be regarded as substantially constant expansion under fixed conditions. Therefore, B and B 'and C and C' are usually equal, and the above-mentioned fluctuation of A and A 'directly leads to fluctuation of the distance between the emitter 29 and the high concentration region 30.

[0009]

In the conventional structure described in detail above, it is desirable to set the shortest distances A and A 'as long as the leakage current between the emitter and the base does not increase.
It is difficult to make them both equal and a predetermined value. The result of the variation in the manufacturing process of A and A 'appears as a leakage current between the emitter and the base, and further, a variation in high frequency performance. Therefore, take either of the following two measures: sacrifice the yield of defective products with performance below a certain level in the inspection process, or sacrifice the high-frequency performance by enlarging the element dimensions with a design that allows for margin of photolithography accuracy. There was a problem that had to be.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and solves the conventional problems. A heterojunction bipolar transistor having a novel structure having a sufficiently small leak current and excellent high-frequency performance is provided. To provide a semiconductor device having, without sacrificing other characteristics,
An object of the present invention is to provide a method for manufacturing a semiconductor device including a heterojunction bipolar transistor, which can maintain high-frequency performance and low leakage current with good reproducibility.

[0011]

In order to achieve the above object, a semiconductor device of the present invention comprises a semiconductor substrate having a collector layer of a first conductivity type and a base layer including an epitaxial layer of a second conductivity type formed in that order. A first conductivity type emitter is formed in the base layer in an island shape, and the base layer includes an intrinsic base immediately below the emitter and an external base outside the emitter, and the base layer is formed on the emitter above the emitter. A first insulating film having an opening at an outer edge thereof on the external base, wherein an emitter electrode made of polycrystalline silicon is connected to the emitter in the opening, and the first insulating film is formed. A second insulating film in the form of a side wall is formed to cover the upper surface of the first electrode and to cover the outer periphery of the side surface of the emitter electrode, and a third insulating film covering the entire outer periphery of the second insulating film and the side surface of the first insulating film. Shape of insulating film Are, the emitter electrode is characterized by having a hetero bipolar transistor in which the upper portion is arranged to extend up over the third insulating film.

As a result, the side wall-shaped second insulating film keeps the distance between the emitter and the high concentration region of the external base constant with good reproducibility, and can surely separate the regions at a finer distance than in the conventional example. . As a result, the frequency can be increased without increasing the leakage current between the emitter and the base, and a semiconductor device having a heterojunction bipolar transistor excellent in high frequency performance can be realized.

In addition to the above structure, the present invention may have a structure in which a metal silicide layer is formed on the surface of the external base outside the region surrounded by the side wall-shaped second insulating film.
In such a structure, the external base resistance can be greatly reduced, so that the high-frequency characteristics of elements having the same dimensions can be further improved.

In the present invention, a semiconductor substrate is a silicon substrate or an SOI substrate, the collector layer is mainly made of silicon, and the base layer is a mixed crystal layer containing germanium in at least a part thereof by an epitaxial method. The formed structure can be used. In this case, since a device such as a CMOS using silicon can be easily integrated, a semiconductor device having a high-performance circuit such as a Bi-CMOS can be formed on a single substrate.

According to the semiconductor device of the present invention, a collector layer of a first conductivity type is formed on a semiconductor substrate to form a collector region separated by an oxide film, and the collector region and an oxide film around the collector region are formed. Forming, in a region, a base layer including a second conductivity type epitaxial film containing at least silicon and germanium; oxidizing a surface of the base layer to form a first insulating film; Forming a dummy pattern of an emitter electrode made of polycrystalline silicon or silicon nitride so as to be located on the collector region on the first insulating film; and forming a sidewall-like pattern on the first insulating film around the dummy pattern. A step of forming a second insulating film, a step of covering the first and second insulating films and forming a third insulating film over the entire surface of the substrate, and a step of forming the dummy of the third insulating film. Forming a void by opening a position corresponding to the pattern and removing the dummy pattern and the first insulating film immediately below the dummy pattern; and filling the void and forming an upper portion on the third insulating film. Forming an emitter electrode of first conductivity type polycrystalline silicon exposed to the substrate. In such a manufacturing process, the control of the steps is easy and the reproducibility is excellent. In addition, the first insulating film protects the region of the base layer that affects the element characteristics from processing damage during etching, etc., so that a semiconductor device having a heterojunction bipolar transistor having excellent high-frequency characteristics can be manufactured with high yield. realizable.

Further, according to the present invention, there is provided a step of forming a collector layer of a first conductivity type on a semiconductor substrate to form a collector region separated by an oxide film, and forming the collector region and an oxide film region around the collector region. Forming a base layer including a second conductivity type epitaxial film containing at least silicon and germanium; oxidizing a surface of the base layer; and forming a silicon oxide film on the entire surface of the substrate to form a first insulating film. Forming a film, forming a dummy pattern of the emitter electrode by removing the first insulating film outside the region where the emitter electrode is formed by etching while leaving a predetermined thickness, Forming a side wall-shaped second insulating film on the first insulating film around the dummy pattern; forming a third insulating film on the entire surface of the substrate so as to cover the first and second insulating films; Opening a position of the third insulating film corresponding to the dummy pattern, removing the dummy pattern and the first insulating film immediately below the dummy pattern to form a void, It may be manufactured by a method of forming an emitter electrode of first conductivity type polycrystalline silicon in which a portion is buried and an upper portion is exposed on the third insulating film. According to this method, the step of removing the dummy pattern and the first insulating film to form the gap can be performed at a time, so that there is an effect that the step is simpler and easy to manufacture.

Further, in the present invention, after forming the second insulating film in a side wall shape, a step of removing the first insulating film located outside the second insulating film; Forming a metal silicide film on the surface of the base layer of the second conductivity type, which is located at the second position, and thereafter, performing a step of forming a third insulating film. On the surface of the external base area outside the
A manufacturing method for forming a metal silicide layer can be added. In this case, since the external base resistance can be significantly reduced, the high-frequency characteristics of elements having the same dimensions can be further improved.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic cross section of a semiconductor device of the present invention. A first conductivity type sub-collector layer 2 is provided on a semiconductor substrate 1, a collector layer is formed, and elements are separated by a field oxide film 3.
A collector 4 of the first conductivity type is formed. The base layer 5 includes an intrinsic base 70 and an external base outside thereof. The external base includes a low-concentration region 75 and a high-concentration region 9 of the second conductivity type dopant. A first insulating film 6 having an opening is formed on the base layer 5, an emitter electrode 11 made of polycrystalline silicon is connected to the opening, and a first conductivity type of polycrystalline silicon is formed. The emitter 13 is formed by the diffusion of the dopant. The first insulating film 6 covers the low-concentration region 75, and a part thereof extends to the surface of the high-concentration region 9. A side wall-shaped second insulating film 8 is formed to cover the upper surface of the first insulating film 6 and to cover the outer periphery of the side surface of the emitter electrode 11. Further, the entire outer periphery of the second insulating film 8 and the first insulating film are formed. The third insulating film 10 covering the side surface of the sixth insulating film 6 is formed.

FIGS. 2A to 2D and FIGS. 3A to 3C.
The main cross sections of the present invention are shown for each step, and the manufacturing method will be described in the order of steps. By a known manufacturing method, as shown in FIG. 2A, device isolation was performed using a field oxide film 3 having a thickness of 7500 ° and an n ⁻ -type collector 4 having a thickness of 8000 ° was formed in the device portion. Next, a base layer 5 made of a p-type epitaxial film containing germanium is formed,
After patterning, the surface is thermally oxidized to a thickness of 80Å.
The first insulating film 6 was formed. The base layer 5 has a reduced pressure CV
Using a D apparatus, add a buffer layer to the interface with collector 4
A SiGe film having a thickness of 00 ° and a germanium concentration of 20% is formed, and boron is applied thereon with the same germanium concentration of 1 ×.
The structure is such that a film having a thickness of 300Å is formed by doping at 10 ¹⁹ cm ^-3 and a silicon film having a thickness of 300Å is further formed. These films grow monocrystalline epitaxially on the collector 4 and grow polycrystalline on the field oxide film 3.

Next, as shown in FIG. 2B, a dummy pattern 7 corresponding to the emitter shape is formed in a region where the emitter is to be formed, and a polycrystalline silicon film having a thickness of 50 is formed by low pressure CVD.
After the film was formed by photolithography, the film was formed by photolithography and RIE (reactive ion etching), and then a silicon nitride film 8 was formed on the entire surface to a film thickness of 6000 by plasma CVD. Subsequently, as shown in FIG. 2C, the entire surface of the silicon nitride film 8 was etched by RIE, so that the second insulating film 8 was left on the side wall of the dummy pattern 7 having a step. The maximum height and maximum width of the formed side wall-shaped second insulating film 8 were about 0.5 μm and about 0.3 μm, respectively. At this time, the first insulating film 6 was also etched in the region where the second insulating film 8 was etched. However, the dummy pattern 7 and the sidewall-shaped second insulating film 8 served as a mask, and the region where the emitter was formed and its In the vicinity, processing damage to the first insulating film 6 does not occur, and in this region, the situation where the base layer is protected from process contamination and processing damage by the first insulating film 6 is maintained.

Then, as shown in FIG. 2D, ion implantation of BF ₂ ^{+ using} the dummy pattern 7 and the side wall-shaped second insulating film 8 as a mask is performed at an acceleration voltage of 30 keV and a dose of 2 × 10 ¹⁵ cm. ^{This was} performed under the conditions of ^-2 to form a p ⁺ -type high concentration region 9. Thereafter, the third insulating film 10 formed of silicon oxide by atmospheric pressure CVD so as to cover the entire surface with a thickness of 6000 ° is subjected to a planarization process by an etch-back method using a resist so as to reduce a step. Was. This flattening process is effective for making the photolithography conditions in the next step the same when the step shape is different.
In the example of FIG. 2, the first insulating film 6 on the high-concentration region 9 of the external base which is made to be p ⁺ type by ion implantation has been removed first. It is more preferable that the insulating film 6 is left.

Thereafter, as shown in FIG. 3A, the emitter region of the third insulating film 10 is opened, and the dummy pattern 7 is formed.
Only the emitter region of the first insulating film 6 was selectively removed by etching. The opening of the third insulating film 10 is positioned by performing mask alignment with the dummy pattern 7, but misalignment occurs. Therefore, the opening width is designed to be 0.2 μm narrower than the dummy pattern 7. After the dummy pattern 7 is selectively removed by etching, when the first insulating film 6 is etched, the side etching proceeds to the opening of the third insulating film 10, so that the opening width is substantially reduced. No problem. Further, even when the opening of the third insulating film 10 is biased outside the dummy pattern 7 due to misalignment, no defect occurs because the opening is within the width of the bottom of the second insulating film 8. Alternatively, FIG.
In the case of the etch back described above in FIG.
If etching is performed until the surface is exposed, a self-aligning process that does not require mask alignment can be performed, and this is particularly effective when the width of the emitter 13 is reduced to the minimum dimension of photolithography.

Next, as shown in FIG.
An emitter electrode 11 was formed by forming and patterning polycrystalline silicon having a film thickness of 5000 ° doped with × 10 ²⁰ cm ⁻³ , and then an emitter 13 was formed by thermal diffusion of the dopant. Since the high-concentration region 9 of boron is formed close to the emitter 13 by the diffusion of boron in the thermal diffusion process, it is necessary to optimize the thermal diffusion process conditions and the width of the bottom of the second insulating film 8. is there. In the present embodiment, the condition of the thermal diffusion treatment is 850 ° C. × 30 seconds. FIG.
As shown in FIG. 3C, following the patterning of the emitter electrode 11 made of polycrystalline silicon, the third insulating film 10 is formed.
May be etched to remove the insulating film 10 from the connection portion of the base electrode 16. The hetero structure is not limited to the above-described SiGe film, but may be a structure using a SiGeC film to which carbon is added as a base, an emitter, or the like.

In this manner, the emitter 13 could be separated from the high concentration region 9 of the external base at a certain distance. At this time, the previously formed first insulating film 6
Is used to prevent leakage current between the emitter and the base and to reduce process contamination and processing damage before the formation of the emitter 5. The side wall-shaped second insulating film 8 is formed by the emitter 13 and the emitter electrode 11 made of polycrystalline silicon and the external base. The third insulating film 10 serves to ensure the insulation separation of the emitter electrode 11 while keeping the distance of the high concentration region 9 constant. The heterojunction bipolar transistor thus formed is
It is desirable that the width at the bottom of the second insulating film 8 be in the range of 0.2 μm to 0.5 μm in order to increase the frequency without increasing the leak current. In this case, the height of the second insulating film 8 can be manufactured in a range where the highest part is 0.3 μm to 1 μm. According to the data of the inventors, the optimum value is a forming condition in which the width at the bottom of the second insulating film 8 is 0.3 μm and the height is 0.5 μm.

The above three types of insulating films are required to have insulating properties in view of their structures. On the other hand, the dummy pattern 7 may be made of an insulating material or not. Therefore, the material of the dummy pattern 7 and the side wall-shaped second insulating film 8 can be arbitrarily selected as long as the combination can realize the shape shown in FIG. As such a combination, the dummy pattern 7 is made of polycrystalline silicon,
In a combination using a silicon nitride film for the insulating film 8 of
The thickness of the silicon oxide, which is the material of the first insulating film 6, is from 50 °, which is a film thickness necessary for protecting the device from surface contamination, and the influence of side etching on the window opening size in FIG. Can be selected up to a film thickness of 1000 °, at which the occurrence of cracks starts.

As a second combination example of the material of the dummy pattern 7 and the sidewall-shaped second insulating film 8, polycrystalline silicon is used for the dummy pattern 7 and a silicon oxide film is used for the second insulating film 8. it can. Similarly, as a third combination example of the material of the dummy pattern 7 and the sidewall-shaped second insulating film 8, silicon nitride can be used for the dummy pattern 7 and silicon oxide can be used for the second insulating film 8. . In any case, since the etching selectivity of the first insulating film 6 and the second insulating film 8 is small, the dummy pattern 7 is removed in the step of removing the emitter opening of the first insulating film 6 in FIG. The width of the side etching occurs due to the processing width of. In such a case, the first insulating film 6 is
By reducing the thickness from {circle around (1)} to {right arrow over (100)}, a measure could be taken to suppress the spread of side etching to within 0.1 μm.

[Second Embodiment] As a fourth combination example of the material of the dummy pattern 7 and the sidewall-shaped second insulating film 8, silicon oxide is used for the dummy pattern 7,
4A to 4D show steps of the second embodiment using a silicon nitride film as the insulating film 8. The first insulating film 6 forming the silicon oxide of the dummy pattern 7 has a thickness of 80 °.
And a 5000-nm-thick silicon oxide film continuously formed by normal pressure CVD. FIG.
As shown in (B), the first is obtained by photolithography.
When etching the insulating film 6, the dummy pattern 7 was formed by stopping the etching so that the remaining film thickness of the first insulating film 6 became 700 ° without being etched off. In this case, it is preferable that the remaining film thickness of the first insulating film 6 after etching is set to 1000 ° or less. At this time, the second insulating film 8 in FIG.
Was typically 0.3 microns wide at the bottom and 0.4 microns high. FIG. 4D shows the shape of FIG.
This is the same as (D), and the subsequent steps are the same as in the case of the first embodiment.

[Third Embodiment] FIGS. 5A to 5D
7 shows a process of the third embodiment in which metal silicide is formed on the external base portion other than the vicinity of the emitter 13 in order to greatly reduce the external base resistance in the embodiment shown in FIG. In the present invention, the first insulating film 6 located on the outer periphery of the second insulating film 8 selectively formed on the side wall of the dummy pattern 7 is removed, and the external base portion is removed before removing the dummy pattern 7. It is possible to add a step of forming a metal silicide on the silicon surface.

As shown in FIG. 4C, a dummy pattern 7 is formed and a side wall-shaped second insulating film 8 is formed. In the region where the second insulating film 8 is etched, the first insulating film 6 is formed. 5A, boron ions are implanted into the external base region, and then a metal titanium film is formed by a known method and then heat-treated to form a silicide, thereby forming an unreacted material. Metal titanium layer is removed to form a film thickness of 200
A titanium silicide layer 18 of about Å was selectively formed.
Such metals that can selectively form silicide include cobalt, tungsten, nickel, chromium, and the like in addition to titanium.

Thereafter, as shown in FIGS. 5B to 5D, an emitter region is opened in the third insulating film 10 formed so as to cover the whole, and the dummy pattern 7 and the first
Only the emitter region of the insulating film 6 was selectively removed by etching, the emitter electrode 11 was formed, and the emitter 13 was formed. In the conventional silicide process, after the emitter electrode 11 is formed, the metal silicide is formed on the silicon surface of the external base portion outside the emitter electrode 11. Therefore, the variation factor described in the conventional example has the same effect. In the present invention, the second
The thickness of the insulating film 8 allows the addition of the titanium silicide layer 18 with the shortest distance to the emitter 13, the external base resistance is reduced to one-tenth or less as compared with the case where this is not used, and the high-frequency performance varies. Without any improvement.

[0031]

As described above, according to the present invention, the high concentration region of the emitter and the external base can be separated at the shortest distance.
A semiconductor device including a heterojunction bipolar transistor with improved high-frequency performance without increasing the leakage current between the emitter and the base can be obtained. Further, according to the manufacturing method of the present invention, the above-described semiconductor device can be manufactured with high yield.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a semiconductor device obtained according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for each step showing a method for manufacturing the semiconductor device shown in FIG. 1;

FIG. 3 is a cross-sectional view of each step following FIG. 2;

FIG. 4 is a sectional view of each step of a semiconductor device obtained according to a second embodiment of the present invention.

FIG. 5 is a sectional view of each step of a semiconductor device obtained according to a third embodiment of the present invention.

FIG. 6 is a schematic sectional view showing an example of a conventional semiconductor device.

FIG. 7 is a cross-sectional view for each step showing the method for manufacturing the semiconductor device shown in FIG. 6;

FIG. 8 is an enlarged cross-sectional view of a part of the semiconductor device shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 21 Semiconductor substrate 2, 22 Subcollector layer 3, 23 Field oxide film 4, 24 Collector 5, 25 Base layer 50, 70 Intrinsic base 9, 30 High concentration area of external base 55, 75 Low concentration area of external base 6 , 26 First insulating film 7 Dummy pattern 8 Second insulating film 10 Third insulating film 11, 27 Emitter electrode 12, 28 Collector electrode 13, 29 Emitter

Claims (6)

[Claims] A first conductivity type collector layer formed on a semiconductor substrate;
A base layer including an epitaxial layer of the second conductivity type is formed in order, and an emitter of the first conductivity type is formed in the base layer in an island shape. A first insulating film is formed on the base layer, the first insulating film having an opening on the emitter and having an outer edge on the external base; and An emitter electrode is connected to the emitter, and a sidewall-shaped second insulating film covering an upper surface of the first insulating film and covering an outer periphery of a side surface of the emitter electrode is formed. A third insulating film is formed to cover the entire outer periphery of the first insulating film and a side surface of the first insulating film, and the emitter electrode has an upper portion extending over the third insulating film. A semiconductor device comprising: a. 2. The semiconductor device according to claim 1, wherein the external base outside a region surrounded by the second insulating film has a metal silicide layer provided on an upper surface thereof. 3. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate or a silicon substrate.
An OI (Silicone On Insulator) substrate, wherein the collector layer is mainly composed of silicon, and the base layer is formed at least partially with a mixed crystal layer of silicon and germanium formed by an epitaxial method. The semiconductor device according to claim 1. 4. A step of forming a collector layer of a first conductivity type on a semiconductor substrate to form a collector region separated by an oxide film, and forming at least silicon in the collector region and an oxide film region around the collector region. Forming a base layer including a second conductivity type epitaxial film containing silicon and germanium; oxidizing a surface of the base layer to form a first insulating film; and forming a first insulating film on the first insulating film. Forming a dummy pattern of an emitter electrode made of polycrystalline silicon or silicon nitride so as to be located on the collector region; and forming a sidewall-shaped second insulating film on the first insulating film around the dummy pattern. Forming the first, and the first
Forming a third insulating film over the entire surface of the substrate, covering the entire surface of the substrate, and opening a position of the third insulating film corresponding to the dummy pattern to form a third insulating film. Forming a gap by removing the first insulating film; and forming an emitter electrode of first conductivity type polycrystalline silicon filling the gap and exposing an upper portion on the third insulating film. And a method of manufacturing a semiconductor device. 5. A step of forming a collector layer of a first conductivity type on a semiconductor substrate to form a collector region separated by an oxide film, and forming at least silicon in the collector region and an oxide film region around the collector region. Forming a base layer including a second conductivity type epitaxial film containing silicon and germanium; and oxidizing the surface of the base layer, forming a silicon oxide film over the entire surface of the substrate to form a first insulating film. And forming the first electrode outside the region where the emitter electrode is formed.
Forming a dummy pattern of the emitter electrode by removing the insulating film by etching while leaving a predetermined thickness, and forming a sidewall-shaped second insulating film on the first insulating film around the dummy pattern. Forming a film, covering the first and second insulating films and forming a third insulating film over the entire surface of the substrate, and opening a position of the third insulating film corresponding to the dummy pattern. Removing the dummy pattern and the first insulating film immediately below the dummy pattern to form a gap, and filling the gap with a first conductive type having an upper part exposed on the third insulating film. Forming an emitter electrode of polycrystalline silicon. 6. A step of removing the first insulating film located outside the second insulating film after forming the sidewall-shaped second insulating film; 6. The method according to claim 4, further comprising: forming a metal silicide film on a surface of the base layer of the second conductivity type located at a second position, and then forming the third insulating film. A method for manufacturing a semiconductor device.