JP2002269894A - Rotation control circuit and recordable optical disk driving device using the same, and rotation control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform stable rotation control of an optical disk without jitters due to disturbance. SOLUTION: A reference clock A before being changed in phase according to phase difference information is inputted to a frequency difference detector 208 in a wobble CLV control circuit 201. In this case, disturbance due to the phase difference information does not occur when the frequency of a locked wobble signal is matched to the reference frequency, the frequency difference can stably be detected. On the other hand, a reference clock B changed in phase according to the phase difference information between an ATIP synchronous signal and a code frame synchronous signal is inputted to a phase difference detector 209 in the wobble CLV control circuit 201. In this case, the ATIP synchronous signal and the sub-code frame synchronous signal can be made to be in phase with each other with accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a rotation control circuit, a recordable optical disk drive using the same, and a rotation control method.

[0002]

2. Description of the Related Art In recent years, CD-Rs have been used as information recording media.
Recordable optical disks such as W, MO, and DVD-RAM have been widely used. In such an optical disc, when writing information, rotation control of the optical disc becomes important in order to accurately record write data at a predetermined address of the optical disc.

A conventional example of an optical disk drive for controlling the rotation of a recordable optical disk will be described below.

FIG. 17 schematically shows a conventional optical disk drive. FIG. 18 shows a specific example of the rotation control circuit 111 in the optical disk drive of FIG.

The rotation control circuit 111 has a wobble CLV
(Wobble Constant Linear Velocity) control circuit 20
1. Phase change circuit 202 and ATIP (Absolute Time
In Pre-groove) It comprises a phase difference detection circuit 203.

The ATIP phase difference detection circuit 203 will be described.

[0007] The ATIP phase difference detection circuit 203 includes a phase comparator 210 and a gain adjustment circuit 211.
The subcode frame synchronization signal and the ATIP synchronization signal are
It is input to the phase comparator 210. The subcode frame synchronization signal indicates, for example, a write address specified by the microcomputer, and the ATIP synchronization signal indicates an actual address of the optical disc 101. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address of the optical disc 101.

[0008] The output signal of the phase comparator 210 is input to a gain adjustment circuit 211. The gain adjustment circuit 211
The gain of the output signal of the phase comparator 210 is adjusted. The output signal of the gain adjustment circuit 211 is input to the phase change circuit 202.

The phase change circuit 202 includes a gain adjustment circuit 2
A reference clock B having a constant phase (or frequency) and a changed phase (or frequency) is generated according to the output signal of the reference clock A. The phase change circuit 202
For example, it can be realized by a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211.

For example, consider a case where the phase of the ATIP synchronization signal is ahead of the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase lead flag according to the phase difference between the two signals. This phase advance flag means that the rotation speed of the optical disk 101 is faster than the timing of recording the write data.

Therefore, while the phase advance flag is being output from the phase comparator 210, the phase change circuit 202 is used to change the reference clock A by an amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal. The phase is delayed and a reference clock B is generated. Since this phase delay is directly reflected on the output signal of the phase difference detector 209, it acts in the direction of decreasing the rotation speed of the optical disc 101.

Also, consider a case where the phase of the ATIP synchronization signal is delayed with respect to the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase delay flag according to the phase difference between the two signals. This phase delay flag means that the rotation speed of the optical disk 101 is slower than the timing of recording the write data.

Therefore, while the phase delay flag is being output from the phase comparator 210, the phase change circuit 202 is used to change the reference clock A by the amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal. The phase is advanced, and a reference clock B is generated. Since the advance of the phase is directly reflected on the output signal of the phase difference detector 209, it acts in the direction of increasing the rotation speed of the optical disc 101.

If the phase of the sub-code frame synchronization signal matches the phase of the ATIP synchronization signal,
Neither the phase advance flag nor the phase delay flag is output from the phase comparator 210. Therefore, the reference clock A is used as it is as the reference clock B, and the phase change circuit 202
Output from

A wobble CLV control circuit 201 controls a motor for rotating an optical disk based on a reference clock B and a locked wobble signal.
Outputs WM (Pulse Width Modulation) signal.

The wobble CLV control circuit 201 has a PWM
Output circuit 204, adder 205, buffers 206, 20
7. It comprises a frequency difference detector 208 and a phase difference detector 209.

The reference clock B and the locked wobble signal are input to a frequency difference detector 208 and a phase difference detector 209, respectively. As described above, the reference clock B is used to correct the deviation between the write address specified by the microcomputer and the actual address on the optical disk.
Using the TIP phase difference detection circuit 203, the reference clock A
Is a signal generated by The locked wobble signal is
This is a signal that is locked by a PLL to the average frequency of the meandering of grooves spirally formed on the optical disk, and is a signal that indicates the rotation speed of the optical disk.

The frequency difference detector 208 receives the reference clock B
Is compared with the frequency of the locked wobble signal, and an output signal corresponding to the frequency difference between the two is output. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal, and outputs an output signal according to the phase difference between the two.

The adder 205 adds the output signal of the frequency difference detector 208 and the output signal of the phase difference detector 209 and outputs the added result to the PWM output circuit 204. P
The WM output circuit 204 controls the motor for rotating the optical disk based on the output signal of the adder 205.
Output a signal.

[0020]

In the optical disk drive shown in FIGS. 17 and 18, when information is recorded on the optical disk, if a disturbance (noise) enters the signal in the rotation control circuit 111, the information is stored in the correct address. Recording cannot be performed.

For example, in the optical disk drive shown in FIGS. 17 and 18, the reference clock A is converted into a reference clock B based on the phase correction signal output from the ATIP phase difference detection circuit 203. It is given to the wobble CLV control circuit 201. That is, both the frequency difference detector 208 and the phase difference detector 209 in the wobble CLV control circuit 201 receive the reference clock B whose phase has been changed.

However, since the phase correction signal output from the ATIP phase difference detection circuit 203 is information of a phase shift, the phase correction signal is transmitted to the wobble CLV control circuit 20.
When the signal is reflected on the frequency difference detector 208 within 1, the output signal of the frequency difference detector 208 causes disturbance.

The ATIP phase difference detection circuit 203
If there is a difference between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal, a phase correction signal is output. Here, for example, when the optical disk has eccentricity, a shift occurs between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal. Although this deviation is minute, it always occurs in a steady state, and as a result, a phase correction signal is also frequently output. This phase correction signal becomes a disturbance.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency difference detector which eliminates the influence of an output signal of an ATIP phase difference detection circuit and detects a stable frequency difference. And to perform stable rotation control even for a minute phase shift (jitter) in a steady state.

[0025]

(1) A rotation control circuit according to the present invention comprises a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data. A phase difference detection circuit that outputs a phase correction signal based on the first phase difference, and changes a phase of a first reference clock based on the phase correction signal;
A phase change circuit that outputs a second reference clock; and a third change circuit that indicates a rotation speed of the first reference clock and the disk.
A frequency difference detector for detecting a frequency difference between the signal and
A second signal between the second reference clock and the third signal;
And an output circuit that outputs a fourth signal for controlling the rotation speed of the disk based on the frequency difference and the second phase difference.

The optical disk drive of the present invention generates the rotation control circuit that outputs the fourth signal based on the first, second, and third signals, and generates the first and third signals. A timing generator for generating the second signal; and a driver for driving the optical disk based on the fourth signal.

According to the rotation control method of the present invention, a step of detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data; Generating a phase correction signal based on a phase difference between the first and second reference clocks; generating a second reference clock in which the phase of a first reference clock is changed based on the phase correction signal; Detecting a frequency difference between a clock and a third signal representing the rotational speed of the disk; and detecting a second phase difference between the second reference clock and the third signal. And controlling the rotation speed of the disk based on the frequency difference and the second phase difference.

(2) The rotation control circuit according to the present invention detects a first phase difference between a first signal representing an absolute address of the disk and a second signal representing the timing of write data, and A phase difference detection circuit that outputs a phase correction signal based on the first phase difference when the phase difference is equal to or greater than a threshold, and changes a phase of a first reference clock based on the phase correction signal. A phase change circuit that outputs a second reference clock; a frequency difference detector that detects a frequency difference between the second reference clock and a third signal that indicates a rotation speed of the disk; A phase difference detector that detects a second phase difference between the reference clock and the third signal; and a second controller that controls a rotation speed of the disk based on the frequency difference and the second phase difference. And an output circuit for outputting the signal of You.

An optical disk drive according to the present invention generates the rotation control circuit for outputting the fourth signal based on the first, second and third signals, and generates the first and third signals. A timing generator for generating the second signal; and a driver for driving the optical disk based on the fourth signal.

According to the rotation control method of the present invention, a step of detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data; Generating a phase correction signal based on the first phase difference when the phase difference is equal to or greater than a threshold, and a second phase changing a first reference clock based on the phase correction signal. Generating a reference clock; detecting a frequency difference between the second reference clock and a third signal representing a rotational speed of the disk; and detecting the second reference clock and the third signal. Detecting the second phase difference between the two, and controlling the rotational speed of the disk based on the frequency difference and the second phase difference.

(3) The rotation control circuit according to the present invention detects a first phase difference between a first signal indicating an absolute address of the disk and a second signal indicating the timing of write data, and A phase difference detection circuit that outputs a phase correction signal based on the first phase difference when the phase difference is equal to or greater than a threshold, and changes a phase of a first reference clock based on the phase correction signal. A phase change circuit that outputs a second reference clock; a frequency difference detector that detects a frequency difference between the first reference clock and a third signal that indicates a rotation speed of the disk; A phase difference detector that detects a second phase difference between the reference clock and the third signal; and a second controller that controls a rotation speed of the disk based on the frequency difference and the second phase difference. And an output circuit for outputting the signal of You.

The optical disk drive of the present invention generates the rotation control circuit for outputting the fourth signal based on the first, second and third signals, and generates the first and third signals. A timing generator for generating the second signal; and a driver for driving the optical disk based on the fourth signal.

According to the rotation control method of the present invention, a step of detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data; Generating a phase correction signal based on the first phase difference when the phase difference is equal to or greater than a threshold, and a second phase changing a first reference clock based on the phase correction signal. Generating a reference clock; detecting a frequency difference between the first reference clock and a third signal representing the rotational speed of the disk; and detecting the second reference clock and the third signal. Detecting the second phase difference between the two, and controlling the rotational speed of the disk based on the frequency difference and the second phase difference.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a rotation control circuit, a recordable optical disk drive using the same, and a rotation control method according to the present invention will be described with reference to the drawings.

1. Optical Disk Drive FIG. 1 schematically shows an optical disk drive according to the present invention.

On the optical disk 101, a pre-groove spirally formed and meandering at a predetermined period.
Is engraved. By modulating the period of this pre-groove meander, ie, wobbling,
ATIP corresponding to address information on optical disk 101
(Absolute Time In Pre-groove) can be recorded.

The wobbling on the optical disk 101 is formatted so that the ATIP is recorded in a 75 Hz frame. That is, in each frame,
Absolute time based on the innermost circumference of the optical disc (absolute time
time) is recorded as a 42-bit absolute address.

The absolute address is a 4-bit synchronization code,
It is composed of minute data, second data and frame data consisting of 8-bit BCD (Binary Code Decimal), and 14-bit CRC (Cyclic Redundancy Check) data (the above is collectively referred to as ATIP data), and 3150 bits N with a bit rate of / sec
Coding to RZ (Non Return to Zero) code (c
oding).

The ATIP data is 6.3 kHz.
Bi-phase mark modulation by the bit clock of
It becomes a bi-phase signal. Further, when the bi-phase signal is frequency-modulated, the FM of the carrier frequency of 22.05 Hz is obtained.
A signal (wobble signal) is obtained.

The spindle motor 113 is used for the optical disc 1
01 and rotate. Pickup 102
Irradiates the optical disk 101 with a laser beam, receives reflected light from the optical disk 101, converts it into an electric signal, and outputs it as an RF signal. Signal detection amplifier 103
Processes the RF signal and outputs the above-mentioned wobble signal.

The wobble signal is sent to the ATIP decoder 104
Is input to The ATIP decoder 104 outputs an ATIP synchronization signal based on the wobble signal, locks the PLL to the carrier frequency of the wobble signal, and outputs a signal representing the rotation speed of the optical disc 101 (hereinafter, referred to as a locked wobble signal). I do. The ATIP synchronization signal and the locked wobble signal are input to the rotation control circuit 111.

The crystal oscillator 107 has, for example, a 22 mega H
Generate a clock having a frequency of z. This clock is input to the frequency dividing circuit 108 and the multiplying circuit 109.

The frequency dividing circuit 108 outputs, as a reference clock A, a clock obtained by dividing the frequency of the clock generated by the crystal oscillator 107 to 1 / N (N is a positive number).
The multiplying circuit 109 outputs a clock obtained by multiplying the frequency of the clock generated by the crystal oscillator 107.

The timing generator 110 includes the multiplication circuit 10
9 and outputs a subcode frame synchronization signal and a timing signal for operating the CD encoder 105.

The sub-code frame synchronization signal is input to the rotation control circuit 111. The CD encoder 105 encodes the write data based on the timing signal. That is, the CD encoder 105 performs EFM modulation on the main data and the subcode data, and outputs an EFM signal.

The laser drive circuit 106 drives the pickup 102 based on the EFM signal output from the CD encoder 105, and determines a laser irradiation position. Further, the laser drive circuit 106 controls the laser power based on the EFM signal output from the CD encoder 105, such as increasing the laser power at the time of writing.

The rotation control circuit 111 outputs a PWM signal for controlling the rotation speed of the optical disk 101 based on the locked wobble signal, the reference clock A, the ATIP synchronization signal and the subcode frame synchronization signal. The driver 112 receives the PWM signal and actually drives the spindle motor 113 to control the rotation speed of the optical disc 101.

2. FIG. 2 shows a first example of the rotation control circuit 111 in the optical disk drive of FIG.

The rotation control circuit 111 has a wobble CLV
(Wobble Constant Linear Velocity) control circuit 20
1. Phase change circuit 202 and ATIP (Absolute Time
In Pre-groove) It comprises a phase difference detection circuit 203.

The ATIP phase difference detection circuit 203 comprises a phase comparator 210 and a gain adjustment circuit 211.
The subcode frame synchronization signal and the ATIP synchronization signal are
It is input to the phase comparator 210. The subcode frame synchronization signal represents, for example, a write address specified by the microcomputer, and the ATIP synchronization signal represents an actual address on the optical disc 101. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address on the optical disc 101.

The output signal of the phase comparator 210 is input to the gain adjustment circuit 211. The gain adjustment circuit 211
The gain of the output signal of the phase comparator 210 is adjusted. The output signal of the gain adjustment circuit 211 is input to the phase change circuit 202.

The phase change circuit 202 includes a gain adjustment circuit 2
A reference clock B having a constant phase (or frequency) and a changed phase (or frequency) is generated according to the output signal of the reference clock A. The phase change circuit 202
For example, it can be realized by a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211.

For example, consider a case where the phase of the ATIP synchronization signal is ahead of the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase lead flag according to the phase difference between the two signals. This phase advance flag means that the rotation speed of the optical disk 101 is faster than the timing of recording the write data.

Therefore, while the phase advance flag is being output from the phase comparator 210, the phase change circuit 202 is used to change the reference clock A by the amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal. The phase is delayed and a reference clock B is generated. The phase difference between the reference clock B with the delayed phase and the locked wobble signal indicating the rotation speed of the optical disk 101 is compared using the phase difference detection circuit 209. Since the rotation control circuit 111 operates in synchronization with the reference clock B, it acts in a direction to reduce the rotation speed of the optical disc 101.

Also, consider a case where the phase of the ATIP synchronization signal lags behind the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase delay flag according to the phase difference between the two signals. This phase delay flag means that the rotation speed of the optical disk 101 is slower than the timing of recording the write data.

Therefore, while the phase delay flag is being output from the phase comparator 210, the phase change circuit 202 is used to change the reference clock A by the amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal. The phase is advanced, and a reference clock B is generated. The phase difference between the reference clock B whose phase is advanced and the locked wobble signal indicating the rotation speed of the optical disk 101 is compared using the phase difference detection circuit 209. Since the rotation control circuit 111 operates in synchronization with the reference clock B, it acts in a direction to increase the rotation speed of the optical disc 101.

When the phase of the sub-code frame synchronization signal matches the phase of the ATIP synchronization signal,
Neither the phase advance flag nor the phase delay flag is output from the phase comparator 210. Therefore, the reference clock A is used as it is as the reference clock B and the phase change circuit 202
Output from

The wobble CLV control circuit 201 outputs a PWM (Pulse Width Modulation) signal for controlling a motor for rotating an optical disk based on the reference clocks A and B and a locked wobble signal.

The wobble CLV control circuit 201 has a PWM
Output circuit 204, adder 205, buffers 206, 20
7. It comprises a frequency difference detector 208 and a phase difference detector 209.

Here, in the present invention, the frequency difference detector 20
8, a reference clock A and a locked wobble signal are input. The reference clock A is an ATIP phase difference detection circuit 2
Since the frequency difference detector 208 is not affected by the output signal of the frequency difference 03, the frequency difference detector 208 can stably detect the frequency difference.

On the other hand, the reference clock B and the locked wobble signal are input to the phase difference detector 209. Since the reference clock B reflects the phase correction signal output from the ATIP phase difference detection circuit 203, control for matching the ATIP synchronization signal with the subcode frame synchronization signal can be performed.

The frequency difference detector 208 receives the reference clock A
Is compared with the frequency of the locked wobble signal, and an output signal corresponding to the frequency difference between the two is output. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal, and outputs an output signal according to the phase difference between the two.

The adder 205 adds the output signal of the frequency difference detector 208 and the output signal of the phase difference detector 209 and outputs the added result to the PWM output circuit 204. P
The WM output circuit 204 controls the motor for rotating the optical disk based on the output signal of the adder 205.
Output a signal.

As described above, according to the rotation control circuit of this embodiment, the frequency difference detector 208 in the wobble CLV control circuit 201 has a reference which is not affected by the phase correction signal output from the ATIP phase difference detection circuit 203. Clock A is input. In other words, when detecting the frequency difference, the information of the phase shift does not become a disturbance, so that the frequency difference detector 208
In this case, a stable frequency difference can be detected.

The phase difference detector 209 in the wobble CLV control circuit 201 has an ATIP phase difference detection circuit 20.
3, the reference clock B reflecting the phase correction signal is input. In other words, when the phase difference is detected, the information of the phase shift is reflected, so that control for matching the ATIP synchronization signal with the subcode frame synchronization signal can be performed.

3. Next, a first example of the rotation control method of the present invention will be described.

FIG. 3 shows an outline of the rotation control method of the present invention.

The rotation control method according to the present invention relates to a method for controlling the rotation of a disk during data writing, and more specifically, to a method for synchronizing a locked wobble signal and a reference clock.

First, the phase of the ATIP synchronization signal is compared with the phase of the subcode frame synchronization signal, and a phase difference between the two is detected (step ST1). Then, a phase correction signal is generated based on the phase difference (step ST
2) Based on the phase correction signal, a reference clock B in which the phase of the reference clock A is changed is generated (step ST3).

Here, for example, the phase correction signal can be composed of two types of signals, a phase advance flag and a phase delay flag.

In this case, when the phase of the ATIP synchronization signal is ahead of the phase of the subcode frame synchronization signal, the phase advance flag is set to the “H” level. While the phase advance flag is at the “H” level, the reference clock B is generated by delaying the phase of the reference clock A by a certain time.

When the phase of the ATIP synchronizing signal is behind the phase of the sub-code frame synchronizing signal, the phase delay flag goes to "H" level. While the phase delay flag is at the “H” level, a reference clock B in which the phase of the reference clock A is advanced by a certain time is generated.

Further, when the phase of the subcode frame synchronization signal coincides with the phase of the ATIP synchronization signal,
Both the phase advance flag and the phase delay flag become “L” level. While both the phase advance flag and the phase delay flag are at “L” level, the reference clock A becomes the reference clock B as it is.

Next, the frequency of the locked wobble signal is compared with the frequency of the reference clock A, the phase of the locked wobble signal is compared with the phase of the reference clock B, and the locked wobble signal and the reference clock A are compared. And the phase difference between the locked wobble signal and the reference clock B are detected (step ST4).

The rotation speed of the optical disk is controlled based on the frequency difference and the phase difference (step S).
T5). As a result, the subcode frame synchronization signal and the AT
It is possible to completely synchronize with the IP synchronization signal.

For example, as shown in FIG. 4, the frequency difference detector 208 outputs a current cycle of the locked wobble signal as a count value of the counter (the number of reference clocks A) 208A and a target cycle. (Target value = the number of reference clocks A) 208B, the difference between the current period (count value) of the locked wobble signal and the target value,
That is, it is composed of an arithmetic unit 208C for detecting a frequency difference.

The portion 208A for outputting the current cycle of the locked wobble signal as a count value includes, for example,
It has a circuit configuration as shown in FIG.

In the examples of FIGS. 4 and 5, the count value of the counter is taken into the latch circuit at the rising edge of the locked wobble signal, and the count value is cleared to the initial value with a slight delay. When the count value of the counter is cleared, again based on the reference clock A,
The count value of the counter is sequentially incremented from the initial value.

In this case, if the period (frequency) of the locked wobble signal does not match the target value, the count value latched by the latch circuit does not match the target value, as shown in FIG. Therefore, the frequency difference (= count value−target value) is calculated by the arithmetic unit 208C, and the rotation speed of the disk is controlled so that the frequency difference becomes zero.

For example, as shown in FIG. 7, the phase difference detector 209 outputs a current phase (position of a falling edge) of the locked wobble signal as a count value of the counter, a target 209A, and a target 209A. Phase, that is,
A part 20 for outputting the position (target value) of the falling edge
9B and an arithmetic unit 209C for detecting a difference between the current falling edge position (count value) of the locked wobble signal and the target value, that is, a phase difference.

The portion 209A that outputs the current phase of the locked wobble signal as a count value includes, for example,
It has a circuit configuration as shown in FIG.

In the examples of FIGS. 7 and 8, the count value of the counter is taken into the latch circuit at the falling edge of the locked wobble signal. Note that the count value of the counter is not cleared by the locked wobble signal and continues to count repeatedly from the initial value to the final value.

In this case, when the phase of the locked wobble signal (the position of the falling edge) does not match the target value, the count value and the target value latched by the latch circuit are changed as shown in FIG. ,It does not match. Therefore, the phase difference (= count value−target value) is calculated by the calculation unit 209C,
The rotation speed of the disk is controlled so that this phase difference becomes zero.

By employing the above rotation control method, the locked wobble signal and the reference clock can be accurately synchronized, and the write data can be accurately recorded at the address specified by the microcomputer. it can.

4. FIG. 10 shows a second example of the rotation control circuit 111 in the optical disk drive of FIG.

The rotation control circuit 111 includes a wobble CLV control circuit 201, a phase change circuit 202, and an ATIP phase difference detection circuit 203.

The ATIP phase difference detection circuit 203 comprises a phase comparator 210 and a gain adjustment circuit 211A. In this example, the gain adjustment circuit 211A has a threshold (dead zone), and does not output a phase correction signal when the output signal (or phase difference) of the phase comparator 210 is less than the threshold. .

Thus, for example, when the phase of the ATIP synchronizing signal and the phase of the subcode frame synchronizing signal are always minutely shifted, for example, when the optical disk has eccentricity, the phase correction signal is frequently output. , And stable rotation control can be performed.

Subcode frame synchronization signal and ATIP
The synchronization signal is input to the phase comparator 210. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address of the optical disc 101.

The output signal of phase comparator 210 is input to gain adjustment circuit 211A. Gain adjustment circuit 211A
Adjusts the gain of the output signal of the phase comparator 210.
However, when the phase difference is smaller than the threshold, the gain adjustment circuit 211A always sets the level of the output signal to zero. The output signal of the gain adjustment circuit 211A is
2 is input.

The phase change circuit 202 is provided with the gain adjustment circuit 2
Constant phase (or frequency) according to the output signal of 11A
A reference clock B is generated in which the phase (or frequency) of the reference clock A is changed. Phase change circuit 202
Can be realized by, for example, a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211A.

A wobble CLV control circuit 201 controls a motor for rotating an optical disk based on a reference clock B and a locked wobble signal.
Outputs WM (Pulse Width Modulation) signal.

The wobble CLV control circuit 201 has a PWM
Output circuit 204, adder 205, buffers 206, 20
7. It comprises a frequency difference detector 208 and a phase difference detector 209.

Frequency difference detector 208 and phase difference detector 2
09 is input with the reference clock B and the locked wobble signal, respectively. Since the reference clock B reflects the phase correction signal output from the ATIP phase difference detection circuit 203, control for matching the ATIP synchronization signal with the subcode frame synchronization signal can be performed.

The frequency difference detector 208 receives the reference clock B
Is compared with the frequency of the locked wobble signal, and an output signal corresponding to the frequency difference between the two is output. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal, and outputs an output signal according to the phase difference between the two.

The adder 205 adds the output signal of the frequency difference detector 208 and the output signal of the phase difference detector 209 and outputs the added result to the PWM output circuit 204. P
The WM output circuit 204 controls the motor for rotating the optical disk based on the output signal of the adder 205.
Output a signal.

FIG. 11 shows the gain adjustment circuit 211 of FIG.
3A shows an operation waveform.

In the figure, P1, P2, N1, N2
Is a threshold value. Also, the phase correction signal of FIG.
1 corresponds to a phase advance flag and a phase delay flag.

First, when the phase of the subcode frame synchronization signal matches the phase of the ATIP synchronization signal,
Both the phase advance flag and the phase delay flag are at “L” level. With this state as the initial state (precondition),
Hereinafter, the operation of the gain adjustment circuit when a phase shift occurs will be described.

(1) When the phase of the ATIP synchronization signal advances with respect to the phase of the subcode frame synchronization signal When the advance of the phase is smaller than the threshold value P1, the phase advance flag remains at "L" level. is there. The advance of the phase
When the phase advance flag becomes larger than the threshold value P1, the phase advance flag becomes “L”.
The level changes from “H” level to “H” level. At this time, the phase delay flag remains at “L” level.

While the phase advance flag is at the "H" level, a reference clock B in which the phase of the reference clock A is delayed by a predetermined time is generated.

When the phase advance flag is at "H" level and the advance of the phase of the ATIP synchronization signal with respect to the subcode frame synchronization signal is greater than threshold value P2, the phase advance flag maintains the "H" level. The phase advance is equal to the threshold P
When it becomes smaller than 2, the phase advance flag becomes “H”.
The level changes from “L” level to “L” level.

(2) When the phase of the ATIP synchronization signal lags behind the phase of the subcode frame synchronization signal When the phase lag is smaller than the threshold value N1, the phase lag flag remains at "L" level. is there. The phase lag is
When it becomes larger than the threshold value N1, the phase delay flag becomes “L”.
The level changes from “H” level to “H” level. At this time, the phase advance flag remains at “L” level.

While the phase delay flag is at the "H" level, the reference clock B is generated by advancing the phase of the reference clock A by a predetermined time.

When the phase delay flag is at the "H" level and the delay of the phase of the ATIP synchronization signal with respect to the subcode frame synchronization signal is greater than threshold value N2, the phase delay flag maintains the "H" level. The phase delay is equal to the threshold N
When it becomes smaller than 2, the phase delay flag becomes “H”.
The level changes from “L” level to “L” level.

As described above, if a dead zone is provided by means of a threshold value for a minute phase error in a steady state, the rotation control of the optical disk can be stably performed.

In this example, the gain adjustment circuit 211A
Although the dead zone is provided in the first embodiment, the same effect as in the present embodiment can be realized by, for example, a filter.

Even if a phase difference (including both leading and lagging) occurs between the subcode frame synchronization signal and the ATIP synchronization signal, if the phase difference is less than a predetermined value, the filter performs the phase difference. Has the function of setting

For example, as shown in FIG. 12, when a filter 211B is arranged in front of the gain adjustment circuit 211, the filter 211B uses the subcode frame synchronization signal and the AT
If the phase difference with the IP synchronization signal is less than a certain value,
The information that the phase difference is zero is sent to the gain adjustment circuit 211.
Give to.

As shown in FIG. 13, when a filter 211B is arranged after the gain adjustment circuit 211, the filter 211B transmits the subcode frame synchronization signal and the ATI
If the phase difference between the P synchronizing signal and the P synchronizing signal is smaller than a certain value, the phase correction signal (phase advance flag and phase delay flag) output from the gain adjustment circuit 211 is set to the “L” level.

In any case, a minute phase error in a steady state can be ignored, and stable rotation control can be realized.

As described above, according to the rotation control circuit of this embodiment, the AT
Gain adjustment circuit 211A in IP phase difference detection circuit 203
Is provided with a threshold (dead zone). For this reason, for example, when the phase of the ATIP synchronizing signal and the phase of the subcode frame synchronizing signal always have a slight deviation, such as when the optical disk is eccentric, the phase correction signal is frequently output. And stable rotation control can be performed.

[0113] 5. Next, a second example of the rotation control method of the present invention will be described.

FIG. 14 shows an outline of the rotation control method of the present invention.

The rotation control method of the present invention relates to a method of controlling the rotation of a disk at the time of writing data, and more specifically, to a method of synchronizing a locked wobble signal and a reference clock.

First, the phase of the ATIP synchronization signal is compared with the phase of the sub-code frame synchronization signal, and a phase difference between the two is detected (step ST1). Then, a phase correction signal is generated based on the phase difference (step ST
2) Based on the phase correction signal, a reference clock B in which the phase of the reference clock A is changed is generated (step ST3).

In the case of this example, the phase correction signal is composed of two types of signals, a phase advance flag and a phase delay flag, and the phase correction signal is output only when the phase difference is equal to or larger than the threshold value (phase correction signal). The advance flag or the phase delay flag becomes “H”.)

For example, if the phase of the ATIP synchronization signal is ahead of the phase of the subcode frame synchronization signal and the advance of the phase is equal to or greater than a threshold value (for example, P1, P2), the phase advance flag is set. Becomes "H" level. While the phase advance flag is at the “H” level, the reference clock B is generated by delaying the phase of the reference clock A by a certain time.

Also, the phase of the ATIP synchronization signal lags behind the phase of the subcode frame synchronization signal, and
If the phase delay is equal to or greater than a threshold value (eg, N1, N2), the phase delay flag goes to “H” level. While the phase delay flag is at the “H” level, a reference clock B in which the phase of the reference clock A is advanced by a certain time is generated.

Further, when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal match, and when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal are shifted, the phase difference is Threshold (P1,
(P2, N1, N2), both the phase advance flag and the phase delay flag are at "L" level. While both the phase advance flag and the phase delay flag are at “L” level, the reference clock A becomes the reference clock B as it is.

Next, the frequency of the locked wobble signal is compared with the frequency of the reference clock B, the phase of the locked wobble signal is compared with the phase of the reference clock B, and the locked wobble signal and the reference clock B are compared. And the phase difference between the locked wobble signal and the reference clock B are detected (step ST4).

Then, the rotational speed of the optical disk is controlled based on the frequency difference and the phase difference (step S).
T5). As a result, the subcode frame synchronization signal and the AT
It is possible to completely synchronize with the IP synchronization signal.

By employing the above-described rotation control method, the locked wobble signal can be accurately synchronized with the reference clock, and the write data can be accurately recorded at the address specified by the microcomputer. it can.

6. Rotation Control Circuit (Part 3) FIG. 15 shows a third example of the rotation control circuit 111 in the optical disk drive of FIG.

This embodiment is different from the rotation control circuit shown in FIG.
This is a combination of the features of the zero rotation control circuit.

The rotation control circuit 111 includes a wobble CLV control circuit 201, a phase change circuit 202, and an ATIP phase difference detection circuit 203.

The reference clock A is input to the frequency difference detector 208 in the wobble CLV control circuit 201, and the reference clock B is input to the phase difference detector 209 in the wobble CLV control circuit 201.

The gain adjustment circuit 211A in the ATIP phase difference detection circuit 203 has a threshold (dead zone), and when the phase difference is less than the threshold, sets the level of the output signal (phase correction signal) to zero.

As described above, the rotation control circuit shown in FIG.
Can be used in combination.

7. Phase Change Circuit Lastly, the phase change circuit used in the rotation control circuit of FIGS. 2, 10 and 15 will be briefly described.

FIG. 16 shows a phase change circuit used in the rotation control circuit of the present invention.

The phase change circuit 202 includes a plurality of frequency dividers 202A, 202B, 202C having different frequency division ratios.
And a selector 202E for determining the frequency division ratio of the reference clock A based on the phase correction signal.

In this example, the frequency of the reference clock A is divided into 1/6 by the frequency divider 202D, and as a result, the reference clock A 'is generated. Then, the reference clock A '
Is input to the frequency difference detector.

Therefore, when the phase correction signals (the phase advance flag and the phase delay flag) are both at "L" level, the frequency divider 202B is selected in the phase change circuit 202,
As a result, the reference clock B becomes the same as the reference clock A '.

When the phase advance flag is at "H" level, the frequency divider 202C is selected in the phase change circuit 202, and as a result, the phase of the reference clock B becomes the phase of the reference clock A '. It will be late compared.

When the phase delay flag is at "H" level, the frequency divider 202A is selected in the phase change circuit 202, and as a result, the phase of the reference clock B becomes the phase of the reference clock A '. It will advance in comparison.

Note that the timing generator 202F determines the time when the phase correction signal (phase advance flag and phase delay flag) becomes valid.

[0138]

As described above, according to the present invention, first, the wobble CLV is applied to the reference clock whose phase is changed according to the phase difference information between the ATIP synchronization signal and the subcode frame synchronization signal. Only the phase difference detector in the control circuit is inputted, and the frequency difference detector is inputted with the reference clock before the phase is changed according to the phase difference information. For this reason, when adjusting the frequency of the locked wobble signal to the frequency of the reference clock, disturbance due to the phase difference information does not occur, and the frequency difference can be detected stably. Further, the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal can be accurately matched.

Second, a threshold (dead zone) is provided in the gain adjustment circuit in the ATIP phase difference detection circuit, or
By providing a filter before or after the gain adjustment circuit, a minute phase shift in a steady state can be ignored, and stable rotation control can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an optical disk drive device of the present invention.

FIG. 2 is a diagram showing a first example of a rotation control circuit according to the present invention.

FIG. 3 is a diagram showing a first example of a rotation control method according to the present invention.

FIG. 4 is a diagram illustrating an example of a frequency difference detector.

FIG. 5 illustrates a portion 208A of the frequency difference detector of FIG.

FIG. 6 is a waveform chart showing the operation of the frequency difference detector of FIGS. 4 and 5;

FIG. 7 is a diagram illustrating an example of a phase difference detector.

FIG. 8 is a diagram showing a portion 209A of the phase difference detector of FIG. 7;

FIG. 9 is a waveform chart showing the operation of the phase difference detector of FIGS. 7 and 8.

FIG. 10 is a diagram showing a second example of the rotation control circuit of the present invention.

FIG. 11 is a waveform chart showing the operation of a gain adjustment circuit having a threshold.

FIG. 12 is a diagram showing a modification of the ATIP phase difference detection circuit.

FIG. 13 is a diagram showing a modification of the ATIP phase difference detection circuit.

FIG. 14 is a diagram showing a second example of the rotation control method according to the present invention.

FIG. 15 is a diagram showing a third example of the rotation control circuit of the present invention.

FIG. 16 is a diagram showing an example of a phase change circuit used for the rotation control circuit of the present invention.

FIG. 17 is a diagram showing a conventional optical disk drive device.

FIG. 18 is a diagram showing a conventional rotation control circuit.

[Explanation of symbols]

101: optical disk, 10
2: Pickup, 103
: Signal detection amplifier, 104
: ATIP decoder, 10
5: CD encoder, 10
6: laser drive circuit, 10
7: crystal oscillator, 108
: Frequency divider, 109
: Multiplication circuit, 110
: Timing generator, 111
: Rotation control circuit, 112
: Driver, 113
: Spindle motor, 201
: Wobble CLV control circuit, 202
: Phase change circuit, 203
: ATIP phase difference detection circuit, 204
: PWM output circuit, 205
: Adders, 206, 207
: Buffer, 208
: Frequency difference detector, 209
: Phase difference detector, 210
： Phase comparator, 211
: Gain adjustment circuit, 211A
: Gain adjustment circuit having a threshold value, 211B
:filter.

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H02P 5/00 301 H02P 5/00 301J F term (reference) 5D109 KA04 KB05 KB14 KD13 KD22 KD41 5H550 AA20 BB06 FF08 HA06 HB06 HB16 JJ02 JJ03 JJ11 JJ12 JJ14 JJ25 LL08 LL36

Claims (9)

[Claims] 1. A method for detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data, and correcting a phase based on the first phase difference. A phase difference detection circuit that outputs a signal, a phase change circuit that changes a phase of a first reference clock based on the phase correction signal, and outputs a second reference clock; A frequency difference detector for detecting a frequency difference between the third signal representing the rotation speed of the disk and a second signal between the second reference clock and the third signal;
A phase difference detector that detects a phase difference between the two, and an output circuit that outputs a fourth signal that controls a rotation speed of the disk based on the frequency difference and the second phase difference. And a rotation control circuit. 2. The rotation control circuit according to claim 1, wherein the fourth signal is output based on the first, second, and third signals, and a decoder that generates the first and third signals. ,
An optical disk drive device comprising: a timing generator that generates the second signal; and a driver that drives the optical disk based on the fourth signal. Detecting a first phase difference between a first signal representing an absolute address of the disk and a second signal representing a timing of write data; and detecting the first phase difference based on the first phase difference. Generating a phase correction signal; generating a second reference clock in which the phase of a first reference clock is changed based on the phase correction signal; and rotating the first reference clock and the disk. Detecting a frequency difference between a third signal representing speed and a second signal between the second reference clock and the third signal.
Detecting the phase difference of the disk, and controlling the rotation speed of the disk based on the frequency difference and the second phase difference. 4. A method for detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data, wherein the first phase difference is equal to or larger than a threshold value. A phase difference detection circuit that outputs a phase correction signal based on the first phase difference; and changes a phase of a first reference clock based on the phase correction signal to output a second reference clock. A phase change circuit; a frequency difference detector for detecting a frequency difference between the second reference clock and a third signal representing a rotation speed of the disk; a second reference clock and the third signal The second between
A phase difference detector that detects a phase difference between the two, and an output circuit that outputs a fourth signal that controls a rotation speed of the disk based on the frequency difference and the second phase difference. And a rotation control circuit. 5. The rotation control circuit according to claim 4, which outputs the fourth signal based on the first, second, and third signals, and a decoder that generates the first and third signals. ,
An optical disk drive device comprising: a timing generator that generates the second signal; and a driver that drives the optical disk based on the fourth signal. 6. detecting a first phase difference between a first signal representing an absolute address of the disk and a second signal representing the timing of write data; and wherein the first phase difference is equal to or greater than a threshold value. Generating a phase correction signal based on the first phase difference; and generating a second reference clock in which the phase of the first reference clock is changed based on the phase correction signal. Detecting a frequency difference between the second reference clock and a third signal representing the rotation speed of the disk; and detecting a second frequency difference between the second reference clock and the third signal.
Detecting the phase difference of the disk, and controlling the rotation speed of the disk based on the frequency difference and the second phase difference. 7. A method for detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data, wherein the first phase difference is equal to or larger than a threshold value. A phase difference detection circuit that outputs a phase correction signal based on the first phase difference; and changes a phase of a first reference clock based on the phase correction signal to output a second reference clock. A phase change circuit; a frequency difference detector for detecting a frequency difference between the first reference clock and a third signal representing a rotation speed of the disk; a second reference clock and the third signal The second between
A phase difference detector that detects a phase difference between the two, and an output circuit that outputs a fourth signal that controls a rotation speed of the disk based on the frequency difference and the second phase difference. And a rotation control circuit. 8. The rotation control circuit according to claim 7, which outputs the fourth signal based on the first, second, and third signals, and a decoder that generates the first and third signals. ,
An optical disk drive device comprising: a timing generator that generates the second signal; and a driver that drives the optical disk based on the fourth signal. 9. detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data; and wherein the first phase difference is equal to or greater than a threshold value. Generating a phase correction signal based on the first phase difference; and generating a second reference clock in which the phase of the first reference clock is changed based on the phase correction signal. Detecting a frequency difference between the first reference clock and a third signal representing a rotation speed of the disk; and detecting a second frequency difference between the second reference clock and the third signal.
Detecting the phase difference of the disk, and controlling the rotation speed of the disk based on the frequency difference and the second phase difference.