JP3998427B2 - Rotation control circuit, recordable optical disc drive apparatus using the same, and rotation control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a rotation control circuit, a recordable optical disc drive using the same, and a rotation control method.
[0002]
[Prior art]
In recent years, recordable optical discs such as CD-RW, MO, and DVD-RAM have been widely used as information recording media. In such an optical disc, when information is written, rotation control of the optical disc is important in order to accurately record write data at a predetermined address of the optical disc.
[0003]
A conventional example of an optical disk drive device that controls the rotation of a recordable optical disk will be described below.
[0004]
FIG. 17 shows an outline of a conventional optical disc drive apparatus. FIG. 18 shows a specific example of the rotation control circuit 111 in the optical disk drive apparatus of FIG.
[0005]
The rotation control circuit 111 includes a wobble CLV (wobble constant linear velocity) control circuit 201, a phase change circuit 202, and an ATIP (absolute time in pre-groove) phase difference detection circuit 203.
[0006]
The ATIP phase difference detection circuit 203 will be described.
[0007]
The ATIP phase difference detection circuit 203 includes a phase comparator 210 and a gain adjustment circuit 211. The subcode frame synchronization signal and the ATIP synchronization signal are input to the phase comparator 210. The subcode frame synchronization signal represents, for example, a write address designated by the microcomputer, and the ATIP synchronization signal represents an actual address of the optical disc 101. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address of the optical disc 101.
[0008]
The output signal of the phase comparator 210 is input to the gain adjustment circuit 211. The gain adjustment circuit 211 adjusts the gain of the output signal from the phase comparator 210. The output signal of the gain adjustment circuit 211 is input to the phase change circuit 202.
[0009]
The phase change circuit 202 generates a reference clock B in which the phase (or frequency) of the reference clock A having a constant phase (or frequency) is changed according to the output signal of the gain adjustment circuit 211. For example, the phase change circuit 202 can be realized by a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211.
[0010]
For example, consider a case where the phase of the ATIP synchronization signal is advanced with respect to the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase advance flag corresponding to the phase difference between the two signals. This phase advance flag means that the rotational speed of the optical disc 101 is faster than the timing for recording the write data.
[0011]
Therefore, while the phase advance flag is output from the phase comparator 210, the phase of the reference clock A is delayed by an amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal using the phase change circuit 202. The reference clock B is generated. Since this phase delay is directly reflected in the output signal of the phase difference detector 209, it acts in the direction of reducing the rotational speed of the optical disc 101.
[0012]
Consider a case where the phase of the ATIP synchronization signal is delayed with respect to the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase delay flag corresponding to the phase difference between the two signals. This phase delay flag means that the rotation speed of the optical disc 101 is slower than the timing for recording the write data.
[0013]
Therefore, while the phase lag flag is output from the phase comparator 210, the phase of the reference clock A is advanced by an amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal using the phase change circuit 202. The reference clock B is generated. The advance of the phase is directly reflected in the output signal of the phase difference detector 209, and thus acts in the direction of increasing the rotation speed of the optical disc 101.
[0014]
Further, when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal match, neither the phase advance flag nor the phase delay flag is output from the phase comparator 210. For this reason, the reference clock A is directly output from the phase change circuit 202 as the reference clock B.
[0015]
The wobble CLV control circuit 201 outputs a PWM (Pulse Width Modulation) signal for controlling the motor that rotates the optical disk based on the reference clock B and the locked wobble signal.
[0016]
The wobble CLV control circuit 201 includes a PWM output circuit 204, an adder 205, buffers 206 and 207, a frequency difference detector 208, and a phase difference detector 209.
[0017]
The reference clock B and the locked wobble signal are input to the frequency difference detector 208 and the phase difference detector 209, respectively. As described above, the reference clock B is generated by the reference clock A using the ATIP phase difference detection circuit 203 in order to correct the deviation between the write address designated by the microcomputer and the actual address on the optical disk. Signal. The locked wobble signal is a signal that is locked by a PLL to the mean frequency of the meandering grooves spirally engraved on the optical disk, and is a signal that represents the rotational speed of the optical disk.
[0018]
The frequency difference detector 208 compares the frequency of the reference clock B and the frequency of the locked wobble signal, and outputs an output signal corresponding to the frequency difference between the two. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal and outputs an output signal corresponding to the phase difference between the two.
[0019]
Adder 205 adds the output signal of frequency difference detector 208 and the output signal of phase difference detector 209, and outputs the addition result to PWM output circuit 204. The PWM output circuit 204 outputs a PWM signal for controlling the motor that rotates the optical disk based on the output signal of the adder 205.
[0020]
[Problems to be solved by the invention]
17 and 18, when information is recorded on the optical disk, if a disturbance (noise) enters the signal in the rotation control circuit 111, there is a problem that the information cannot be recorded at an accurate address.
[0021]
For example, in the optical disk drive device of FIGS. 17 and 18, the reference clock A is converted to the reference clock B based on the phase correction signal output from the ATIP phase difference detection circuit 203, and this reference clock B is controlled by the wobble CLV control. This is given to the circuit 201. That is, the phase-changed reference clock B is input to both the frequency difference detector 208 and the phase difference detector 209 in the wobble CLV control circuit 201.
[0022]
However, since the phase correction signal output from the ATIP phase difference detection circuit 203 is information on phase shift, if this phase correction signal is reflected in the frequency difference detector 208 in the wobble CLV control circuit 201, the frequency difference signal A disturbance occurs in the output signal of the detector 208.
[0023]
Further, the ATIP phase difference detection circuit 203 outputs a phase correction signal when there is a shift between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal. Here, for example, when the optical disk is eccentric, there is a shift between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal. Although this deviation is small, it always occurs during steady state, and as a result, phase correction signals are also frequently output. This phase correction signal becomes a disturbance.
[0024]
The present invention has been made to solve such a problem, and an object of the present invention is to eliminate the influence of the output signal of the ATIP phase difference detection circuit and to detect a stable frequency difference in the frequency difference detector. In addition, stable rotation control is performed even for a minute phase shift (jitter) in a steady state.
[0028]
[Means for Solving the Problems]
(1) The rotation control circuit according to the present invention detects a first phase difference between a first signal representing the absolute address of the disk and a second signal representing the timing of write data, and the first phase difference is a threshold value. In the above case, a phase difference detection circuit that outputs a phase correction signal based on the first phase difference, a phase of the first reference clock is changed based on the phase correction signal, and the second reference clock is changed. , A frequency difference detector for detecting a frequency difference between the second reference clock and a third signal representing the rotational speed of the disk, the second reference clock and the second A phase difference detector for detecting a second phase difference between the first and second signals, and a fourth signal for controlling the rotational speed of the disk based on the frequency difference and the second phase difference. And an output circuit.
[0029]
An optical disc drive apparatus according to the present invention includes: the rotation control circuit that outputs the fourth signal based on the first, second, and third signals; a decoder that generates the first and third signals; A timing generator for generating the second signal; and a driver for driving the optical disk based on the fourth signal.
[0030]
The rotation control method of the present invention includes a step of detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data, and the first phase difference. Generating a phase correction signal based on the first phase difference, and a second reference clock having a phase of the first reference clock changed based on the phase correction signal. Generating, a step of detecting a frequency difference between the second reference clock and a third signal representing the rotational speed of the disk, and between the second reference clock and the third signal. Detecting the second phase difference, and controlling the rotational speed of the disk based on the frequency difference and the second phase difference.
[0031]
(2) The rotation control circuit according to the present invention detects a first phase difference between a first signal representing the absolute address of the disk and a second signal representing the timing of write data, and the first phase difference is a threshold value. In the above case, a phase difference detection circuit that outputs a phase correction signal based on the first phase difference, a phase of the first reference clock is changed based on the phase correction signal, and the second reference clock is changed. , A frequency difference detector for detecting a frequency difference between the first reference clock and a third signal representing the rotational speed of the disk, the second reference clock and the second A phase difference detector for detecting a second phase difference between the first and second signals, and a fourth signal for controlling the rotational speed of the disk based on the frequency difference and the second phase difference. And an output circuit.
[0032]
An optical disc drive apparatus according to the present invention includes: the rotation control circuit that outputs the fourth signal based on the first, second, and third signals; a decoder that generates the first and third signals; A timing generator for generating the second signal; and a driver for driving the optical disk based on the fourth signal.
[0033]
The rotation control method of the present invention includes a step of detecting a first phase difference between a first signal representing an absolute address of a disk and a second signal representing a timing of write data, and the first phase difference. Generating a phase correction signal based on the first phase difference, and a second reference clock having a phase of the first reference clock changed based on the phase correction signal. Generating a frequency difference between the first reference clock and a third signal representing the rotational speed of the disk; and between the second reference clock and the third signal. Detecting the second phase difference, and controlling the rotational speed of the disk based on the frequency difference and the second phase difference.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a rotation control circuit of the present invention, a recordable optical disc drive apparatus using the same, and a rotation control method will be described with reference to the drawings.
[0035]
1. Optical disk drive device
FIG. 1 schematically shows an optical disk drive apparatus according to the present invention.
[0036]
On the optical disc 101, a pre-groove which is spiral and meanders at a predetermined period is engraved. By modulating the pregroove meandering, that is, the wobbling period, ATIP (Absolute Time In Pre-groove) corresponding to the address information on the optical disk 101 can be recorded.
[0037]
The wobbling on the optical disc 101 is formatted so that this ATIP is recorded in a 75 Hz frame. That is, in each frame, an absolute time based on the innermost circumference of the optical disc (absolute time) is recorded as a 42-bit absolute address.
[0038]
The absolute address is composed of 4-bit synchronization code, minute data consisting of 8-bit BCD (Binary Code Decimal), second data and frame data, and 14-bit CRC (Cyclic Redundancy Check) data. This is coded as an NRZ (Non Return to Zero) code having a bit rate of 3150 bits / second.
[0039]
The ATIP data is biphase mark modulated by a bit clock of 6.3 kHz and becomes a biphase signal. Further, when the biphase signal is frequency-modulated, an FM signal (wobble signal) having a carrier frequency of 22.05 Hz is obtained.
[0040]
The spindle motor 113 supports and rotates the optical disc 101. The pickup 102 irradiates the optical disc 101 with a laser beam, receives the reflected light from the optical disc 101, converts it into an electrical signal, and outputs it as an RF signal. The signal detection amplifier 103 processes the RF signal and outputs the above-described wobble signal.
[0041]
The wobble signal is input to the ATIP decoder 104. The ATIP decoder 104 outputs an ATIP synchronization signal based on the wobble signal, PLL locks to the carrier frequency of the wobble signal, and outputs a signal indicating the rotation speed of the optical disc 101 (hereinafter referred to as a locked wobble signal). To do. The ATIP synchronization signal and the locked wobble signal are input to the rotation control circuit 111.
[0042]
The crystal oscillator 107 generates a clock having a frequency of 22 MHz, for example. This clock is input to the frequency divider circuit 108 and the multiplier circuit 109.
[0043]
The frequency dividing circuit 108 outputs a clock obtained by dividing the frequency of the clock generated by the crystal oscillator 107 by 1 / N (N is a positive number) as the reference clock A. The multiplier circuit 109 outputs a clock obtained by multiplying the frequency of the clock generated by the crystal oscillator 107.
[0044]
The timing generator 110 receives the output clock of the multiplication circuit 109 and outputs a subcode frame synchronization signal and a timing signal for operating the CD encoder 105.
[0045]
The subcode frame synchronization signal is input to the rotation control circuit 111. The CD encoder 105 encodes write data based on the timing signal. That is, the CD encoder 105 performs EFM modulation on main data and subcode data, and outputs an EFM signal.
[0046]
The laser drive circuit 106 drives the pickup 102 based on the EFM signal output from the CD encoder 105, and determines the laser irradiation position. The laser drive circuit 106 controls the laser power, such as increasing the laser power during writing, based on the EFM signal output from the CD encoder 105.
[0047]
The rotation control circuit 111 outputs a PWM signal for controlling the rotation speed of the optical disc 101 based on the locked wobble signal, the reference clock A, the ATIP synchronization signal, and the subcode frame synchronization signal. In response to this PWM signal, the driver 112 actually drives the spindle motor 113 to control the rotation speed of the optical disc 101.
[0048]
2. Rotation control circuit (1)
FIG. 2 shows a first example of the rotation control circuit 111 in the optical disk drive apparatus of FIG.
[0049]
The rotation control circuit 111 includes a wobble CLV (wobble constant linear velocity) control circuit 201, a phase change circuit 202, and an ATIP (absolute time in pre-groove) phase difference detection circuit 203.
[0050]
The ATIP phase difference detection circuit 203 includes a phase comparator 210 and a gain adjustment circuit 211. The subcode frame synchronization signal and the ATIP synchronization signal are input to the phase comparator 210. The subcode frame synchronization signal represents, for example, a write address designated by the microcomputer, and the ATIP synchronization signal represents an actual address on the optical disc 101. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address on the optical disc 101.
[0051]
The output signal of the phase comparator 210 is input to the gain adjustment circuit 211. The gain adjustment circuit 211 adjusts the gain of the output signal from the phase comparator 210. The output signal of the gain adjustment circuit 211 is input to the phase change circuit 202.
[0052]
The phase change circuit 202 generates a reference clock B in which the phase (or frequency) of the reference clock A having a constant phase (or frequency) is changed according to the output signal of the gain adjustment circuit 211. For example, the phase change circuit 202 can be realized by a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211.
[0053]
For example, consider a case where the phase of the ATIP synchronization signal is advanced with respect to the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase advance flag corresponding to the phase difference between the two signals. This phase advance flag means that the rotational speed of the optical disc 101 is faster than the timing for recording the write data.
[0054]
Therefore, while the phase advance flag is output from the phase comparator 210, the phase of the reference clock A is delayed by an amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal using the phase change circuit 202. The reference clock B is generated. The phase difference detection circuit 209 is used to compare the phases of the reference clock B and the locked wobble signal representing the rotation speed of the optical disc 101. Since the rotation control circuit 111 operates in synchronization with the reference clock B, the rotation control circuit 111 acts in the direction of reducing the rotation speed of the optical disc 101.
[0055]
Consider a case where the phase of the ATIP synchronization signal is delayed with respect to the phase of the subcode frame synchronization signal. In this case, the phase comparator 210 outputs a phase delay flag corresponding to the phase difference between the two signals. This phase delay flag means that the rotation speed of the optical disc 101 is slower than the timing for recording the write data.
[0056]
Therefore, while the phase lag flag is output from the phase comparator 210, the phase of the reference clock A is advanced by an amount corresponding to the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal using the phase change circuit 202. The reference clock B is generated. The phase difference detection circuit 209 is used to compare the phases of the reference clock B with the advanced phase and the locked wobble signal indicating the rotation speed of the optical disc 101. Since the rotation control circuit 111 operates in synchronization with the reference clock B, it acts in the direction of increasing the rotation speed of the optical disc 101.
[0057]
Further, when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal match, neither the phase advance flag nor the phase delay flag is output from the phase comparator 210. For this reason, the reference clock A is directly output from the phase change circuit 202 as the reference clock B.
[0058]
The wobble CLV control circuit 201 outputs a PWM (Pulse Width Modulation) signal for controlling the motor that rotates the optical disk based on the reference clocks A and B and the locked wobble signal.
[0059]
The wobble CLV control circuit 201 includes a PWM output circuit 204, an adder 205, buffers 206 and 207, a frequency difference detector 208, and a phase difference detector 209.
[0060]
Here, in the present invention, the reference clock A and the locked wobble signal are input to the frequency difference detector 208. Since the reference clock A is not affected by the output signal of the ATIP phase difference detection circuit 203, the frequency difference detector 208 can stably detect the frequency difference.
[0061]
On the other hand, the reference clock B and the locked wobble signal are input to the phase difference detector 209. Since the reference clock B reflects the phase correction signal output from the ATIP phase difference detection circuit 203, it is possible to control the ATIP synchronization signal and the subcode frame synchronization signal to coincide with each other.
[0062]
The frequency difference detector 208 compares the frequency of the reference clock A and the frequency of the locked wobble signal, and outputs an output signal corresponding to the frequency difference between the two. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal and outputs an output signal corresponding to the phase difference between the two.
[0063]
Adder 205 adds the output signal of frequency difference detector 208 and the output signal of phase difference detector 209, and outputs the addition result to PWM output circuit 204. The PWM output circuit 204 outputs a PWM signal for controlling the motor that rotates the optical disk based on the output signal of the adder 205.
[0064]
As described above, according to the rotation control circuit of this example, the reference clock A that is not affected by the phase correction signal output from the ATIP phase difference detection circuit 203 is supplied to the frequency difference detector 208 in the wobble CLV control circuit 201. Entered. That is, when detecting the frequency difference, the information on the phase shift does not become disturbance, so that the frequency difference detector 208 can stably detect the frequency difference.
[0065]
A reference clock B reflecting the phase correction signal output from the ATIP phase difference detection circuit 203 is input to the phase difference detector 209 in the wobble CLV control circuit 201. That is, when detecting the phase difference, information on the phase shift is reflected, so that the ATIP synchronization signal and the subcode frame synchronization signal can be controlled to coincide with each other.
[0066]
3. Rotation control method (1)
Next, a first example of the rotation control method of the present invention will be described.
[0067]
FIG. 3 shows an outline of the rotation control method of the present invention.
[0068]
The rotation control method of the present invention relates to a disk rotation control method at the time of data writing, and more specifically, to a synchronization method of a locked wobble signal and a reference clock.
[0069]
First, the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal are compared, and the phase difference between the two is detected (step ST1). A phase correction signal is generated based on this phase difference (step ST2), and a reference clock B in which the phase of the reference clock A is changed is generated based on this phase correction signal (step ST3). .
[0070]
Here, for example, the phase correction signal can be composed of two types of signals, a phase advance flag and a phase delay flag.
[0071]
In this case, when the phase of the ATIP synchronization signal is advanced with respect to the phase of the subcode frame synchronization signal, the phase advance flag becomes “H” level. While the phase advance flag is at the “H” level, the reference clock B in which the phase of the reference clock A is delayed by a certain time is generated.
[0072]
In addition, when the phase of the ATIP synchronization signal is delayed with respect to the phase of the subcode frame synchronization signal, the phase delay flag becomes “H” level. While the phase delay flag is at the “H” level, the reference clock B is generated by advancing the phase of the reference clock A by a predetermined time.
[0073]
Further, when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal match, both the phase advance flag and the phase delay flag become “L” level. While both the phase advance flag and the phase delay flag are at “L” level, the reference clock A becomes the reference clock B as it is.
[0074]
Next, the frequency of the locked wobble signal is compared with the frequency of the reference clock A, the phase of the locked wobble signal is compared with the phase of the reference clock B, and the frequency difference between the locked wobble signal and the reference clock A is compared. Then, the phase difference between the locked wobble signal and the reference clock B is detected (step ST4).
[0075]
Based on these frequency difference and phase difference, the rotation speed of the optical disc is controlled (step ST5). As a result, the subcode frame synchronization signal and the ATIP synchronization signal can be completely synchronized.
[0076]
For example, as shown in FIG. 4, the frequency difference detector 208 includes a portion 208A that outputs the current period of the locked wobble signal as a counter count value (number of reference clocks A), and a target period (target value). = Number of reference clocks A) and a calculation unit 208C that detects a difference between the current period (count value) of the locked wobble signal and the target value, that is, a frequency difference.
[0077]
The portion 208A that outputs the current period of the locked wobble signal as a count value has a circuit configuration as shown in FIG. 5, for example.
[0078]
In the example of FIGS. 4 and 5, the count value of the counter is taken into the latch circuit at the rising edge of the locked wobble signal, and this count value is cleared to the initial value with a slight delay. When the count value of the counter is cleared, the count value of the counter is sequentially incremented from the initial value again based on the reference clock A.
[0079]
In this case, when the period (frequency) of the locked wobble signal does not match the target value, the count value latched in the latch circuit and the target value do not match as shown in FIG. Therefore, the frequency difference (= count value−target value) is calculated by the calculation unit 208C, and the rotational speed of the disk is controlled so that this frequency difference becomes zero.
[0080]
Further, for example, as shown in FIG. 7, the phase difference detector 209 includes a portion 209A that outputs the current phase (the position of the falling edge) of the locked wobble signal as the count value of the counter, the target phase, That is, the portion 209B that outputs the position (target value) of the falling edge and the arithmetic unit that detects the difference between the current falling edge position (count value) of the locked wobble signal and the target value, that is, the phase difference. 209C.
[0081]
The portion 209A that outputs the current phase of the locked wobble signal as a count value has a circuit configuration as shown in FIG. 8, for example.
[0082]
In the example of FIGS. 7 and 8, the count value of the counter is taken into the latch circuit at the falling edge of the locked wobble signal. Note that the count value of the counter is continuously cleared from the initial value to the final value without being cleared by the locked wobble signal.
[0083]
In this case, if the phase of the locked wobble signal (falling edge position) does not match the target value, the count value latched in the latch circuit does not match the target value, as shown in FIG. . Therefore, the phase difference (= count value−target value) is calculated by the calculation unit 209C, and the rotational speed of the disk is controlled so that this phase difference becomes zero.
[0084]
By adopting the above rotation control method, the locked wobble signal and the reference clock can be accurately synchronized, and the write data can be accurately recorded at the address designated by the microcomputer.
[0085]
4). Rotation control circuit (2)
FIG. 10 shows a second example of the rotation control circuit 111 in the optical disc drive apparatus of FIG.
[0086]
The rotation control circuit 111 includes a wobble CLV control circuit 201, a phase change circuit 202, and an ATIP phase difference detection circuit 203.
[0087]
The ATIP phase difference detection circuit 203 includes a phase comparator 210 and a gain adjustment circuit 211A. In this example, the gain adjustment circuit 211A has a threshold (dead zone), and does not output a phase correction signal when the output signal (or phase difference) of the phase comparator 210 is less than the threshold. .
[0088]
As a result, for example, when the optical disk is eccentric, a phase correction signal is frequently output when there is always a slight deviation between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal. Therefore, stable rotation control can be performed.
[0089]
The subcode frame synchronization signal and the ATIP synchronization signal are input to the phase comparator 210. The phase comparator 210 compares the phases of the two signals and outputs a signal corresponding to the phase difference, thereby contributing to eliminating the deviation between the write address and the actual address of the optical disc 101.
[0090]
The output signal of the phase comparator 210 is input to the gain adjustment circuit 211A. The gain adjustment circuit 211A adjusts the gain of the output signal of the phase comparator 210. However, the gain adjustment circuit 211A always sets the level of the output signal to zero when the phase difference is less than the threshold value. The output signal of the gain adjustment circuit 211A is input to the phase change circuit 202.
[0091]
The phase change circuit 202 generates a reference clock B in which the phase (or frequency) of the reference clock A having a constant phase (or frequency) is changed according to the output signal of the gain adjustment circuit 211A. The phase change circuit 202 can be realized, for example, by a frequency divider whose frequency division ratio changes intermittently according to the output signal of the gain adjustment circuit 211A.
[0092]
The wobble CLV control circuit 201 outputs a PWM (Pulse Width Modulation) signal for controlling the motor that rotates the optical disk based on the reference clock B and the locked wobble signal.
[0093]
The wobble CLV control circuit 201 includes a PWM output circuit 204, an adder 205, buffers 206 and 207, a frequency difference detector 208, and a phase difference detector 209.
[0094]
A reference clock B and a locked wobble signal are input to the frequency difference detector 208 and the phase difference detector 209, respectively. Since the reference clock B reflects the phase correction signal output from the ATIP phase difference detection circuit 203, it is possible to control the ATIP synchronization signal and the subcode frame synchronization signal to coincide with each other.
[0095]
The frequency difference detector 208 compares the frequency of the reference clock B and the frequency of the locked wobble signal, and outputs an output signal corresponding to the frequency difference between the two. The phase difference detector 209 compares the phase of the reference clock B with the phase of the locked wobble signal and outputs an output signal corresponding to the phase difference between the two.
[0096]
Adder 205 adds the output signal of frequency difference detector 208 and the output signal of phase difference detector 209, and outputs the addition result to PWM output circuit 204. The PWM output circuit 204 outputs a PWM signal for controlling the motor that rotates the optical disk based on the output signal of the adder 205.
[0097]
FIG. 11 shows an operation waveform of the gain adjustment circuit 211A of FIG.
[0098]
In the figure, P1, P2, N1, and N2 are threshold values. Further, the phase correction signal in FIG. 10 corresponds to the phase advance flag and the phase delay flag in FIG.
[0099]
First, when the phase of the subcode frame synchronization signal matches the phase of the ATIP synchronization signal, both the phase advance flag and the phase delay flag are at the “L” level. With this state as the initial state (precondition), the operation of the gain adjustment circuit when a phase shift occurs will be described below.
[0100]
(1) When the phase of the ATIP sync signal is advanced relative to the phase of the subcode frame sync signal
When the phase advance is smaller than the threshold value P1, the phase advance flag remains at the “L” level. When the phase advance becomes larger than the threshold value P1, the phase advance flag changes from the “L” level to the “H” level. At this time, the phase delay flag remains at the “L” level.
[0101]
While the phase advance flag is at the “H” level, the reference clock B in which the phase of the reference clock A is delayed by a certain time is generated.
[0102]
When the phase advance flag is “H” level and the phase advance of the ATIP synchronization signal with respect to the subcode frame synchronization signal is larger than the threshold value P2, the phase advance flag maintains the “H” level. When the phase advance becomes smaller than the threshold value P2, the phase advance flag changes from the “H” level to the “L” level.
[0103]
(2) When the phase of the ATIP sync signal is delayed with respect to the phase of the subcode frame sync signal
When the phase delay is smaller than the threshold value N1, the phase delay flag remains at the “L” level. When the phase delay becomes larger than the threshold value N1, the phase delay flag changes from the “L” level to the “H” level. At this time, the phase advance flag remains at the “L” level.
[0104]
While the phase delay flag is at the “H” level, the reference clock B is generated by advancing the phase of the reference clock A by a predetermined time.
[0105]
When the phase delay flag is at “H” level and the phase delay of the ATIP synchronization signal with respect to the subcode frame synchronization signal is larger than the threshold value N2, the phase delay flag maintains the “H” level. When the phase delay becomes smaller than the threshold value N2, the phase delay flag changes from the “H” level to the “L” level.
[0106]
As described above, if a dead zone is provided by means of a threshold for a minute phase error in a steady state, the rotation control of the optical disk can be stably performed.
[0107]
In this example, the dead zone is provided in the gain adjustment circuit 211A. However, the same effect as this example can be realized by a filter, for example.
[0108]
The filter sets the phase difference to zero when the phase difference (including both of the advance and lag) occurs between the subcode frame synchronization signal and the ATIP synchronization signal when the phase difference is less than a certain value. It has the function to do.
[0109]
For example, as shown in FIG. 12, when the filter 211B is arranged in front of the gain adjustment circuit 211, the filter 211B is used when the phase difference between the subcode frame synchronization signal and the ATIP synchronization signal is less than a certain value. Information that the phase difference is zero is given to the gain adjustment circuit 211.
[0110]
Further, as shown in FIG. 13, when the filter 211B is arranged after the gain adjustment circuit 211, the filter 211B has a phase difference of less than a certain value between the subcode frame synchronization signal and the ATIP synchronization signal. The phase correction signal (phase advance flag and phase lag flag) output from the gain adjustment circuit 211 is set to the “L” level.
[0111]
In either case, a minute phase error in the steady state can be ignored, and stable rotation control can be realized.
[0112]
As described above, according to the rotation control circuit of this example, the threshold value (dead zone) is provided in the gain adjustment circuit 211A in the ATIP phase difference detection circuit 203. For this reason, for example, when the optical disk is decentered, the phase correction signal is frequently output when there is always a slight deviation between the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal. Therefore, stable rotation control can be performed.
[0113]
5). Rotation control method (2)
Next, a second example of the rotation control method of the present invention will be described.
[0114]
FIG. 14 shows an outline of the rotation control method of the present invention.
[0115]
The rotation control method of the present invention relates to a disk rotation control method at the time of data writing, and more specifically, to a synchronization method of a locked wobble signal and a reference clock.
[0116]
First, the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal are compared, and the phase difference between the two is detected (step ST1). A phase correction signal is generated based on this phase difference (step ST2), and a reference clock B in which the phase of the reference clock A is changed is generated based on this phase correction signal (step ST3). .
[0117]
In the case of this example, the phase correction signal is composed of two types of signals, ie, a phase advance flag and a phase delay flag, and the phase correction signal is output only when the phase difference is equal to or greater than the threshold (phase advance flag or The phase lag flag becomes “H”.)
[0118]
For example, when the phase of the ATIP synchronization signal is advanced with respect to the phase of the subcode frame synchronization signal and the advance of the phase is greater than or equal to a threshold value (for example, P1, P2), the phase advance flag is set to “H”. "Become level. While the phase advance flag is at the “H” level, the reference clock B in which the phase of the reference clock A is delayed by a certain time is generated.
[0119]
When the phase of the ATIP synchronization signal is delayed with respect to the phase of the subcode frame synchronization signal and the phase delay is equal to or greater than a threshold value (for example, N1, N2), the phase delay flag is set to “H”. "Become level. While the phase delay flag is at the “H” level, the reference clock B is generated by advancing the phase of the reference clock A by a predetermined time.
[0120]
Further, when the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal are the same, and the phase of the subcode frame synchronization signal and the phase of the ATIP synchronization signal are shifted, the phase difference is the threshold value (P1 , P2, N1, and N2), both the phase advance flag and the phase lag flag are at the “L” level. While both the phase advance flag and the phase delay flag are at “L” level, the reference clock A becomes the reference clock B as it is.
[0121]
Next, the frequency of the locked wobble signal is compared with the frequency of the reference clock B, the phase of the locked wobble signal is compared with the phase of the reference clock B, and the frequency difference between the locked wobble signal and the reference clock B is compared. Then, the phase difference between the locked wobble signal and the reference clock B is detected (step ST4).
[0122]
Based on these frequency difference and phase difference, the rotation speed of the optical disc is controlled (step ST5). As a result, the subcode frame synchronization signal and the ATIP synchronization signal can be completely synchronized.
[0123]
By adopting the above rotation control method, the locked wobble signal and the reference clock can be accurately synchronized, and the write data can be accurately recorded at the address designated by the microcomputer.
[0124]
6). Rotation control circuit (3)
FIG. 15 shows a third example of the rotation control circuit 111 in the optical disc drive apparatus of FIG.
[0125]
In this example, the features of the rotation control circuit of FIG. 2 and the features of the rotation control circuit of FIG. 10 are combined.
[0126]
The rotation control circuit 111 includes a wobble CLV control circuit 201, a phase change circuit 202, and an ATIP phase difference detection circuit 203.
[0127]
The reference clock A is input to the frequency difference detector 208 in the wobble CLV control circuit 201, and the reference clock B is input to the phase difference detector 209 in the wobble CLV control circuit 201.
[0128]
The gain adjustment circuit 211A in the ATIP phase difference detection circuit 203 has a threshold value (dead zone), and when the phase difference is less than the threshold value, the level of the output signal (phase correction signal) is set to zero.
[0129]
Thus, the rotation control circuit of FIG. 2 and the rotation control circuit of FIG. 10 can be used in combination.
[0130]
7). Phase change circuit
Finally, the phase change circuit used in the rotation control circuit of FIGS. 2, 10, and 15 will be briefly described.
[0131]
FIG. 16 shows a phase change circuit used in the rotation control circuit of the present invention.
[0132]
The phase change circuit 202 includes a plurality of frequency dividers 202A, 202B, and 202C having different frequency division ratios, and a selector 202E that determines the frequency division ratio of the reference clock A based on the phase correction signal.
[0133]
In this example, the frequency of the reference clock A is divided by 1/6 by the frequency divider 202D, and as a result, the reference clock A ′ is generated. Then, the reference clock A ′ is input to the frequency difference detector.
[0134]
Therefore, when both of the phase correction signals (phase advance flag and phase delay flag) are at the “L” level, the frequency divider 202B is selected in the phase change circuit 202. As a result, the reference clock B is the reference clock. Same as A '.
[0135]
When the phase advance flag is at the “H” level, the frequency divider 202C is selected in the phase change circuit 202, and as a result, the phase of the reference clock B is delayed compared to the phase of the reference clock A ′. It will be.
[0136]
When the phase delay flag is at “H” level, the frequency divider 202A is selected in the phase change circuit 202, and as a result, the phase of the reference clock B advances compared to the phase of the reference clock A ′. It will be.
[0137]
The timing generator 202F determines the time for which the phase correction signal (phase advance flag and phase delay flag) is valid.
[0138]
【The invention's effect】
As described above, according to the present invention, first, the reference clock whose phase is changed according to the phase difference information between the ATIP synchronization signal and the subcode frame synchronization signal is the level in the wobble CLV control circuit. Only the phase difference detector is inputted, and the frequency difference detector is inputted with a reference clock before the phase is changed in accordance with the phase difference information. For this reason, when adjusting the frequency of the locked wobble signal to the frequency of the reference clock, disturbance due to phase difference information does not occur, and the frequency difference can be detected stably. Also, the phase of the ATIP synchronization signal and the phase of the subcode frame synchronization signal can be accurately matched.
[0139]
Second, by providing a threshold value (dead zone) in the gain adjustment circuit in the ATIP phase difference detection circuit, or by providing a filter before or after the gain adjustment circuit, a small phase shift in the steady state is ignored. And stable rotation control can be performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing an optical disk drive device of the present invention.
FIG. 2 is a diagram showing a first example of a rotation control circuit of the present invention.
FIG. 3 is a diagram showing a first example of a rotation control method of the present invention.
FIG. 4 is a diagram illustrating an example of a frequency difference detector.
5 shows a portion 208A of the frequency difference detector of FIG.
6 is a waveform diagram showing the operation of the frequency difference detector of FIGS. 4 and 5. FIG.
FIG. 7 is a diagram illustrating an example of a phase difference detector.
FIG. 8 is a diagram showing a portion 209A of the phase difference detector of FIG.
9 is a waveform diagram showing an operation of the phase difference detector of FIGS. 7 and 8. FIG.
FIG. 10 is a diagram showing a second example of the rotation control circuit of the present invention.
FIG. 11 is a waveform diagram showing the operation of a gain adjustment circuit having a threshold value.
FIG. 12 is a view showing a modification of the ATIP phase difference detection circuit.
FIG. 13 is a view showing a modification of the ATIP phase difference detection circuit.
FIG. 14 is a diagram showing a second example of the rotation control method of the present invention.
FIG. 15 is a diagram showing a third example of the rotation control circuit of the present invention.
FIG. 16 is a diagram showing an example of a phase change circuit used in the rotation control circuit of the present invention.
FIG. 17 is a diagram showing a conventional optical disc drive apparatus.
FIG. 18 is a diagram showing a conventional rotation control circuit.
[Explanation of symbols]
101: Optical disc,
102: pickup,
103: Signal detection amplifier,
104: ATIP decoder,
105: CD encoder,
106: a laser driving circuit,
107: Crystal oscillator,
108: Frequency divider circuit,
109: Multiplication circuit,
110: Timing generator,
111: Rotation control circuit,
112: Driver,
113: spindle motor,
201: a wobble CLV control circuit,
202: Phase change circuit,
203: ATIP phase difference detection circuit,
204: PWM output circuit,
205: Adder,
206, 207: buffer,
208: Frequency difference detector,
209: Phase difference detector,
210: Phase comparator,
211: Gain adjustment circuit,
211A: a gain adjusting circuit having a threshold value,
211B: Filter.

Claims (6)

A first phase difference between a first signal that represents the absolute address of the disk and a second signal that represents the timing of the write data is detected, and the first phase difference is greater than or equal to a threshold value. A phase difference detection circuit that outputs a phase correction signal based on the phase difference of
A phase change circuit that changes the phase of the first reference clock and outputs a second reference clock based on the phase correction signal;
A frequency difference detector for detecting a frequency difference between the second reference clock and a third signal representing the rotational speed of the disk;
A phase difference detector for detecting a second phase difference between the second reference clock and the third signal;
An output circuit for outputting a fourth signal for controlling the rotational speed of the disk based on the frequency difference and the second phase difference; The rotation control circuit according to claim 1 , wherein the fourth signal is output based on the first, second, and third signals, a decoder that generates the first and third signals, and the second signal An optical disc drive apparatus comprising: a timing generator that generates a signal; and a driver that drives the optical disc based on the fourth signal. Detecting a first phase difference between a first signal representing the absolute address of the disk and a second signal representing the timing of the write data;
Generating a phase correction signal based on the first phase difference when the first phase difference is greater than or equal to a threshold;
Generating a second reference clock in which the phase of the first reference clock is changed based on the phase correction signal;
Detecting a frequency difference between the second reference clock and a third signal representing the rotational speed of the disk;
Detecting a second phase difference between the second reference clock and the third signal;
And a step of controlling a rotational speed of the disk based on the frequency difference and the second phase difference. A first phase difference between a first signal that represents the absolute address of the disk and a second signal that represents the timing of the write data is detected, and the first phase difference is greater than or equal to a threshold value. A phase difference detection circuit that outputs a phase correction signal based on the phase difference of
A phase change circuit that changes the phase of the first reference clock and outputs a second reference clock based on the phase correction signal;
A frequency difference detector for detecting a frequency difference between the first reference clock and a third signal representing the rotational speed of the disk;
A phase difference detector for detecting a second phase difference between the second reference clock and the third signal;
An output circuit for outputting a fourth signal for controlling the rotational speed of the disk based on the frequency difference and the second phase difference; 5. The rotation control circuit according to claim 4, wherein the fourth signal is output based on the first, second, and third signals, a decoder that generates the first and third signals, and the second signal An optical disc drive apparatus comprising: a timing generator that generates a signal; and a driver that drives the optical disc based on the fourth signal. Detecting a first phase difference between a first signal representing the absolute address of the disk and a second signal representing the timing of the write data;
Generating a phase correction signal based on the first phase difference when the first phase difference is greater than or equal to a threshold;
Generating a second reference clock in which the phase of the first reference clock is changed based on the phase correction signal;
Detecting a frequency difference between the first reference clock and a third signal representing the rotational speed of the disk;
Detecting a second phase difference between the second reference clock and the third signal;
And a step of controlling a rotational speed of the disk based on the frequency difference and the second phase difference.

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