JP2002269162A - Action synthesizing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an action synthesizing method for enabling optimal circuit design by canceling the defect of conventional technology that a satisfactory circuit can not be provided since synthesis makes redundant descriptions increase as it is because of a difference in the features of SAW and H/W in a conventional action synthesizing method. SOLUTION: A loop sentence (sentence starting with 'for' and sentence starting with 'while', for example,) having a description (data-a, data-b and buffer, for example,) on an array is automatically detected out of a source written with descriptions capable of action synthesis, and a circuit structure is divided and made parallel for the unit of group from a number of times of loop having a description on substitution and a number of times of loop having a description on reference. Thus, a register can be discarded and the reduction of a circuit area and acceleration can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for behavioral synthesis, and more particularly, to analyzing a C algorithm at the time of behavioral synthesis to obtain a redundant array or the like resulting from a difference in software (S / W) and hardware (H / W) characteristics. The present invention relates to a method and an apparatus for automatically optimizing a logic circuit design by eliminating a description.

[0002]

2. Description of the Related Art With the advance of computer technology, CAD
(Computer-Aided Design) It is common to design, analyze, and evaluate a logic circuit using a system. Conventional techniques in such a technical field are disclosed in, for example, "Design Supporting Apparatus" in JP-A-9-106407 and "Logic Synthesizing Apparatus" in JP-A-2000-172730.

When performing behavioral synthesis using a behavioral synthesis tool, an input description written in a behavioral level description language including information necessary for H / W conversion such as an input port and a bit width of a variable is used. Must be prepared. FIG. 10 shows an example of a source written in a software language. FIG.
Is originally written in a software language as shown in FIG. 10 and rewritten into an input description capable of behavioral synthesis. In the second line in FIG.
Is a function representing the output port, and ter (α to β) is the MSB
It is a function that declares the terminal signals of α and LSBβ. The mem (α to β) in the third line is MSBα and LSB
Function to declare memory of β. Also, reg (α to
β) is a function that declares the registers of MSBα and LSBβ.

When an input description capable of behavioral synthesis as shown in FIG. 11 is prepared, behavioral synthesis is performed according to a flowchart of FIG. 12 showing a procedure of a conventional behavioral synthesis method. Here, a conventional behavioral synthesis method will be described below with reference to FIG. 12 using the input description of FIG. 11 as an example.

In FIG. 12, first, a syntax analysis of the prepared input description capable of behavioral synthesis is performed (step A1).
Subsequently, it is determined whether or not there is an array in the description (source) (step A2). If there is an array (step A2:
In Yes, it is determined from the declaration of the array whether it is realized by a memory or a register (step A).
3). In the example of FIG. 11, both the array tmp and out_mem are mem (0 t
o 7) Since out_mem [N] and mem (0 to 7) tmp [M] are described, the memory is designed as an 8-bit memory. If this is desired to be used as a register, it can be described as reg (0 to 7) out_mem [N] (step A5). After the array is realized in the memory (step A4), a control data flow graph (hereinafter, referred to as CDFG) is generated (step A4).
6). This CDFG is used when performing resource binding and scheduling processing (step A7).

FIG. 13 shows the CDFG of the example shown in FIG. The block B_01 in FIG.
8 and 9 and is repeated M times by a loop statement. Block B_02 corresponds to the 10th and 11th lines in FIG. 11, and is repeated N times by a loop statement. Thus, the loop description of FIG. 11 is divided into two blocks B_01 and B_02.

Next, resource binding and scheduling are performed based on the CDFG of FIG. 13 (step A7). Here, mapping and sharing of a computing unit, a register, a multiplexer, and the like are performed based on a circuit frequency and a computing unit constraint that are synthesis constraints.
FIG. 14 shows the circuit diagram obtained in step A7. Finally, the synthesized circuit configuration can be directly transferred to a register transfer level (R
The description in the H / W description language of (TL) is output, and the behavioral synthesis ends (step A8).

[0008]

SUMMARY OF THE INVENTION Software (S /
The major difference between W) and hardware (H / W) is that S / W
Is that H / W can perform processing in parallel, while processing can be performed only sequentially. For example, from the S / W description in FIG.
When the description is changed to the H / W-like description shown in (1), it is necessary to execute the “for statement” M times and then N times. Even if the processing in the “for statement” is completed in one clock, (M +
N) It takes time corresponding to the clock. But H
/ W allows parallel processing, so for example, two “for
Sentence "is divided into two, and the parallel processing is performed.
(M + N) / 2 clocks, so that a circuit with twice the processing speed can be designed by itself.

Further, in the conventional behavioral synthesis method, the arrays tmp and out_mem in FIG. 11 can be selected from either all memories or all registers. Therefore, when the number of elements in the array is large, there is a problem that the processing speed of the circuit is deteriorated by using a memory, and the circuit area is deteriorated by using a register. As described above, in the conventional behavioral synthesis tool, there is a problem that if the synthesis is performed as it is, the redundant description increases and an excellent circuit cannot be obtained due to the difference between the S / W and H / W characteristics.

[0010]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and a behavioral synthesis method capable of further optimal circuit design by adding a function of optimizing a C algorithm. The purpose is to provide.

[0011]

According to the behavioral synthesis method of the present invention, a loop statement having a description related to an array is automatically detected from a source described in a behaviorally synthesizable description, and the detected array is substituted. Based on the number of loops in a loop statement with a reference statement and the number of loop statements in a reference statement, the circuit structure related to the loop description is divided into groups and parallelized, eliminating redundant registers and sharing. I do.

According to a preferred embodiment of the behavioral synthesis method of the present invention, the above-described division is performed by dividing a loop sentence having a large number of loops in accordance with a loop unit having a small number of loops. Also, the array is divided according to the division. The divided loop statements are grouped into groups by the dependency of the loop statements to eliminate redundant arrays. If there is no description regarding the assignment and reference of the array in the loop statement, it is selected whether the array is realized by a memory or a register.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of the behavioral synthesis method according to the present invention will be described below in detail with reference to the accompanying drawings.

First, a description will be given of a case where a source written with the behavioral synthesizable description shown in FIG. 5 is performed by a conventional behavioral synthesis method. FIG. 6 shows a circuit diagram obtained by synthesizing FIG. 5 by the conventional behavioral synthesis method. (Note that the circuit itself is not the subject of the present invention, and therefore detailed description is omitted. The same applies to many circuits described below. ). B_02 in FIG. 6 is a sub-function
This is a part that performs read processing, loops 64 times in the sub function, and is called 30 times from the main function. Therefore, B
The loop count of —02 is 64 × 30 = 1920. B_03 is a part that performs processing of the sub-function cal, loops 32 times in the sub-function, and 1
Since it is called five times, the loop count of B_03 is 32
× 15 = 480 times. And B_ of the data output unit
Since the number of loops of 01 is 480, the total number of loops is 1920 + 480 + 480 = 2880.

FIG. 1 is a flowchart showing the procedure of a preferred embodiment of the behavioral synthesis method according to the present invention. A case in which behavioral synthesis is performed according to this flowchart will be described. First, a syntax that can be synthesized is input and syntax analysis is performed (step B1). Thereafter, it is confirmed whether or not the source has an array (step B2). In FIG. 5, the third line,
In the fourth row, there are arrays data_a, data_b, and buffer (step B2: Yes), so the process proceeds to step B3. Then, it is confirmed whether or not a description relating to array assignment and reference exists in the loop statement (step B3). Arrays data_a and da
ta_b is substituted in the loop statement on lines 25 to 28 in FIG.
It is referenced in the loop statement on lines 35-40. On the other hand, the array buffer is substituted by a loop statement on lines 35 to 40, and 1
It is referred to in the loop statement on lines 6 to 18 (step B
3: Yes). Therefore, for each array, step B5
And B6 are executed.

In step B5, the dependent array da
Consider ta_a and data_b. In step B4,
Check whether the dependent loop statement satisfies the expression or the expression. Here, when the number of loops on the substitution side is M and the number of loops on the reference side is N, the equation and the equation are as follows:
It is as follows. When N ≧ M, N = αM (α is a positive integer of 1 or more)... When M> N, M = αN (α is a positive integer of 2 or more)... 3 times with 64 loops
The loop statement in the 5th to 40th lines satisfies the expression (step B4: Yes) because the number of loops is 32. As a result, the block B_02 relating to the loop statement on the 25th to 28th lines with the large number of loops is divided into two. FIG. 7 shows the architecture at this time.

Further, re including the loop statement on lines 25 to 28
The ad function is a loop statement in the main function on the 10th to 12th lines.
Called 0 times. Further, the cal function including the loop statement on the 35th to 40th lines is called 15 times by the loop statement in the main function on the 13th to 15th lines. Since these two loops also satisfy the formula, they are similarly divided into smaller loop number units. FIG. 8 shows a circuit diagram at this time. As a result, the number of loops in the sub function read and cal is equal to the number of loops in which the main function calls read and cal.

Next, loop statements are put together for each group (step B6). By arranging the B_02 and B_03 parts of the architecture of FIG. 8 and excluding redundant circuits and arrays, as shown in FIG. 9, the arrays data_a and data_b
It is only necessary to use one register for sharing.

Further, the array buffer will be described. Array
bufffer is substituted in the loop statement on lines 35 to 40, and 1
It is referenced in the loop statement on lines 6-18. Since these two loop statements also satisfy the expression, the loop statements on the 16th to 18th lines where the number of loops is large are divided. Since the number of divisions is 480/32 = 15, there are 15 divisions.
The cal function including the loop statement on lines 35 to 40 is 1
It is called 15 times in the loop statement of the 3rd to 15th lines. Since the number of loops and the loop statement divided earlier satisfy the expression, they are put together (step B6). FIG. 9 shows a circuit diagram at this time. After performing the above-described processing of steps B3 to B9 on all the arrays, a CDFG is generated (step B10). Thereafter, resource binding and scheduling are performed (step B11).
Finally, RTL H having the architecture shown in FIG.
The description in the / W description language is output (step B12), and the behavioral synthesis ends.

The circuit shown in FIG. 9 can be obtained by the behavioral synthesis method according to the present invention. The loop count of B_01 is 4
The number of loops is 80 (= 32 × 15), which is 1/6 the number of loops as compared with the circuit of FIG. 6 obtained by the conventional behavioral synthesis method, and it can be seen that the circuit can be speeded up. In addition, arrays data_a [30] [64], data_b [30] [64], buffer
[480] can be shared with nine registers, so that the area is also reduced.

Here, the behavioral synthesis method of the present invention described above is summarized below. The behavioral synthesis tool optimizes the synthesis circuit by looking at the description about the array. In the behavioral synthesis flowchart shown in FIG. 1, the number of loops M on the substitution side shown in FIG.
In the case of FIG. 2 where the input description is 60, the syntax analysis of the prepared behavioral input description is performed in step B1. In step B2, it is checked whether or not an array is used in the source. If an array is used, in step B3,
The description about the assignment and reference of the array used is "fo
Check whether it is surrounded by loop statements such as "r statement" and "while statement". If it is enclosed by loop statements, in step B4, the number of loop statements M and N
Check. If the above-described expression or the expression is satisfied, the circuit is optimized by dividing and parallelizing the loop statement so that the algorithm does not change.

When the above-mentioned expression is satisfied, the division of the loop statement is detected in step B5. In the example of FIG.
Since (= 120) is twice N (= 60), which satisfies the expression, the loop statement on the assignment side is divided into two. The array is divided according to the division of the loop statement. In this case, since the loop statement is divided into two, the array tmp [120] is stored in tmp_1
[60] and tmp_2 [60] are divided into two (see FIG. 3). The circuit of FIG. 3 has two B_01 units in parallel as compared with the circuit of FIG. 14, so that the processing speed is correspondingly increased.
Next, in step B6, the loop statements on the assignment side and the reference side are
Group by group. In the example of FIG. 2, B_0 on the substitution side
Since 1 and B_02 on the reference side are in a 2: 1 relationship, B_01 is two-parallel, and B_02 is the same circuit as 1
Can be considered as two groups. Thereby, B_ of FIG.
01 and B_02 become the same 60 loops, and can be grouped as one group. And 1
By grouping them into one group, the arrays tmp_1 and tmp_2 are not required, and the two registers can be shared. As shown in FIG. 4, the resulting circuit does not have an array tmp having as many as 160 positive numbers, and the circuit can be realized with only two registers, and the area can be reduced. In addition, by combining the loops into one, the total number of loops becomes 60, which is 1/3 of the number of loops 180 in the case of the architecture shown in FIG. 14, so that a high-speed circuit can be realized.

The configuration and operation of the preferred embodiment of the behavioral synthesis method according to the present invention have been described above in detail. However, such an embodiment is merely an example of the present invention and does not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications and changes can be made in accordance with the particular application by departing from the spirit of the invention.

[0024]

As will be understood from the above description, the behavioral synthesis method according to the present invention has the following remarkable practical effects. That is, from the source written in the description that can be synthesized, the loops with the description about the array are automatically detected, and the circuit structure is divided into groups based on the number of loops with the assignment and the number of loops with the reference. I do. Further, by parallelizing this, the register is abolished, and the circuit can be reduced in size and the speed can be increased as compared with the prior art.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a preferred embodiment of a behavioral synthesis method according to the present invention.

FIG. 2 shows a specific example of a source written in a behavior synthesizable description.

FIG. 3 is a circuit diagram obtained in step B5 in FIG.

FIG. 4 is a circuit diagram obtained in step B6 in FIG.

FIG. 5 is a specific example of a source written in a behaviorally synthesizable description used in the description of the present invention.

FIG. 6 is a circuit diagram when the sources shown in FIG. 5 are synthesized by a conventional behavioral synthesis;

7 shows arrays data_a and d at step B5 in FIG.
FIG. 14 is a circuit diagram selected as a result of performing a process on ata_b.

FIG. 8 is a diagram showing an example in which arrays data_a and d
FIG. 14 is a circuit diagram obtained as a result of summarizing loop portions for ata_b.

FIG. 9 is a circuit diagram obtained as a result of summarizing loop portions for an array buffer in step B6 in FIG. 1;

FIG. 10 is an example of a source written in a software language.

FIG. 11 is an example of a source written in a behavior synthesizable description.

FIG. 12 is a flowchart of a conventional behavioral synthesis.

FIG. 13 shows the CDFG obtained in step A6 in FIG.
It is.

FIG. 14 is a circuit diagram obtained when the signals are synthesized by the conventional behavioral synthesis method shown in FIG.

Claims (5)

[Claims] 1. A method for automatically detecting a loop statement with a description related to an array from a source written in a behavior-synthesizable description, referring to the number of loops of a loop statement with a description related to the assignment of the detected array, and A behavioral synthesis method characterized in that a circuit structure of a portion related to a loop description is divided into groups based on the number of loops of a loop statement having a description of the same, and a redundant register is abolished and shared by performing parallelization. 2. The behavior synthesizing method according to claim 1, wherein said dividing is performed by dividing a loop statement having a large number of loops in accordance with a loop unit having a small number of loops. 3. The behavioral synthesis method according to claim 2, wherein the array is also divided according to the division. 4. The behavioral synthesis method according to claim 1, wherein the loop statements after the division are grouped into groups according to loop statement dependencies to eliminate redundant arrays. 5. The method according to claim 1, wherein if the description relating to the assignment and reference of the array is not included in the loop statement, the array is realized or selected by a memory or a register. Behavioral synthesis method.