JP2014225201A - Semiconductor device design apparatus, semiconductor device design method, and semiconductor device design program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device design apparatus, a semiconductor device design method, and a semiconductor device design program capable of preventing a redundant register from being added during a behavioral description, preventing an increase in a code quantity of the behavioral description, preventing an increase in an area of generated hardware, and achieving high speed operation.SOLUTION: An analysis unit analyzes a possible range of a subscript of a first array access from a behavioral description. A first processing unit changes a range of a first loop to a range of a second loop so as to include the possible range of the subscript of the first array access. A second processing unit adds a second array access including entirety of the range of the subscript of the first array access within the range of the second loop. A third processing unit calculates a reuse distance between the first and second array accesses by searching a data reuse relation between the first and second array accesses, adds description of a shift register to the second loop, and replaces the first array access by a register having the same number as the reuse distance.

Description

  The present invention relates to a semiconductor device design apparatus, a design method, and a design program for optimizing a behavior level description (hereinafter simply referred to as a behavior description) in which an operation of a digital circuit is described.

  The high-level synthesis technology (Non-patent Document 1) can automatically generate an RTL (Register Transfer Level) description from an operation description (hereinafter also referred to as C description) configured by a program such as C language. ) Design efficiency can be greatly improved. However, in order to generate a high-performance RTL description, it is usually necessary to optimize memory access on the C description. Currently, optimization of memory access by a high-level synthesis tool requires the user of the high-level synthesis tool to manually optimize the C description, which increases design time.

  One technique for optimizing memory access is a technique called scalar replacement (Non-Patent Documents 2, 3, and 4). The array and temporary variable in the C description are a memory and a register on the hardware. The scalar place is a technique that replaces access to a plurality of arrays in a C description with access to temporary variables, that is, access to a memory with access to a register. For example, by preparing a shift register, an array can be accessed. Access can be reduced. By applying this to the C description before high-level synthesis, it is possible to reduce the memory access of the automatically generated hardware and to expect an improvement in performance.

  However, in the existing scalar replacement, it may be necessary to set an initial value in a shift register prepared in advance. At this time, there is a problem that the code amount increases, the area of hardware increases, and the operation speed decreases.

JP 2012-118835 A

Daniel D. Gajski, “High Level Synthesis: An Introduction to Chip and System Design,” Kluwer Academic Publishers, 1992. Steve Carr, Ken Kennedy, “Scalar Replacement in the Presence of Conditional Control Flow,” Software-Practice and Experience, Vol. 24, Issue 1, pp. 51-77, 1994. Byoungro So, “An Efficient, Design Space Exploration For Balance Between Computation And Memory”, Ph.D. University of Southern California, 2003. Nastaran Baradaran, Pedro C. Diniz, and Joonseok Park, “Extending the Applicability of Scalar Replacement to Multiple Induction Variables,” pp. 455-469, Languages and Compilers for High Performance Computing, 2004

  The present invention provides a design apparatus, a design method, and a design program for a semiconductor device that can prevent a hardware area from increasing and enable high-speed operation when a shift register is initialized.

  According to an aspect of the semiconductor device designing apparatus of the present invention, a storage unit storing operation descriptions in which a plurality of first array accesses and operations of a digital circuit including a first loop are described is stored in the storage unit. The analysis unit for analyzing the range that can be taken by the subscript of the first array access, and the range that can be taken by the subscript of the first array access analyzed by the analysis unit are included from the above described behavior description A first processing unit that changes a range of the first loop to a range of a second loop so that there is a second array access to be performed, and in the range of the second loop, the first loop A second processing unit that adds the second array access including the entire range of array access subscripts, and a data reuse relationship between the first and second array accesses. Calculate the reuse distance A description of a shift register having the same size as the maximum reuse distance is added to the second loop, and a third array access is replaced with an access to a register having the same number as the reuse distance. And a processing unit.

The figure which shows an example of operation | movement description. The figure which shows the progress in the case of performing the scalar replacement, initialization, and loop peeling by the existing method with respect to the behavioral description shown in FIG. The figure which shows the result at the time of performing the scalar replacement, initialization, and loop peeling by the existing method with respect to the behavioral description shown in FIG. The block diagram which shows an example of the behavioral synthesis apparatus with which this embodiment is applied. The block diagram which shows the function of the control part and memory | storage device which are shown in FIG. The flowchart which shows operation | movement of this embodiment. The figure which shows an example of the action description applied to this embodiment. The figure which shows the range which the subscript of each array access in the action description shown in FIG. 7 can take. The figure which shows the process result of the 1st process part which concerns on this embodiment. The figure which shows the process result of the 2nd process part which concerns on this embodiment. FIGS. 11A and 11B are diagrams showing a reuse relationship between array accesses according to the present embodiment. The figure which shows the relationship of reuse shown in FIG.11 (b) collectively. The figure which shows the process result of the 3rd process part which concerns on this embodiment, and shows an example of the optimized operation | movement description. The figure which shows the operation description at the time of adding the deletion of the existing array access and the array access for initialization with respect to the operation description shown in FIG. The figure which shows the action description at the time of carrying out the existing loop peeling of the loop (loop i) of the outer side of the action description shown in FIG. The figure which shows the operation | movement description at the time of carrying out the existing loop peeling of the inner loop (loop j) of the operation | movement description shown in FIG.

  As described above, in the scalar replace, it may be necessary to set an initial value in a prepared shift register. For example, when the existing scalar replacement technique and the existing initialization technique are applied to the behavioral description shown in FIG. 1, the final result is as shown in FIG. FIG. 2 shows an intermediate code from FIG. 1 to FIG. 2 and 3, “shift_registers (B_reg_5,..., B_reg_0)” simply shows a description of the shift register that is required when the array access in FIG. 1 is replaced with an access to the shift register. Yes. In FIG. 2, the third and fifth lines are executable statements for initializing the shift register.

  The array access B [i] [j] in the third row in FIG. 1 is a reuse generator (reuse source). That is, it is a supply source for supplying data to be reused for array access B [i-1] [j-1]. Therefore, in order to copy the data accessed by B [i] [j] to the shift register, the executable statement in the third line in FIG. 2 is required. However, this initialization only assigns a value to the register B_reg_0, and no value exists in the register B_reg_5 in the sixth row in FIG. Therefore, until the value is filled in the shift register, it is necessary to set an appropriate value for the register B_reg_5 as shown in the fifth row of FIG.

  In the existing method, after applying the scalar replacement and initialization shown in FIG. 2, by applying loop peeling, and dividing the loop, the array access generated by the initialization is removed from the main loop. The Here, the loop peeling is to execute some of the first or last iteration of the loop separately from the main loop. As a result, the array access in the main loop is repeatedly executed as shown in FIG. This is a technique that moves an executable statement such as a line to the outside of a loop, shortens the start interval of main loop execution, and improves performance.

  FIG. 3 shows the result of applying loop peeling to the behavioral description shown in FIG. By applying the loop peeling, the innermost loop shown in the 12th to 16th rows in FIG. 3 can access the array B once per loop. However, since the amount of code increases due to loop peeling, it becomes a factor of increasing the area when hardware is realized using high-level synthesis.

  Thus, in the present embodiment, the initialization of a shift register that does not require loop peeling will be described.

(Embodiment)
Hereinafter, embodiments will be specifically described with reference to the drawings.

  In the present embodiment, optimization of integrated circuit design by optimizing behavioral descriptions will be described. The optimization of the behavioral description is a subordinate concept of the high-level synthesis, and the optimization of the behavioral description is used when generating the RTL description from the behavioral description configured by a programming language such as C language, as in the high-level synthesis. For example, it is widely applied to the design of image processing and audio signal processing circuits. However, this embodiment is not limited to optimizing behavioral descriptions, and can also be applied to high-level synthesis.

(Device configuration)
FIG. 4 shows an example of an operation description optimizing device to which the present embodiment is applied. The behavioral description optimizing device 10 is constituted by, for example, a computer, and this computer is constituted by, for example, an input device 12, an output device 13, a storage device 14, and a memory 15 connected to the control unit 11.

  The control unit 11 is a CPU (Central Processing Unit), for example, and executes a predetermined operation according to a program stored in the memory 15.

  The input device 12 is, for example, a keyboard for inputting information necessary for optimizing the operation description indicating the operation of the semiconductor integrated circuit and the operation description such as restrictions on the semiconductor integrated circuit.

  The output device 13 outputs the generated operation description and the like, and is configured by a printer, for example.

  The storage device 14 is a computer-readable storage medium such as a hard disk device or a flash memory. The storage device 14 stores, for example, a program necessary for the operation of the control unit 11, a program necessary for optimizing the operation description, or an operation description in C language, for example.

  The memory 15 is, for example, a RAM (Random Access Memory), and is loaded with a program and the like necessary for the operation of the control unit 11 read from the storage device 14.

  FIG. 5 shows functions realized by the control unit 11 and the storage device 14 shown in FIG.

  The control unit 11 includes an analysis processing unit 11a, a first processing unit 11b, a second processing unit 11c, and a third processing unit 11d.

  The storage device 14 need not be directly connected to the control unit 11 and may be connected via a network.

  Further, the storage device 14 stores an operation description 14a, array access range information 14b generated in the course of the operation of the control unit 11, and an optimized operation description 14c.

(Operation)
FIG. 6 shows the operation of the control unit 11, and each function shown in FIG. 5 will be described with reference to FIG.

  First, the analysis processing unit 11a of the control unit 11 reads the behavior description 14a from the storage device 14, and analyzes the range taken by the array access subscript in the behavior description 14a (S11).

  FIG. 7 shows an example of the behavior description stored in the storage device 14. An array access is an actual reference to an array appearing in the “for” loop. When the behavioral description is as shown in FIG. 7, one array access A [i] [j] is related to the array A. And for array B, three array accesses B [i] [j + 1], B [i] [j], B [i-1] [j] are included.

  The array access subscript means, for example, “x” and “y” for the array access B [x] [y], for example, B [i−1] [j] shown in FIG. In this case, it means “i−1” and “j”. The range taken by the subscript means a range where the subscript changes in the set loop. Therefore, to analyze the range taken by the array access subscript, the variable that controls the execution of the loop, that is, the loop variable “i” “j” is the range specified in the loop (in FIG. 7, 1 <= i < = 32, 1 <= j <= 16), the range in which the array access index moves is checked. For example, for the above three array accesses B [i] [j + 1], B [i] [j], and B [i-1] [j], the range in which the subscript moves is as follows.

B [i] [j + 1]: 1 <= i <= 32, 2 <= j + 1 <= 17
B [i] [j]: 1 <= i <= 32, 1 <= j <= 16
B [i-1] [j]: 0 <= i-1 <= 31, 1 <= j <= 16
The broken lines shown in FIG. 8 indicate the subscript ranges of the array accesses B [i] [j + 1], B [i] [j], and B [i-1] [j].

  Next, the analysis processing unit 11a analyzes the range of the array subscript based on the analyzed range of the array access subscript (S12).

  The range taken by the array subscript is to obtain the union of the ranges taken by the subscripts of each array access for each array. For example, in the behavioral description shown in FIG. 7, the range of the subscript [X] [Y] of the array B is as follows.

{1 <= X <= 32 ∪ 1 <= X <= 32 ０ 0 <= X <= 31}
= {0 <= X <= 32},
{2 <= Y <= 17 １ 1 <= Y <= 16 ∪ 1 <= Y <= 16}
= {1 <= Y <= 17}
A solid line frame shown in FIG. 8 indicates a range that the subscript [X] [Y] of the two-dimensional array B can take.

  The range taken by the array access subscript analyzed as described above and the information on the range taken by the array subscript are stored in the storage device 14 as array access range information 14b.

  Next, based on the analysis result, the first processing unit 11b changes the loop range (S13).

  That is, the initial value and final value of the loop variable are changed based on the range taken by the subscript of the array. For example, in the behavioral description shown in FIG. 7, the array access that is the source of reuse data for each array access, that is, the subscript of the array access B [i] [j + 1] as a generator is “i, j + 1”. Yes, the range taken by these subscripts only needs to include the range taken by the subscripts of the array. Therefore, these subscripts may be 0 <= i <= 32 and 1 <= j + 1 <= 17, respectively. That is, the range of the loop variable after the change is 0 <= i <= 32 and 0 <= j <= 16, and the array access B [i that becomes the reuse generator under the range of the loop variable after the change. ] The range taken by the subscript of array access B [i] [j + 1] having the same subscript as [j + 1] is a range including the range that can be taken by the subscript of each array access. Therefore, in order to maintain the same operation as the original operation description shown in FIG. 7, the loop range is changed as follows.

for (i = 0; i <33; i ++) {
for (j = 0; j <17; j ++) {
if ((i> = 1) &&(j> = 1)) {
The method of determining the loop range to be changed is as follows in other words.

  In the behavioral description that requires initialization shown in FIG. 7, the range taken by the array subscript must be included in the range taken by the subscript for array access serving as a generator.

  For example, in the behavioral description shown in FIG. 7, the range taken by the array access B [i] [j + 1] as a generator is 1 <= i <= 32 and 2 <= j + 1 <= 17 as described above. The range of the subscript of the array B is B [X] [Y] {0 <= X <= 32} and {1 <= Y <= 17}. For the array access having the same subscript as the array access B [i] [j + 1] serving as the reuse generator, the loop variable necessary to match the range taken by the subscript with the range taken by the subscript of the array A range is required. In the behavioral description shown in FIG. 7, the reuse generator subscripts are “i, j + 1”, and these subscripts can be 0 <= i <= 32 and 1 <= j + 1 <= 17, respectively. Therefore, the range of the loop variable is 0 <= i <= 32 and 0 <= j <= 16.

  FIG. 9 shows the behavioral description after changing the loop range. In the first line of FIG. 9, “i = 1” is changed to “i = 0”, in the second line, “j = 1” is changed to “j = 0”, and the conditional statement is changed to the third line. Has been inserted.

  Thereafter, array access is added by the second processing unit 11c (S14). Specifically, as shown in the third row of FIG. 10, array access “Breg0 = B [i] [j + 1]” including the entire range of array subscripts is added to the head of the innermost loop.

  Next, array access is deleted by the third processing unit 11d.

  More specifically, the reuse dependency between a plurality of array accesses is analyzed (S15).

  For array access B [i] [j + 1], B [i] [j], B [i-1] [j], the data for array access B [i] [j + 1] is B [i] [j + 1], B Since it is reused for [i] [j] and B [i-1] [j], they are in a dependency relationship.

  For this behavioral description, the reuse relationship between array accesses is analyzed and the reuse distance is calculated.

  FIG. 11 shows a reuse graph corresponding to the behavioral description shown in FIG. A reuse graph creates a node of a generator as a supply source (reuse source) of reuse data or a node of a supply destination (hereinafter also referred to as a reuse destination) for each array access. Are connected to the supply destination node by an arrow called an edge. This edge is accompanied by a reuse vector.

  In the reuse graph shown in FIGS. 11A and 11B, the four circles indicate array access B [i] [j + 1], B [i] [j + 1], B [i] [j], B [i -1] represents [j], and the reuse relationship is represented by an edge. The root of the edge is a generator as a reuse source, and the tip of the edge is the reuse destination.

  11 (a) and 11 (b), array access B [i] [j + 1] surrounded by double circles is connected only to the edges facing outward from the array access B [i] [j + 1]. Edges facing B [i] [j + 1] are not connected. For this reason, array access B [i] [j + 1] surrounded by a double circle is a generator.

  As shown in FIG. 11A, reuse vectors <dy, dx> are added to the edges. The reuse vector <dy, dx> is configured by a difference between array access subscripts connected by edges. For example, the reuse vector of array access B [i] [j + 1] and B [i] [j + 1] is obtained as <0, 0>, and array access B [i] [j + 1] and B [i] [ j] is obtained as <0,1>, and the reuse vector between array accesses B [i] [j + 1] and B [i-1] [j] is <1,1>. Desired.

  Next, based on the dependency relationship between the array accesses, the reuse distance d is calculated by the third processing unit 11d (S16).

  The reuse vector <dy, dx> shown in FIG. 11 (a) represents how many times each array access is reused after a loop has been made to the generator. For example, in the case of a reuse vector <dy, dx> (in the case of a double loop), it indicates that reuse occurs from the reuse source to the reuse destination after the outer loop is rotated dy times and the inner loop is rotated dx times. .

  The reuse distance d shown in FIG. 11B represents how many times each array access is looped with respect to the generator and then reused in terms of the innermost loop count. The reuse distance d is calculated based on the reuse vector shown in FIG. That is, the reuse distance d is represented by “d = dy × j + dx”, where the reuse vector <dy, dx> and the number of loops are j. In the case of the reuse vector <0, 0> shown in FIG. 11A, the number of inner loops is 17 times from FIG. Based on this, the reuse distance d1 is calculated to be d1 = 0 × 17 + 0 = 0. In the case of the reuse vector <0, 1>, the reuse distance d3 is d3 = 0 × 17 + 1 = 1. Further, in the case of the reuse vector <1, 1>, the reuse distance d4 is d4 = 1 × 17 + 1 = 18.

  FIG. 12 is a table summarizing information necessary for deletion of array access, and is represented by access type, array access, and reuse distance. In this table, the arrows of the reuse graph of the array of interest (array B) are arranged from the top in ascending order of reuse distance.

  Thereafter, the description of the shift register is added to the last part of the innermost loop by the third processing unit 11d, and the array access is replaced with the temporary variable access (S17).

  The size of the shift register, that is, the number of registers constituting the shift register is set to the maximum value of the reuse distance. In this example, since the maximum value of the reuse distance is d4 = 18, the shift register is composed of 18 registers.

  Furthermore, the array access is replaced with a temporary variable access so that the array access at the reuse destination refers to the shift register having the corresponding reuse distance number, and the behavioral description is optimized.

  FIG. 13 shows an example of an optimized behavior description with array access deleted. In the fifth line shown in FIG. 13, the array access at the reuse destination is replaced with a temporary variable access (register access) having a reuse distance number, and the description of the shift register is added to the seventh to 24th lines. Yes. This description of the shift register indicates that the data of Bregi is shifted to Bregi + 1 every time the loop goes around.

  As shown in FIG. 5, the optimized behavior description 14 c is stored in the storage device 14.

(Effect of embodiment)
According to the above embodiment, the range that each array access subscript included in the behavior description can take and the range that includes the range that these array access subscripts take are analyzed, and the loop range is determined based on the analysis result. Change the loop range by expanding, add array access based on this changed loop range, analyze the reuse relationship of multiple array accesses including this added sequence access, and from the analyzed reuse relationship Calculate the reuse distance, add a shift register of a size corresponding to the calculated maximum reuse distance to the operation description, and replace the array access with access to the register having the reuse distance number. The shift register is referred to by this register. For this reason, compared with the case where the existing loop peeling is used, the code amount of the operation description can be reduced, and the addition of a redundant shift register can be prevented. Therefore, it is possible to prevent an increase in the area of the generated hardware.

  Specifically, in the case of the initialization method using the existing loop reeling, since the loop is divided, a plurality of loops are created. In the present embodiment, scalar replacement by one loop is possible. Therefore, the code can be shortened.

  14 to 16 show behavioral descriptions when the existing scalar replacement and loop peeling are applied to the behavioral description shown in FIG.

  FIG. 14 shows the code after adding array access deletion and initialization array access to the behavioral description shown in FIG.

  FIG. 15 shows a code obtained by loop peeling the outer loop (loop i) once from the behavioral description shown in FIG.

  FIG. 16 shows code obtained by loop peeling the inner loop (loop j) shown in the 27th line of FIG. 15 once for the behavioral description shown in FIG. As shown in the 50th to 68th lines, all array accesses for initialization are deleted from the description of the main loop surrounded by the broken line by the loop peeling.

  As shown in FIG. 16, the amount of code when executing the existing scalar replacement and loop peeling for the original behavioral description shown in FIG. 7, and the scalar replacement without using the loop peeling according to the present embodiment shown in FIG. Comparing the amount of code after application, the existing method requires 70 lines of code as shown in FIG. On the other hand, in the case of this embodiment, it is composed of 25 lines of code. For this reason, in the case of this embodiment, compared with the case where the existing scalar replace and loop peeling are used, the code amount can be reduced by 63%. Therefore, the area of the generated hardware can be significantly reduced as compared with the existing method.

  In addition, since the area of hardware can be reduced and an increase in redundant registers can be prevented, high-speed operation is possible.

  Note that the reuse graphs shown in FIGS. 11A and 11B and the reuse occurrence graph shown in FIG. 12 are arbitrary, and array access may be replaced with a shift register based on the calculated reuse distance. Is possible.

  In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 10 ... Operation description optimization apparatus, 11 ... Control part, 14 ... Memory | storage device, 11a ... Analysis process part, 11b ... 1st process part, 11c ... 2nd process part, 11d ... 3rd process part, 14a ... Behavior description, 14b ... Array access range information, 14c ... Optimized behavior description.

Claims (6)

A storage unit storing a plurality of first array accesses and an operation description in which operations of the digital circuit including the first loop are described;
An analysis unit that analyzes each possible range of the subscript of the first array access from the behavior description stored in the storage unit;
The range of the first loop is the range of the second loop so that there is a second sequence access that includes the range that can be taken by the subscript of the first sequence access analyzed by the analysis unit. A first processing unit to be changed to
A second processing unit for adding the second array access including all subscript ranges of the first array access in the range of the second loop;
The data reuse relationship between the first and second array accesses is examined, the reuse distance between each array access is calculated, and the description of the shift register having the same size as the maximum value of the reuse distance is described in the second And a third processing unit for adding to the loop and replacing the first array access with an access to a register having the same number as the reuse distance.   2. The semiconductor device design apparatus according to claim 1, wherein the first processing unit calculates a union of ranges that can be taken by a plurality of subscripts of the array access analyzed by the analysis unit.   2. The semiconductor device according to claim 1, wherein the second processing unit adds an array access including the entire subscript range of the array to the head of the innermost loop of the second loop. Design equipment.   The semiconductor device design apparatus according to claim 1, wherein the third processing unit adds the shift register to the last part of the innermost loop of the second loop. A storage unit storing a plurality of first array accesses and an operation description in which operations of the digital circuit including the first loop are described;
Analyzing each possible range of subscripts of the first array access from the operation description stored in the storage unit and describing the operation of the digital circuit including the plurality of first array accesses and the first loop. ,
The range of the first loop is changed to the range of the second loop so that there is a second sequence access that includes the possible range of the subscript of the analyzed first sequence access. ,
Adding the second array access including all subscript ranges of the first array access in the range of the second loop;
The data reuse relationship between the first and second array accesses is examined, the reuse distance between each array access is calculated, and the description of the shift register having the same size as the maximum value of the reuse distance is described in the second A method for designing a semiconductor device, wherein the method is added to a loop, and the first array access is replaced with an access to a register having the same number as the reuse distance. A storage unit storing a plurality of first array accesses and an operation description in which operations of the digital circuit including the first loop are described;
Analyzing each possible range of subscripts of the first array access from the operation description stored in the storage unit and describing the operation of the digital circuit including the plurality of first array accesses and the first loop. ,
The range of the first loop is changed to the range of the second loop so that there is a second sequence access that includes the possible range of the subscript of the analyzed first sequence access. ,
Adding the second array access including all subscript ranges of the first array access in the range of the second loop;
The data reuse relationship between the first and second array accesses is examined, the reuse distance between each array access is calculated, and the description of the shift register having the same size as the maximum value of the reuse distance is described in the second A semiconductor device design program for causing a computer to execute a process of adding to a loop and replacing the first array access with an access to a register having the same number as the reuse distance.

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