JP2020135743A - Circuit design support device, circuit design support method, and information processing device - Google Patents

Abstract

To consider performance when a logic circuit is repeatedly accessed on software in making a portion of software description a logic circuit.SOLUTION: A circuit design support device includes: a measurement part having a function for detecting processing which enables parallel operation configuration in a logic circuit and is executed a plurality of times in making a portion of software description the logic circuit, listing inputs when the logic circuit performs the processing, and outputting performance in reducing an input amount to the logic circuit as a logic circuit formation candidate list; and a description insertion part having a function for inserting description for reducing the input amount to the logic circuit into the software description for a logic circuit formation candidate selected from the logic circuit formation candidate list.SELECTED DRAWING: Figure 3

Description

The present invention relates to a circuit design assisting technique that supports logic circuit design. A specific example relates to a circuit design support device and a method for supporting a logic circuit design using high-level synthesis that automatically generates a logic circuit description from a software description.

As one of the methods for accelerating the software processing running on the CPU (Central Processing Unit), there is a method of implementing the processing that is the load of the software processing on a logic circuit device and offloading it. For logic circuit devices such as FPGA (field-programmable gate array), the internal logic circuit can be freely designed by the logic circuit description. Unlike a CPU that performs sequential processing, a logic circuit can execute multiple processes at the same time, so when speeding up software processing, by constructing operations in parallel on the logic circuit, it demonstrates faster performance than the CPU. It is possible to do.

Conventionally, logic circuit design has been required at the register transfer level, but in recent years, high-level synthesis designed by a higher-level language such as C language, which has a higher degree of abstraction, has become possible. By utilizing high-level synthesis, it is also possible to directly convert the load processing code of software running on the CPU into a logic circuit using high-level synthesis, and speed up the logic circuit device.

However, since the software description is generally described so that it is processed sequentially on the CPU, if it is implemented in a logic circuit by high-level synthesis as it is, parallelization will not be successful, and logic such as accessing an external memory will be performed. It is difficult to obtain the expected speed-up effect due to redundant processing for the circuit.

In Japanese Patent Application Laid-Open No. 2015-95130 (Patent Document 1), "In the parallelization candidate code block, the evaluation target range, which is the range of the code block to be evaluated, is changed in the narrowness around the critical code block. Multiple settings are made, the characteristics of the data path corresponding to the code block of the evaluation target range are evaluated for each evaluation target range, and the evaluation target range to be the target of circuit parallelization is selected from the multiple evaluation target ranges. As stated in "It is characterized by having a part", it is necessary not only to simply apply high-level composition to the part where the speed-up effect by parallel computing is expected to be high, but also to identify the part that is most suitable for the logic circuit. There is.

JP-A-2015-95130

Patent Document 1 refers to a plurality of logic circuit cases when a portion of software processing in which speeding up by a parallel circuit can be achieved is set as a logic circuit target and a plurality of peripheral processes are included. This is a performance evaluation technology.

However, Patent Document 1 does not evaluate the performance when the logic circuit is repeatedly called on the software. That is, when making a part of the software description into a logic circuit, it is desirable to consider the performance when the logic circuit is repeatedly called on the software.

A preferable aspect of the present invention is that when a part of the software description is made into a logic circuit, a process that is executed a plurality of times that allows a parallel arithmetic configuration in the logic circuit is detected, and an input when the process is performed in the logic circuit For the measurement unit that has the function of listing the performance when the input amount to the logic circuit is reduced and outputting it as a logic circuit candidate list, and for the logic circuit candidates selected from the logic circuit candidate list, software It is a circuit design support device including a description insertion unit having a function of inserting a description for reducing the amount of input to a logic circuit into the description.

Another preferable aspect of the present invention is a circuit design support method for converting a part of the software description into a logic circuit, that is, an iterative process extraction process for extracting the iterative process for making a logic circuit from the software description, and the extracted iteration. Software to extract an input array that repeatedly uses the same value in the process, and to convert an input array that repeatedly uses the same value into an array that has the same number of elements as other input sequences. This is a circuit design support method that performs a description insertion process that changes the description.

Another preferred aspect of the present invention includes a CPU, a logic circuit, and a memory, and when the software stored in the memory is executed by the CPU to perform processing, the logic circuit is called to execute a part of the processing. , An information processing device. In this device, when the CPU calls a logic circuit to execute a part of the processing, the input of the processing executed by the logic circuit includes a plurality of arrays, and the plurality of arrays repeatedly input the same value. If, an array that repeatedly uses the same value is converted to an array that has the same number of elements as other arrays and transferred to the logical circuit, and the logical circuit transfers the array that repeatedly uses the same value to the built-in memory. It is stored and processing is performed using the array stored in the built-in memory.

When a part of the software description is made into a logic circuit, a system considering the performance when the logic circuit is repeatedly called on the software can be obtained.

The conceptual diagram which shows an example of the logic circuit of software processing. A conceptual diagram showing another example of logic circuitization of software processing. The block diagram which shows the design support apparatus of the operation description to which embodiment is applied. The block diagram which shows the structure of the high-level synthesis which concerns on Example. The flowchart which shows the operation in the measurement part in an embodiment. The conceptual diagram which shows the example of the logic circuit of software processing by an Example. The flowchart which shows the operation in the description insertion part in an embodiment. The table diagram of the logic circuit candidate list in an embodiment. The block diagram which shows the hardware architecture to which an embodiment is applied. The figure of the code description example in the logic circuit of software processing. The figure of the code description example in the logic circuit of software processing by an Example.

The embodiment will be described in detail with reference to the drawings. However, the present invention is not construed as being limited to the description of the embodiments shown below. It is easily understood by those skilled in the art that a specific configuration thereof can be changed without departing from the idea or purpose of the present invention.

In the configuration of the invention described below, the same reference numerals may be used in common among different drawings for the same parts or parts having similar functions, and duplicate description may be omitted.

When there are a plurality of elements having the same or similar functions, they may be described by adding different subscripts to the same code. However, if it is not necessary to distinguish between a plurality of elements, the subscript may be omitted for explanation.

Notations such as "first", "second", and "third" in the present specification and the like are attached to identify the components, and do not necessarily limit the number, order, or contents thereof. is not. In addition, numbers for identifying components are used for each context, and numbers used in one context do not always indicate the same composition in other contexts. Further, it does not prevent the component identified by a certain number from having the function of the component identified by another number.

The position, size, shape, range, etc. of each configuration shown in the drawings and the like may not represent the actual position, size, shape, range, etc. in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings and the like.

In this embodiment, a design support device for operation description will be described. The design support device of the operation description extracts the iterative process that can be configured by the parallel circuit from the software processes, and when the extracted process is called multiple times on the software, the logic is taken into consideration for multiple calls. The amount of input to the circuit can be reduced and the processing time can be shortened.

Generally, when a part of software processing is made into a logic circuit by high-level synthesis, high-level synthesis is performed so as to be optimized as a logic circuit for one process. Hereinafter, a specific conversion process when performing high-level synthesis will be described.

For example, in high-level synthesis in which a part of the software description is made into a logic circuit to speed up, when the logic circuit is called multiple times, multiple arrays are transferred, and there is an array whose value does not change, all the input arrays are used as arguments. , It is necessary to repeatedly input an array with the same value. Therefore, by aligning the array with the same value with the number of elements of the array with a large number of elements, the input interface is made common, and the array with the same value is performed with one input. Further, by using one array with the largest number of elements as an input to the logic circuit and aligning the number of elements in all the input arrays, the input interface can be made common. By storing the array in which the same value is input in the memory in the logic circuit, it is possible to reuse it in the logic circuit without repeating the transfer, and it is possible to reduce the transfer time and increase the speed.

FIG. 1 shows an example of a configuration when a part of software processing is made into a logic circuit by high-level synthesis. When a certain process is made into a logic circuit by high-level synthesis, the process is made into a function on software, and the arguments in the function are treated as input / output to the logic circuit. In FIG. 1, among the processes A, B, C, and D described in the software description (100), the process D (101D) called repeatedly 50 times is made into a logic circuit, and the array is input to the logic circuit D (200D). A [100] is transferred in order of sequence A1 [100] (301) sequence A2 [100] (302) sequence A3 [100] (303).

The arrays A1, A2, and A3 all mean an array A [100] having 100 elements that store different values, and the values differ by 50 times, which is the repetition of the process D (101D), that is, A1 [100]. ] To A50 [100] are input to the logic circuit D (200D). In the logic circuit D (200D), the 100 elements of the received array A [100] are expanded in parallel to perform parallel calculation (201) 50 times, and other operations (202) are performed as necessary. Outputs the result and returns to software processing. With the above configuration, 100 elements of array A [100] can be operated in parallel by the logic circuit D (200D).

FIG. 2 is a diagram showing an example in which a plurality of arrays are input. Of the processes A, B, C, and D of the software description (100), when the logic circuit is executed for the process B (101B) called 100 times, the logic circuit B (200B) is obtained.

Since the process B (101B) has a plurality of (two in this example) arrays A [100] and B [10] as inputs, the array A [100], also for the logic circuit B (200B), An input set (501) (502) (503) or the like composed of a plurality of arrays of the array B [10] is input.

In the logic circuit B (200B), parallel operation (201) is configured, and arrays A1 [100], A2 [100], A3 in an input set (501) (502) (503) composed of a plurality of arrays, etc. [100] ... Parallel operations are executed in order for A100 [100]. In the logic circuit B (200B), the operation (203) is also processed with the array B [10] as an input at the same time as the parallel operation (201).

Here, in the input, the array A [100] stores and transfers different values each time, but assuming that the array B [10] transfers the same value, the transfer and operation of the array B are originally performed ( In 203), even though one process is sufficient, it is transferred and calculated every time.

When the logic circuit is made by high-level synthesis, the number of elements and the number of arrays in the input at the time of calling the logic circuit once are uniformly determined. That is, in this example, the input to the logic circuit B is always limited to two, an array of elements 100 and an array of elements 10. Therefore, in the example of FIG. 2, it is a condition that the input sets of the array A [100] and the array B [10] are input at the same time, and it is not possible to transfer only the array B [10]. Therefore, the input set (502) and the array B inherent in the input set (503) must be input to the logic circuit B (200B) even though they are the same as the values of the input set (501). The process of repeatedly transferring the same value increases the amount of transfer to the logic circuit and increases the processing time.

An example in which this problem is taken into consideration will be described below. In the following embodiment, when an iterative process that can be configured by a parallel circuit is extracted from the software description to be speeded up and the extracted operation is made into a logic circuit, the same process is performed when the process is called multiple times on the software. Detects whether there is an input array (hereinafter also referred to as an equivalence transfer array) that repeatedly transfers values. If an equivalence transfer array exists, the processing time required for repeated transfer can be reduced by inserting a description so that it is transferred to the memory in the logic circuit in advance before the parallel operation is processed in the target logic circuit. Reduce.

Further, for an array for which one input is originally sufficient, repeated transfer to the logic circuit is omitted by unifying and integrating the number of elements with other arrays. Explaining with the example of FIG. 2, array A and array B are integrated into one type of input set, and array A and array B are included in the input set so that they can be input to a logic circuit. Specifically, by transforming array B into a form containing 100 elements and making it possible to input in the same way as array A by high-level synthesis, processing can be executed by transferring one type of array with 100 elements. To.

FIG. 3 is an example when the present invention is applied to the software description, and shows the flow of processing of the design support device for the operation description. The measurement unit (2), the description insertion unit (4), and the high-level synthesis (7) indicate functional blocks. Functions such as calculation and control executed in the functional block shall be realized by an information processing device including an input device, an output device, a processing device, and a recording device, for example, a server. A functional block is realized by executing a program stored in a storage device by a processing device in cooperation with other hardware. A program executed by a computer or the like, its function, or a means for realizing the function may be referred to as a "function", a "means", a "part", a "unit", a "module", or the like.

The software description (1), the logic circuit candidate list (3), the optimized operation description (5), and the non-operation description software description (6) are data or software processed or processed by a functional block. The optimized operation description (5) is made into a logic circuit by high-level synthesis (7), and is implemented as a logic circuit (8) in, for example, an FPGA. The software description (6) outside the operation description is processed by the CPU by the CPU process (9).

The measurement unit (2) extracts the process that enables parallel calculation from the software description (1), and detects the number of times each parallel operation is called and the equivalence transfer array included in each parallel operation. The reduction time when the description to be transferred to the logic circuit is inserted in advance for the equivalence transfer array is calculated, and the result is output as the logic circuit conversion candidate list (3). The logic circuit candidate list (3) is output and displayed by, for example, a display device (monitor or the like) of a server or a printer, and can be viewed by a user (designer).

The designer selects which processing part is to be made into a logic circuit from the output logic circuit formation candidate list (3). In the description insertion unit (4), a description is inserted so that the equivalence transfer array included in the selected logic circuitized portion is transferred to the logic circuit in advance before the parallel operation. As a result, the software description (1) is the optimized operation description (5) after the optimization description is inserted in the description insertion section (4) based on the location selected in the logic circuit candidate list (3). ) And software description (6) outside the operation description.

The optimized operation description (5) is directly converted into a logic circuit by high-level synthesis (7), and is implemented as a logic circuit (8) on the logic device. The software description (6) outside the operation description is processed on the CPU side.

FIG. 4 is a diagram showing details of the measurement unit (2), the logic circuit candidate list (3), and the description insertion unit (4). In the design device of this operation description, the parts that can be speeded up are extracted and the interface is made common. The measurement unit (2) is composed of a repetitive processing extraction unit (10), an equivalence transfer sequence extraction unit (11), and a reduction amount calculation unit (12).

The iterative process extraction unit (10) extracts the iterative process in which the same process is executed a plurality of times from the software description. Specifically, iterative processing that can achieve high speed by parallel calculation is extracted from the software description, and the number of times each iterative processing is called on the software is measured.

The equivalence transfer array extraction unit (11) extracts an array in which the same value is repeatedly input from the input / output array representing the argument referred to in the iterative process. Specifically, for each iterative process extracted by the iterative process extraction unit (10), an array that becomes input / output when the logic circuit is formed is detected, and the same value is repeatedly obtained when the logic circuit is formed. Extract the array to be input.

The reduction amount calculation unit (12) outputs the reduction amount when deleted and the speed-up performance for the equivalence transfer array satisfying the conditions. Specifically, the transfer amount of the equivalence transfer sequence that can be reduced by executing the processes shown in steps 18 to 27 described later in FIG. 5 for each equivalence transfer sequence extracted by the equivalence transfer sequence extraction unit (11). Then, the speed-up performance after deletion is calculated, and it is output as a logic circuit candidate list (3) together with each iterative processing list and the equivalence transfer array.

The logic circuit candidate list (3) displays the number of repetitions, the amount of input or output data when the equivalence transfer array is reduced, the amount of data reduced, and the number of reduced latencies for each repetition process. The designer selects the iterative process to actually make a logic circuit from the logic circuit candidate list (3).

The software description (1) is based on the logic circuitization candidate selected in the logic circuitization candidate list (3), and the description insertion unit (4) inserts the description so that the input of the equivalence transfer array is reduced. According to the description, when the selected process is made into a logic circuit, the speed can be increased by the method of sharing the interface. As a result, the designer can obtain an optimized operation description (5) in which the equivalence transfer sequence is reduced and a software description (6) outside the operation description.

FIG. 5 is a flowchart showing the processing of the measurement unit (2) of the circuit design support device shown in FIG. The operation based on FIG. 5 is as follows. The iterative processing extraction unit (10) executes steps 13 to 16.

Step 13: Read the software description (1) and extract the iterative process included in the description. Since the same process is applied to different elements in the iterative process, the effect of speeding up due to the parallel circuit configuration is high.

Step 14: List the iterative processes read in step 13.

Step 15: Each iterative process listed in step 14 is made into a function including internal processes. At this time, all variables and arrays used in the function are used as arguments. By making arguments, all external data to be referenced and assigned in internal processing can be clarified as arguments. The variables and arrays that are the arguments here are the input / output values of the logic circuit when making the logic circuit.

Step 16: List the arguments of the function separated in step 15 by input and output.

In the processes from step 17 to step 26, the equivalence transfer sequence is detected and the transfer amount that can be reduced is calculated. The processes from step 17 to step 21 are executed by the equivalence transfer sequence extraction unit (11). The processing from step 22 to step 26 is executed by the reduction amount calculation unit (12).

The specific processing performed in each step and its principle will be described with reference to FIG. In this embodiment, taking the form of FIG. 6 can reduce the transfer of the input sets (502), (503) in FIG. 2 and the subsequent array B [10] inside the input set.

FIG. 6 is an example in which the technique of this embodiment is applied when the process B (101B) in which the same process is repeated 100 times is made into a logic circuit as in FIG. Similar to FIG. 2, since the process B (101B) has a plurality of arrays A [100] and B [10] as inputs, normally, the array A [100] is also applied to the logic circuit B (200). , Multiple arrays of array B [10] are input.

In this embodiment, the input array to the logic circuit B (200) is only one array of the type of the array A [100], which is the target of the parallel operation (201), and only 100 elements, and the array B [10]. The number of array elements of is set to 100, which is the same as that of array A [100] (600). For this purpose, for example, 90 dummy data may be added to 10 original array elements. By transforming into this form, the input in one call of the logic circuit B (200) becomes only one array having 100 elements, and each of the array A [100] and the array B [10] is transferred individually. be able to.

At this time, since it is not possible to determine which array the input array is on the logic circuit B (200), the input determination process (204) for determining which array is based on the signal from the variable is arranged before the calculation. The input array may be determined based on the array type and the array value.

The input determination process (204) goes to the memory (205) on the logic circuit B (200) when the input array is the array B [10] (transformed into B [100] on the interface). If it is stored and the array A [100], the process is passed to the parallel operation (201). With this configuration, before the original parallel operation, the array B [10] is input once, stored in the memory (205), and then the parallel operation (201) is executed when the array A [100] is input, and the array B is executed. The operation (203) that requires [10] can acquire the array B [10] from the memory (205) in the logical circuit having less latency than the input from the CPU. As a result, it is possible to design a logic circuit B (200) equivalent to FIG. 2 while reducing the input of the array B [10] to only the first time.

The reduction amount of the array B [10] at this time is that 99 transfers are eliminated, and the array element 90 required to match A [100] in one transfer from the array element of 10 * 99 = 990. Subtracted, the transfer is for 900 elements. By the processing shown above, the input amount of the equivalence transfer array can be reduced, and the processing speed can be increased.

In the flowchart of FIG. 5, the conditions to which this embodiment can be applied are shown and determined as follows.
a) A plurality of arrays are input for the logic circuit candidate processing (step 18).
b) Contains an array in which the same value is repeatedly entered (step 19)
c) Obtain the number of repetitions of the logic circuit candidate process (step 17), and set it to L. When the number of array elements of the equivalence transfer array is a and the number of array elements of the transfer array scheduled for parallel operation is b (step 21), and when a> b &&bL> a (step 22) is satisfied, bL-a is transferred. The amount can be reduced (step 23), and when b> a &&aL> b (step 24) is satisfied, the transfer amount of a (L-1) can be reduced (step 25). Note that "x &&y" is an operator that returns true when both x and y are true.

When the input sequence satisfies the conditions, the process proceeds to step 26, and the reduced transfer amount and processing speed are integrated with the input / output sequence list for each candidate summarized in step 20 (step 27). As a result, the high-speed performance after optimizing the input of the logic circuit candidate processing is output (step 28). The output is collectively output as a logic circuitization candidate list (3) that can be presented to the user.

FIG. 7 is a flowchart of processing in the description insertion section (4) of FIG. The description insertion unit (4) adds a predetermined function to the logic circuit generated by high-level synthesis of the software description (1) by inserting or changing the description in the software description (1). The operation based on FIG. 7 is as follows.

Step 701: From the logic circuit candidate list (3), the designer selects which part to be logic circuited. The designer selects which process to make a logic circuit in consideration of the amount of resources of the device on which the logic circuit is mounted and the target performance. In this step, it is also possible to provide a function of automatically selecting the one with the shortest transfer time from the logic circuit candidate list (3).

Step 702: A logic circuit as shown in the example of FIG. 6 (600) in order to shorten the transfer time by the equivalence transfer sequence detected by the measurement unit (2) for the logic circuitized location selected in step 701. Align the number of elements of other arrays to the number of elements of the array with the largest number of elements among the arrays to be input to.

Step 703: The input to the logic circuit is limited to one array having the maximum number of elements of the array to be input. As a result, the input interface (IF) to the logic circuit is integrated.

Step 704: Insert the input determination process shown in FIG. 6 (204). A branch is described so that when an equivalence transfer array is input, it is stored in the memory (205) (step 705), and when an array in which a different value is stored is input each time, a parallel operation (201) is performed.

Step 706: In the operation (203) using the equivalence transfer array, the description is changed so that the array stored in the memory (205) described in step 50 is used. As a result, the array can be reused from the memory in the logic circuit without having to repeatedly input the same value.

Step 707: Insert a process of inputting the equivalence transfer array into the logic circuit (200) in advance on the operation description before the parallel operation (201) is performed. This makes it possible to input an equivalence transfer array before the parallel arithmetic processing called repeatedly.

FIG. 8 is an output example of the logic circuit candidate list (3) in FIG. Each logic circuit candidate process is listed as an item, and the number of loops, input / output, and equivalence transfer array when the process is made into a function, and the reduction amount when this embodiment is applied (the reduction amount of input data and Processing time reduction amount) is displayed.

FIG. 9 is a diagram showing an architecture in which the target software according to the embodiment operates. The software that is the target of this embodiment operates by reading the program in RAM (Random Access Memory) (902) by the CPU (Central Processing Unit) (901), and performs some processing by PLD (Programmable Logic Device). (903) It takes the form of the above logic circuit. PLD is, for example, FPGA, and the processing that is the load of software processing is implemented by a logic circuit device. The logic circuit device can execute a plurality of processes in parallel. With this configuration, part of the CPU processing is transferred to the PLD to improve processing efficiency. Each device (54-56) is connected by a bus (904).

The CPU (901) reads the program from the RAM (902) in which the program is stored and performs processing. When executing the logic circuit, the input array is transferred to the PLD (902), and the result is received by the CPU (901) again.

FIG. 10 is a code example in the logic circuit formation shown in FIG. 2, which is shown for comparison. The hardware function (1001) in lines 120 to 125 is a function for forming a logic circuit, and corresponds to the logic circuit B (200B) in FIG. Inside the Hardware function (1001), the input array B [10] is processed by func_once (1002), and the array A [100] is looped 100 times (1003).

When a logic circuit is formed by high-level synthesis, this loop operation (1003) is configured as a parallel operation. The hardware function (1001) is called 100 times by the iterative process (1004) on lines 260 to 263. When high-level synthesis is performed, when this hardware function (1001) is called, processing is passed from the CPU to the logic circuit.

The input to the hardware function (1001) is an array A [100] with 100 elements, an array B [10] with 10 elements, and the output is an array output [100] with 100 elements, as defined in line 120. ]. In the iterative process (1004), the values of the array A [100] are updated every time by the refresh function on the 261st line before the hardware function on the 262nd line is called. Array B is initialized by the initialize function on line 255, and no value assignment processing is performed thereafter.

As a result, for the hardware function (1001), the array A [100] inputs a different value each time, and the array B [10] inputs the same value each time. As described above, the configuration of FIG. 2 has a larger overhead due to repeated input than the configuration of FIG.

FIG. 11 is a code example when the present embodiment has the processing structure shown in FIG. The hardware_manager function (1101) on the 120th to 127th lines is a description of the logic circuit B (200) to which the input determination process (204) and the memory (205) of FIG. 6 are added.

The hardware_manager function (1101) has an array input [100] having 100 elements as arguments, a variable sig as a signal for array determination, and an output array output [100] as defined in line 120. Of these, input [100] corresponds to an interface in which two arrays A [100] and array B [10] in FIG. 10 are integrated. In FIG. 6, as if one array of 100 elements was input to the logic circuit B (200), the array A [100] and the array B [10] are input.

Whether the array input by the array input [100] is the array A [100] or the array B [10] is determined by the argument sig. At this time, if the type of the array can be determined from the type of the array, or if the value of the input array can be used for the determination, the contents of the array may be used for the determination.

The conditional branch on the 122nd and 124th lines corresponds to the input determination process (204) in FIG. 6, and when the array B is input (1103), it is stored in the memory because sig = 0. This memory is a memory (205) inside the logic circuit device, and is not initialized when the logic circuit processing is called from the CPU. In high-level synthesis, the array inside the function is initialized every time it is called, but it can be made an array that is not initialized by declaring it as a global array (1102).

In the code (1105) on the 255th to 257th lines, the array B is stored in the input array input by the function mem_set on the 256th line, the variable sig is set to 0 on the 257th line, and the hardware_manager function (1101) is set. Calling and transferring. This process corresponds to the process (600) in FIG. With the code (1105), only the array B can be transferred to the logic circuit. In the logic circuit (200), when the input input [100] is received, the input judgment process (204) confirms the variable sig in the 122nd line, and if sig = 0, it is judged as the array B, and in the 123rd line. Store in memory (205).

In the code (1106) on lines 258 to 261, the refresh function and the hardware_manager function are repeated 100 times. In the Refresh function, a new value is stored in the array A [100] each time it is repeated. In the 260th line, the logic circuit is called by taking the array A [100] as an input and setting the variable sig to 1. Here, since the array A [100] has the same number of elements as the input [100], direct transfer is possible. When the array A [100] is transferred, the hardware_manager function (1101) executes the call of the hardware function (1107) on the 125th line. The hardware function is a function that performs arithmetic processing equivalent to the hardware function (1101) in FIG.

However, in the call of the hardware function on the 262nd line of FIG. 10, the array A and the array B are fixed as defined on the 120th line, whereas the hardware function on the 125th line of FIG. 11 is fixed. In the call to, both array A and array B are integrated into the input input as defined in line 120, and the value of bram B is called from memory.

In the logic circuit (200), when the input input [100] is received, the input determination process (204) confirms that the variable sig is 1 on the 124th line, and performs the parallel operation (201). Further, the operation (202) is performed using the array A [100] input to the logic circuit and the array B [10] already stored in the memory in the logic circuit as arguments. Here, by referring to the array B [10] from the memory (205) in the logic circuit, the transfer time from the software can be reduced and the processing time of the entire logic circuit can be reduced.

In the above embodiment, the variable sig is used to discriminate the sequences, but other methods such as flagging only one of the sequences may be used.

According to the embodiment described above, in the logic circuit of the software description executed on the CPU, when a place where the parallel operation can be configured by the logic circuit is detected and the process is called a plurality of times in the software description, The speed can be increased by optimizing the input to the logic circuit in consideration of being called multiple times and reducing the transfer amount. As a result, for example, when the logic circuit is called a plurality of times on the software, the input amount to the FPGA is optimized, the transfer time in the entire application is reduced, and the speed is increased.

Claims (15)

When a part of the software description is made into a logic circuit, a process that can be configured in parallel in the logic circuit and is executed multiple times is detected, and the inputs for performing the process in the logic circuit are listed and sent to the logic circuit. A measurement unit that has a function to output the performance when the input amount is reduced as a logic circuit candidate list,
A description insertion unit having a function of inserting a description for reducing the amount of input to the logic circuit into the software description for the logic circuit candidate selected from the logic circuit candidate list.
Circuit design support device equipped with. The description insertion part is
Of the multiple arrays included in the input to the logic circuit, the array that repeatedly inputs the same value is converted to an array with the same number of elements as the other array, and the array converted from the other array is transferred to the logic circuit. Has the ability to change the software description, so that
The circuit design support device according to claim 1. The description insertion part is
It has a function of changing the software description so as to add information that can distinguish the other sequence from the converted sequence when the converted sequence is integrated with the other sequence and transferred to the logic circuit.
The circuit design support device according to claim 2. The measurement unit includes a reduction amount calculation unit.
The reduction amount calculation unit calculates how much the processing time can be shortened by reducing the input amount to the logic circuit, the number of loops of the processing for each processing in the software description, and when the processing is made into a logic circuit. The circuit design support device according to claim 1, which has a function of inputting and outputting an input amount to a reducible logic circuit. The reduction amount calculation unit
Calculates how much processing time can be reduced by reducing the input amount of the array when the input to the logic circuit contains multiple arrays and there is an array that transfers the same value to the logic circuit. To do,
The circuit design support device according to claim 4. The reduction amount calculation unit
Let L be the number of repetitions of the process of making a logic circuit, let a be the number of elements in the array that repeatedly transfers the same value, and let b be the number of elements in the array that transfer different values each time, and the conditions a> b and bL> a are satisfied. When bL−a, b> a and aL> b are satisfied, the transfer amount of a (L−1) can be reduced.
The circuit design support device according to claim 5. The description insertion part is
It has a function of inserting into the software description a process of storing an array in which the same value is repeatedly input in a memory in a logic circuit.
The circuit design support device according to claim 2. The description insertion part is
It has a function of changing the software description so as to refer to the memory instead of the input for a logic circuit that refers to an array that repeatedly inputs the same value.
The circuit design support device according to claim 7. The description insertion part is
It has a function of changing the software description so that an array that repeatedly transfers the same value is input to a logic circuit in advance before a parallel operation is called.
The circuit design support device according to claim 2. It is a circuit design support method that makes a part of the software description into a logic circuit.
Iterative process extraction process that extracts the iterative process that makes a logic circuit from the software description,
In the extracted iterative process, an equivalence transfer sequence extraction process that extracts an input sequence that repeatedly uses the same value, and
A description insertion process that changes the software description so as to convert an input array that repeatedly uses the same value into an array that has the same number of elements as other input arrays.
Circuit design support method to perform. When converting an input array that repeatedly uses the same value into an array having the same number of elements as other input arrays, the software adds information that can distinguish the converted input array from other input sequences. Change the description,
The circuit design support method according to claim 10. The software description is modified so that the input array that repeatedly uses the same value is stored in the memory of the logic circuit before the iterative processing is performed in the logic circuit.
The circuit design support method according to claim 10. When the repetitive processing is performed in the logic circuit, the software description is changed so that the same value is called from the memory and the processing is performed.
The circuit design support method according to claim 12. An output process that outputs a logic circuit candidate list that displays the extracted iterative process in association with a change in performance due to a change in the software description.
A selection process for selecting an iterative process for making a logic circuit from the logic circuit candidate list
10. The circuit design support method according to claim 10. An information processing device including a CPU, a logic circuit, and a memory, which calls the logic circuit to execute a part of the processing when the software stored in the memory is executed by the CPU to perform processing.
When the CPU calls the logic circuit to execute a part of the processing, the CPU includes an array in which the input of the processing executed by the logic circuit includes a plurality of arrays and the plurality of arrays repeatedly input the same value. When it is included, an array that repeatedly uses the same value is converted into an array having the same number of elements as other arrays and transferred to the logic circuit.
The logic circuit stores an array in which the same value is repeatedly used in the built-in memory, and performs processing using the array stored in the built-in memory.
Information processing device.

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