JP2002268607A - Matrix type display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption due to the voltage change in segment signal lines at the time of performing assigning intensity levels by a PWM (pulse width modulation) in a display device selecting plural lines. SOLUTION: In this display device, power consumption is reduced while lessening probability in which the voltage change is occurred in the boundary between horizontal scanning periods by changing the counting method of a counter part 15 for controlling selectors 16 for every horizontal scanning period in the selectors 16 for selecting of voltage values corresponding to respective bits of input data to be impressed on segment signal lines and for controlling selection periods of the voltage values, that is, pulse widths to make the selector input which is selected in a certain horizontal scanning period and the selector input which is selected at the beginning of a horizontal scanning period next to the certain horizontal scanning period coincide.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a matrix pixel structure.

[0002]

2. Description of the Related Art As one of the gray scale display systems of a display device having a pixel structure on a matrix, a frame rate control system for performing gray scale expression by using a plurality of frames and controlling on / off for each frame. FR
C). FIG. 17A shows an example in which the first gradation of the eight gradations is expressed.
This can be displayed by displaying the frame. However, there is a problem that flicker occurs when the number of gradations is increased by this method. Therefore, there is a method of suppressing flicker by shifting the timing of ON and OFF for each pixel and adjusting the ratio of the ON pixel and the OFF pixel to the number of gradations spatially. FIG. 17B shows a pattern that realizes this. FIG. 17B shows a display state of the pixel matrix, in which rows are expressed as common or lines, and columns are expressed as segments or columns. In this method, for example, when expressing the Mth gradation out of the N gradations, in the first row, the pixels from the first column to the Mth column are sequentially turned on, and the next (N−
M) Turn off the column and repeat on and off at this rate until the last column. In the second row, the data in the first row is shifted by a certain value L and displayed in order to disperse the on / off pixels. Hereinafter, the display is shifted by L for each line. The shift amount L at this time is defined as a line shift. This makes it possible to spatially disperse the ON / OFF. Next, the on / off state is temporally dispersed. The data in the first column of the second frame is shifted and displayed by a certain value F in the same manner as the line shift with respect to the data column of the first column of the first frame. The shift amount F at this time is defined as a frame shift. Similarly, in the third and subsequent frames, a pattern shifted by F from the first data row of the previous frame is displayed. The second and subsequent columns of each frame are displayed with a line shift similarly to the first frame. FIG. 17B shows a line shift L.
(= 1), this is an example in which the first gradation of eight gradations is expressed using a frame shift F (= 3). Although the description is made here with 7 rows and 7 columns, it is sufficient to arrange these 7 rows and 7 columns vertically and horizontally on a large screen. The proportion of ON pixels is the same in all frames, and when a certain pixel, for example, 173 pixels is viewed, it is OFF / OFF / ON / OFF / OFF / OFF / OFF, and one of eight gradations is expressed. I have. However, even if the ON and OFF pixels are dispersed as described above, flicker becomes noticeable as the number of frames required for gradation expression increases, and it is necessary to increase the frame frequency as a countermeasure.
When the frame frequency is increased, the power consumption is increased, and it is practically difficult to perform the gray scale expression of 32 or more gray scales.

As another gradation display method, there is a pulse width modulation (Pulse Width Modulation) method. The gradation expression is performed by changing the ratio between the width of the pulse indicating ON and the width of the pulse indicating OFF according to the number of gradations. For example, in the case of 16 gradation display, the length of one selection period is set to 8 /
Four pulses having pulse widths of 15, 4/15, 2/15, and 1/15 are prepared, and a pulse representing ON in the four pulses is selected according to the gradation, thereby providing 16 gradations. To express.

[0004]

SUMMARY OF THE INVENTION Pulse width modulation (PW
In the case of performing gradation expression by M: Pulse Width Modulation, increasing the number of display gradations increases the number of pulses prepared in one selection period. In 16 gray scale display, the number of necessary pulses is four, but in 64 gray scales, six are required. A display device is generally a capacitive load, and when a pulse is applied, a rounded waveform is observed at the time of rising and falling. When the number of pulses increases, the pulse width of one pulse is inevitably reduced, so that the influence of rounding on the pulse width increases and the deviation of the applied voltage affects brightness. In addition, repeating on and off means charging and discharging of electric charge to the panel. The power consumption increases as the number of on / off repetitions increases, and becomes more remarkable as the number of pulses increases. For example, if six pulses were required and each pulse turned on / off / on / off / on / off, three charges and three discharges occurred during the selection period of a pixel. I do.
In FRC, since there is only one pulse in one selection period and one charge or discharge, the PWM is FR
There is a problem that power consumption increases as compared with C.

According to the present invention, in the case of performing gradation expression by PWM, a pulse indicating ON and a pulse indicating OFF are arranged as close to each other as possible so as to change the brightness of the display area due to the rounding of the waveform and repeat the on / off operation. A multi-line simultaneous selection method (MLS: Mult), which is said to be suitable for displaying moving images, by providing a display device with reduced power consumption and reduced gradation by reducing the number of times of charging and discharging
PWM suitable for i Line SelectionMethod) circuit configuration
It is an object to provide a gradation display method.

[0006]

In order to achieve this object, a display device according to the present invention is a matrix type device which simultaneously selects a plurality of rows (N rows) of common signal lines and performs gradation display by a pulse width modulation method. In the driving method of the display device, power consumption is changed by changing the order of applying a plurality of pulses existing in one selection period, changing the pulse width and the number of pulses so that the on-pulse and the off-pulse are not adjacent to each other as much as possible. , And a reduction in display quality is reduced.

[0007]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of the Invention) FIG. 1 shows a functional block diagram according to a first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a controller which supplies various control signals required for MLS and pulse width modulation (PWM), 12 denotes a memory for storing external data, 13 denotes an orthogonal function generator, and 14 denotes an orthogonal function matrix generated by 13. , An MLS operation unit that performs an operation on the data output by the elements 12, 15 is a counter unit, 16 is a selector, and 17 is a decoder circuit.

Note that the reference numeral 12 need not necessarily be provided inside the display device, but may be provided as a storage device outside the display device and send an output according to the control of the controller 11 to the display device.

[0010] Multi-Line-Selecti
on method: MLS), the input signal S211 and the orthogonal function generator 213 as shown in FIG.
The orthogonal function matrix H215 generated by
2 to perform an H × S matrix operation to obtain a segment signal line 2
14 is output. At the same time, a voltage proportional to an element of each row of the orthogonal function matrix H is sequentially applied to the common signal line every horizontal operation period, and the voltage applied between the common signal line and the segment signal performs on / off display of pixels. is there.

Next, the operation of the configuration shown in FIG. 1 will be briefly described. The input data 18 is a video signal to be displayed on the pixel of each corresponding segment signal line, and is generally a multi-tone signal. The data stored in the memory 12 is sequentially input to the MLS operation unit 14 under the control of the controller 11.

The number of columns of the orthogonal function matrix H215 is equal to the number of common signal lines, and its elements have a value of 1 or -1 when the common signal line is selected, and have a value of 0 when not selected. Therefore, in the case of simultaneous selection of N rows, since the orthogonal function 215 has N 1 or −1 in one row, to calculate H × S corresponding to a certain horizontal scanning period, the input signal matrix S211 is used.
Is required for at least N rows corresponding to the selected common signal line. Therefore, the input signal 211 is input to the arithmetic unit 212 at the same time (at least within one horizontal scanning period) for the number of simultaneously selected common signal lines N. Therefore, it is necessary to simultaneously input N rows of data to the MLS calculation unit 14 in at least N rows during one horizontal scanning period. For this purpose, for example, the line carrying the input signal must be N
It is also possible to provide one, or to perform high-speed transfer with one.

FIG. 7 shows an MLS operation section, a selector section, a decoder section, and a counter section when input data is 4 bits and a 4-row simultaneous selection method is used. In the PWM driving method, the number of the MLS arithmetic units 7 equal to the number of bits of the input signal is
1 is prepared, an MLS operation is performed for each bit, a voltage value to be applied is calculated and latched. One of the latched voltage values is selected by the selector circuit 73 and applied to the segment signal line. The period during which the voltage value of each bit is selected differs depending on the bit. The least significant bit (LSB) is the shortest, and the pulse width modulation is performed by making the selection period twice as large as that of the preceding bit toward higher bits. This is L
This is because, while the SB is on, the intensity is 1, while the upper bit is on the intensity 2, and the upper bit is on the intensity 4. This intensity difference is expressed not by a voltage value but by a time for applying ON, that is, a pulse width. The counter circuit 74 is for controlling the selection period of the selector circuit 73, and according to the counter value of the counter circuit 74,
The output of the selected MLS operation unit is changed.

As described above, by preparing a number of arithmetic units corresponding to the number of bits of input data, only one access to the memory 72 is required within one horizontal scanning period, and the internal clock can be reduced. , Leading to lower power consumption.

(Embodiment 2) Assuming that the display device can display approximately 260,000 colors, each of the red, green, and blue input data requires 6 bits. In order to realize the PWM driving, six MLS operation units are required for one segment signal line. On the other hand, when displaying 256 colors, red and green each have 3 bits, and blue has 2 bits. At this time, three of the MLS calculation units in each segment signal line are unnecessary for red and green, and four for blue are unnecessary. If this unnecessary MLS operation unit is not operated, power consumption can be reduced. As shown in FIG. 8, a data format detecting means 85 for detecting the number of displayable colors of the input data 18 is provided as shown in FIG. By sending the result to the MLS operation unit 14, the number of operation circuits operated by data can be changed. Since there are at least as many arithmetic circuits as the product of the number of segment signal lines and input data, changing the number of operation arithmetic circuits according to the number of input data is effective in reducing the power consumption of the display device.

(Embodiment 3) The problem of gradation control by PWM is that as the number of gradations increases, the number of voltage changes of the segment signal line increases in one horizontal scanning period, and the power for charging increases. Increase.

For example, in the case of 16 gradation display, within one horizontal scanning period (1H period), the length of one horizontal scanning period is
When four pulses of / 15, 2/15, 4/15, and 8/15 are present and all have different voltage values, 5 pulses within 1H period
The voltage value changes. In the case of 32 gradations, it changes six times, and the power consumption increases accordingly.

In addition, since a display device is generally a capacitive load, when a pulse waveform is applied, a rounding of the pulse waveform due to the capacitance of the display unit and the wiring resistance to the display unit is observed. The voltage value applied to the display device changes due to the rounding, and a pulse having a smaller width is more susceptible to a change in the voltage value due to the rounding to the voltage value.

In order to reduce the influence of the waveform rounding, there is a method of reducing the capacitance of the display device, and a method of using low-resistivity gold or the like for the wiring in order to lower the wiring resistance. It is not easy to change the material used for the display unit or to increase the distance between the common signal line and the segment signal line. Using gold for wiring is not realistic in terms of manufacturing costs.

Therefore, as a method of reducing waveform rounding from the driving surface, there is a method of reversing the order of pulses applied to the segment signal line every 1H period. 3 shows a voltage waveform on a segment signal line shown in FIG. FIG. 2A shows a signal waveform in a case where uniform display of gradation 5 is performed by a conventional method. Looking at this waveform, the voltage changes each time a different pulse is applied. FIG. 2B shows a third embodiment of the present invention. The order in which pulses are input is reversed every 1H period. In the odd-numbered 1H periods, the pulses are applied in the order of increasing pulse width, and in the even-numbered 1H periods, the pulses are applied in the order of decreasing pulse width. As a result, two pulses having the same pulse width are continuously generated at the boundary 21 or 22 between the 1H periods, and the number of changes in the segment voltage is reduced. (B) is reduced to three times compared to five times in (a). Focusing on the boundary 21 of the 1H period, the pulse 1 having the narrowest pulse width is adjacent, and the rising and falling of the pulse which is two places in the conventional driving method is one in the present invention, and the pulse 1 is adjacent. Since there is no waveform rounding in the portion, the influence of the brightness change due to the waveform rounding can be reduced.

Further, since the number of times of voltage change is reduced, the electric power for charging the segment signal lines and the display device is reduced, so that the electric power can be reduced.

As a method of changing the order of the pulses applied every 1H period, the counter method of the counter circuit 15 shown in FIG. 1 may be changed. FIG. 10 shows the inside of the counter circuit 15 and the selector 16. The pulse application order and the pulse width are defined by the counter 101 of the counter unit 15. By changing the value of the bit selection register 102 in accordance with the output of the counter 101, FIG.
The MLS operation output is selected according to the truth table shown in FIG. The counter 101 counts the required number of gradations minus one within the 1H period, and the count intervals are equal. The data output to the decoder circuit depends on the MLS,
It is determined whether to take the operation output, and the output having a long pulse width is output to the decoder using a plurality of count values. For example, in the case of 64 gradation representation, the counter is a 63-ary counter, and the selection period of the voltage having the narrowest pulse width is counted 6
The pulse width modulation can be performed by selecting only the longest one in the period of counts 0 to 31.

Therefore, as shown in FIG. 2B, in order to change the order of applying pulses every 1H, the counter 101
May be changed from an up counter to a down counter. At the time of up-counting, the pulse is applied sequentially from the longest pulse, and at the time of down-counting, the pulse is applied sequentially from the shortest pulse. Fig. 2 (b) if changed every 1H
Is obtained.

In this example, an example is shown in which the pulses are inputted in the order of the pulses 8, 4, 2, 1 or in the reverse order.

Since the influence of waveform rounding is reduced at both ends of the 1H period, it is necessary to apply two pulses having a narrow pulse width, which are particularly susceptible to waveform rounding, to both ends of the 1H period. Thus, the effect of waveform rounding can be minimized. In the example of FIG. 2, pulses 1 and 2 are set to 1
It is most effective to bring it to both ends of the H period. In order to adopt this method, the truth table shown in FIG. 11 may be modified as shown in FIG. 15 so that two pulses having a narrow pulse width are always present at both ends of the 1H period in up-counting and down-counting. Note that the positions of Q0 and Q1 may be interchanged.
The values of 2 to Q5 are arbitrary between Q2 and Q5.

(Embodiment 4) Since a high-frequency component is generated temporarily when the segment voltage is switched, a hazard corresponding to the change in the voltage of the segment signal is also applied to the common signal line via the capacitive display unit. appear. This is shown in FIG. When the absolute value of the changing value is large, the hazard of the common signal line increases as the number of simultaneously changing segment signal lines increases. Due to this hazard, the luminance changes because the effective value of the voltage applied to the display unit changes. In particular, the effect is greatly exerted on a portion where the segment signal line has not changed. In order to avoid this decrease, it is preferable to reduce the number of segment signal lines that simultaneously cause a voltage change in the same direction.

For this purpose, there is a method of changing the order of applying pulses for each segment signal line. Embodiment 3
As shown in FIG. 10, the counting method of the counter 101 in FIG. 10 may be reversed for even columns and odd columns, or the counting may be reversed for each display primary color. Since it is necessary to perform different counts at the same timing, unlike the third embodiment, a plurality of counters A15a and B15b are provided in the counter unit 15 as shown in FIG. This can be realized by reference. For example, for a certain 1H, the counter A counts down, and the counter B counts up.
As shown in (b), the timing of the voltage change is shifted at least in the adjacent lines, and the influence of the differential waveform on the common signal line can be reduced.

As another method of shifting the pulse switching timing, there is a method of changing the initial value of the counter for each segment signal line. FIG. 13 shows an example at the time of expressing 16 gradations. 1 for segment signal line 1
Since the quinary counter counts from 0, it is applied sequentially from the pulse width 8. In the segment signal line 2, the pulse width of 1
Are sequentially applied. Similarly, in the segment signal line 3, 1
2, the pulse width is applied in order from 2. By doing so, it is possible to shift the timing of the voltage change in each signal line, reduce the influence of the differential waveform on the common signal line,
This makes it possible to reduce the influence of a change in luminance on a signal line whose voltage value does not change. The setting of the initial value of the counter may be configured such that a signal designating the initial value from the outside is taken into the counter as the counter initial value setting signal 104 as shown in FIG. 10, and the initial value is read from the signal for each horizontal synchronization signal. Note that a plurality of counters are required to make the initial values different, and the configuration may be as shown in FIG.

(Embodiment 5) In the decoder unit 17 of FIG. 1, when selecting a voltage to be applied to the segment signal line according to the output of the counter unit 15, two voltages are simultaneously selected at a data break. May be done. At this time, a through current corresponding to the difference between the two voltages flows inside the circuit and consumes unnecessary power. Therefore, as shown in FIG. 9, an enable signal 91 is provided, an enable signal is input when the selector output 92 changes, and no voltage value is selected when the enable signal is input as shown in the truth table. The segment signal line 93 is set to a high impedance state to prevent a through current from flowing. In this example, the enable signal 9
Although 1 is used as another signal, for example, in the case of simultaneous selection of 4 lines, the output is quinary, but the selector output 9 for controlling it is 9
2 requires 3 bits. In the case of 3 bits, up to 8 states can be expressed, so that there are three more for quinary voltage selection.
The surplus data may be used in place of the enable signal to set the output to an undefined state when the data is input.

(Embodiment 6) In Embodiment 3 of the present invention, in order to reduce the influence of pulse rounding, a pulse having the same pulse width as the last pulse in a certain 1H period and the first pulse in the next 1H period are inserted. As described above, the counting method of the counter is reversed every 1H period, but a method of changing the initial value of the counter every 1H period can also be realized.
That is, each time the horizontal synchronization signal is input, the counter refers to the information of the initial value that changes every 1H, and outputs the initial value. Subsequent counting methods are optional because the same effect is obtained for both down-counting and up-counting. Here, if the initial value is set to the first count value of the last pulse of the previous 1H period, it is set to 2 on the boundary of the 1H period.
And the same pulse can be applied. The number of gradations and the current 1
Since the last pulse of the 1H period can be specified from the initial value of the H period, it can be realized by referring to the initial value of the current 1H period and rewriting the initial value before the next 1H period. FIG. 14 shows an example of 16 gradation display. As shown in 141, the last pulse of a certain 1H period is always the same as the last pulse of the next 1H period, and when the same gradation display is performed along the segment signal line, the number of times of voltage change is reduced. Is possible.

(Embodiment 7) The minimum pulse width in PWM is determined by the number of display gradations and the frame frequency. As the number of display gradations increases and the frame frequency increases, the minimum pulse width decreases, and the effect of waveform rounding increases. When the frame frequency is reduced, flicker is likely to occur. Therefore, it has been considered that driving can always be performed at an optimum frame frequency according to the number of display gradations. As shown in FIG. 8, the number of bits of the input data is detected by using a data format detecting unit 85, and a plurality of oscillators 81 and 82, a switching circuit 83, and a frequency dividing circuit 84 are prepared. An optimum frequency is selected from the results of step 85, and a frame frequency suitable for the number of display gradations is provided. If the frame frequency can be changed according to the number of display gradations, it is possible to reduce the power consumption by increasing the frame frequency only when necessary and usually driving at a low frame frequency.

The present invention can be implemented by a combination of the first to seventh embodiments.

In the third, fourth and sixth embodiments, external switching means 61 is provided as shown in FIG. 6 so that the initial value of the counter can be set and the counting direction of the counter can be externally set. Is also good. If several types of settings are prepared, it is also possible to adjust according to the user's preference.

The case of simultaneous selection of four lines has been described. However, in general, when displaying by simultaneous selection of N lines, image data of N lines is simultaneously transferred, so that NLS operations can be performed simultaneously on N lines. by doing,
Similar effects can be obtained.

Although the type of the segment voltage value is the N + 1 value, the effect of the present invention does not decrease as compared with the type of the voltage value, and the change tends to occur at the transition of the pulse with the increase of the voltage value. Therefore, the effect becomes large.

Similarly, regarding the number of gradations, the number of MLS calculators increases with the number of gradations, the input of the selector circuit increases, and the count value of the counter is reduced by the number of gradations minus one.
A similar effect can be obtained by using a binary counter.

[0037]

As described above, according to the present invention, when performing gradation expression by PWM in the N-row simultaneous selection method, the order of the pulses input to the segment signal lines is temporally changed, whereby the voltage of the segment signal is changed. Reduce the number of times of value change and reduce power consumption. In addition, by spatially changing, it is possible to reduce the influence of voltage fluctuation on the common signal line and improve display quality. Further, it is possible to measure a reduction in power consumption by changing the operation and stop of the MLS operation unit and changing the frame frequency according to the number of bits of input data.

[Brief description of the drawings]

FIG. 1 is an MLS of a display device according to a first embodiment of the present invention.
The figure which showed the functional block of the drive part and the PWM gradation control part.

FIG. 2 is a diagram showing a segment signal line waveform according to a third embodiment of the present invention.

FIG. 3 is a diagram illustrating a relationship between pulse switching timings in two segment signal lines according to a fourth embodiment of the present invention.

FIG. 4 is a diagram showing an example of a waveform of a segment signal line when a pulse is applied in order of each voltage value in the embodiment of the present invention.

FIG. 5 is a diagram showing waveforms of segment signal lines when different combinations of pulse widths are used in the embodiment of the present invention.

FIG. 6 is a diagram showing functional blocks provided with external switching means so as to be able to select a conventional example and an embodiment of the present invention.

FIG. 7 is a diagram showing a block of an MLS drive circuit according to the first embodiment of the present invention;

FIG. 8 shows an MLS according to the second and seventh embodiments of the present invention.
Diagram showing a functional block diagram for controlling gradation by PWM in driving

FIG. 9 is a fifth embodiment of the present invention, showing a segment signal line output with respect to a selector output.

FIG. 10 is a diagram showing a counter unit and a selector of a PWM control circuit according to a third embodiment of the present invention.

FIG. 11 is a diagram showing a truth table of the selector circuit of FIG. 10 according to the third embodiment of the present invention;

FIG. 12 shows a PW of a display device according to a fourth embodiment of the present invention.
Diagram showing M drive block

FIG. 13 is a diagram showing an embodiment of a waveform of a segment signal line according to the fourth embodiment of the present invention;

FIG. 14 is a diagram showing waveforms of segment signal lines according to the sixth embodiment of the present invention.

FIG. 15 is a diagram illustrating a truth table of a selector unit according to the embodiment of the present invention.

FIG. 16 is a diagram showing an input signal operation circuit for obtaining a segment signal output in the multiple line selection method.

FIG. 17 is a diagram showing an on / off pattern in FRC gradation display.

[Explanation of symbols]

 11 Controller 12 Memory 13 Orthogonal Function Generator 14 MLS Operation Unit 15 Counter 16 Selector 17 Decoder Circuit 18 Data

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) G09G 3/20 623 G09G 3/20 623C 641 641A (72) Inventor Atsuhiro Yamano 1006 Kadoma Kadoma, Kadoma City, Osaka Prefecture F-term (reference) in Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] 1. A method for driving a matrix type display device in which a plurality of rows (N rows) of common signal lines are simultaneously selected and gradation display is performed by pulse width modulation, wherein a plurality of different widths are set within one horizontal scanning period. When applying pulse waveforms with
A driving method for a matrix type display device, wherein the order of applying the plurality of pulse waveforms having different widths is reversed for each horizontal scanning period. 2. A method for driving a matrix type display device in which a plurality of rows (N rows) of common signal lines are simultaneously selected and gradation display is performed by pulse width modulation, wherein a plurality of different widths are set within one horizontal scanning period. When applying pulse waveforms with
A method for driving a matrix-type display device, wherein the order of applying the plurality of pulse waveforms is different for each segment signal sequence. 3. A matrix type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing gradation display by pulse width modulation, wherein a changeover switch is provided outside the display device, and a switch is provided within one horizontal scanning period. In the matrix type display device, when applying a plurality of pulse waveforms having different widths in order, it is possible to select whether or not to change the order in which the plurality of pulse waveforms are applied by the external changeover switch. 4. A matrix-type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing grayscale display by pulse width modulation, comprising: a plurality of arithmetic units; a latch circuit for storing an arithmetic result; An orthogonal function generator, a selector circuit, and a decoder circuit, wherein the number of the arithmetic units is equal to the number of bits of the input video signal line, and the arithmetic units are connected to each bit of the input video signal line in a one-to-one correspondence A matrix type display device characterized in that a calculation result for each bit stored in a latch circuit is sequentially selected by a selector and gradation selection is performed by pulse width modulation. 5. In a matrix type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing gradation display by pulse width modulation, an orthogonal function generator, an exclusive function of orthogonal function elements and data, A plurality of arithmetic units for calculating a logical sum,
A latch circuit for storing an operation result, a selector circuit, a decoder circuit, and a bit number detecting means for input data, wherein the plurality of arithmetic operations are performed by the number of bits of the input data from the result of the bit number detecting means. A matrix type display device characterized by operating a display. 6. A matrix display device which simultaneously selects a plurality of rows (N rows) of common signal lines and performs gradation display by pulse width modulation, wherein a plurality of oscillators and one of outputs of the plurality of oscillators are provided. A switching circuit for selecting a frequency, a frequency dividing circuit for lowering the frequency of the oscillator, a data format detecting means for detecting information of input display data, a storage means for storing the input display data, and an orthogonal function generator. Unit, an element of the orthogonal function generated by the orthogonal function generation unit, and an MLS operation unit that calculates an output of the storage unit;
A selector unit for controlling the selector, the selector unit selecting one of a plurality of outputs of the MLS operation unit, and the data format detecting unit determining a number of colors of the input data. A matrix-type display device which detects a moving image and a still image, controls the switching circuit and the frequency dividing circuit based on the detection result, and switches a frame rate. 7. A matrix type display device which simultaneously selects a plurality of rows (N rows) of common signal lines and performs gradation display by pulse width modulation, wherein the orthogonal function generator and the orthogonal function generator generate the orthogonal signal. It comprises an orthogonal function element, an MLS operation unit for operating an input video signal, a selector unit, and a counter unit for controlling the selector, wherein the selector unit is one of a plurality of outputs of the MLS operation unit. A matrix type display device characterized in that when selecting and applying a voltage to the segment signal line, the segment signal line is temporarily disconnected from the output when the voltage of the segment signal line is switched, thereby setting the voltage to an undefined state. 8. A matrix type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing gradation display by pulse width modulation, comprising: an orthogonal function generator; an element of the orthogonal function; , A selector for selecting one of a plurality of outputs output from the calculator, a counter for controlling the selector, and a decoder for converting the output of the selector to a voltage to be applied to the segment signal line. A selector, wherein the selector selects one of the input signals according to the value of the counter unit, a plurality of the counter units are prepared, and the selector connected to at least an adjacent segment signal line is connected to a different counter unit. The selector operates the selector at different times by setting all the initial values for counting to different values. A matrix type display device characterized by the above-mentioned. 9. A matrix type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing gradation display by pulse width modulation, comprising: an orthogonal function generator; an element of the orthogonal function; , A selector for selecting one of a plurality of outputs output from the calculator, a counter for controlling the selector, and a decoder for converting the output of the selector to a voltage to be applied to the segment signal line. A selector, wherein the selector selects one of the input signals according to the value of the counter unit, a plurality of the counter units are prepared, and the selector connected to at least an adjacent segment signal line is connected to a different counter unit. The selector changes the initial value for starting counting every horizontal scanning period, and sets the initial value of the counter and the display level in a certain horizontal scanning period. The initial value of the counter for the next horizontal scanning period is determined from the tonal number, and the pulse width applied at the end of a certain horizontal scanning period and the pulse applied at the beginning of the next horizontal scanning period of a certain horizontal scanning period A matrix-type display device, characterized in that the widths of the pixels are equal. 10. A matrix type display device for simultaneously selecting a plurality of rows (N rows) of common signal lines and performing gradation display by pulse width modulation, comprising: an orthogonal function generator; , A selector for selecting one of a plurality of outputs output from the calculator, a counter for controlling the selector, and a decoder for converting the output of the selector to a voltage to be applied to the segment signal line. A selector, wherein the selector selects one of the input signals according to the value of the counter section, and when the counter has an initial value and a final value, the selector selects the most of the input data among the outputs of the plurality of operation sections. A matrix type display device, wherein an operation result of an upper bit or an operation result of a least significant bit is selected. 11. A method of driving a matrix type display device in which a plurality of rows (N rows) of common signal lines are selected at the same time and gradation display is performed by pulse width modulation. In a drive circuit that performs an operation for each bit, selects one of a plurality of outputs generated by the selector, and outputs the output to a segment signal line, changes an initial value and a counting method of a counter unit that controls the selector. Wherein the switching timing of at least one of the selectors existing for each segment signal line is changed.