JP2002196729A - Matrix type display device and adjusting method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent flickers when gradations are displayed by FRC(Frame Rate Control) in a display device performing multi-line selection. SOLUTION: The lowest frequency causing flickers differs depending on whether input data are for a moving picture or for a still picture, and also on the number of colors. Therefore, the display device is designed so as to detect a data form and adopt a flicker processing method and a frame frequency suitable for each form, thereby realizing a low power flicker processing circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display having a matrix pixel structure.

[0002]

2. Description of the Related Art As one of the gray scale display methods, there is a frame rate control method (FRC) in which a plurality of frames are used and a column voltage is controlled for each frame to perform a gray scale expression. FIG. 17A shows an example in which the first gray scale out of the eight gray scales is displayed, and display can be performed by displaying one frame on and six frames off. However, there is a problem that flicker occurs when the number of gradations is increased by this method. Therefore, there is a method of suppressing flicker by shifting the timing of ON and OFF for each pixel and adjusting the ratio of the ON pixel and the OFF pixel to the number of gradations spatially. FIG. 17B shows a pattern that realizes this. In this method, for example, when expressing the M-th gradation out of the N gradations, the M-th column is turned on in order from the first column in the first row, the (N-M) -th column is turned off in order, and up to the last column. On and off are repeated at this rate. In the second row, the data in the first row is shifted by a certain value L and displayed in order to disperse the on / off pixels. Hereinafter, the display is shifted by L for each line. The shift amount L at this time is defined as a line shift. This makes it possible to spatially disperse the ON / OFF. Next, the on / off state is temporally dispersed. For the first column of the first frame, the data of the first column of the second frame has a value F similar to the line shift.
Only shift and display. The shift amount F at this time is defined as a frame shift. Similarly, in the third and subsequent frames, a pattern shifted by F from the first data row of the previous frame is displayed. The second and subsequent columns of each frame are displayed with a line shift similarly to the first frame. FIG. 17B shows an example in which the first gradation of eight gradations is expressed using the line shift L (= 1) and the frame shift (= 3). Note that, here, the description is made in seven rows and seven columns.
It suffices to arrange the rows and columns in rows and columns. The proportion of ON pixels is the same in all frames, and when a certain pixel, for example, 173 pixels is viewed, it is OFF / OFF / ON / OFF / OFF / OFF / OFF, and one of eight gradations is expressed. I have.

[0003]

SUMMARY OF THE INVENTION FRC (Frame Rate)
Control), when the number of display gray scales increases, a gray scale in which the ratio of the number of times of on to the number of times of off becomes small occurs, so that flicker is likely to occur.
There is a method of reducing flicker by increasing the frame rate, but power consumption increases. For example, while gradation is expressed by 7 frames in 256-color display, 15 frames are required in 4096-color display. To simply make the flicker level the same, the frame rate must be approximately doubled. On the other hand, the power supply of mobile terminals such as mobile phones is limited, and it is required to reduce power consumption. Also, the display device has a narrower frame,
The circuit for preventing flicker needs to be simple from the viewpoint of cost reduction.

[0004] The present invention solves the above-mentioned conventional problems and provides an FR.
In the case of performing gradation display by C, it is necessary to increase the number of displayable gradations without increasing the frame rate and the circuit scale, and to select a plurality of lines simultaneously (MLS: Multi) which is said to be suitable for displaying moving images. Line Selection Me
It is an object of the present invention to provide an FRC gradation display method suitable for the circuit configuration of (thod).

[0005]

In order to achieve this object, a display device according to the present invention changes an on / off pattern for each frame and each line on a display surface and distributes on and off as randomly as possible. It has a configuration to reduce flicker.

[0006]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment of the Invention) FIG. 1 shows a functional block diagram according to a first embodiment of the present invention. The present invention relates to FR
A gradation register circuit 192 for outputting C data, a gradation control unit 191 for shifting the gradation register for each horizontal synchronization signal 193 or vertical synchronization signal 194, and a gradation for selecting the gradation register output by the input video signal 196. The tone selection circuit 195 is provided. Multiple line selection method (Mu
In the lti-Line-Selection Method (hereinafter referred to as MLS), the input signal S211 and the orthogonal function H215 generated by the orthogonal function generator 213 as shown in FIG.
Is subjected to an H × S matrix operation by the arithmetic unit 212 to obtain H × S
According to the value obtained by the operation result of S, the segment signal line 21
4 is changed, and an on / off display is performed by a voltage applied between the common signal line and the segment signal. Orthogonal function H
The number of columns 215 is the number of common signal lines, and has a value of 1 or -1 when a common signal is selected, and has a value of 0 when not selected. Therefore, in the case of simultaneous selection of N rows, the orthogonal function 215
Since N has 1 or −1 in one row, at least N row data of the input signal S211 is required for the calculation of H × S. Therefore, the input signal 211 is input at the same time for the number of simultaneously selected N lines of the common signal line. Therefore, the input video signal 196 of the gray scale selection circuit 195 of FIG. 1 is simultaneously input to N rows, and if all the N rows have the same gray scale, the same gray scale register output is selected. FIG. 3 shows a gradation selection circuit 195 according to the present invention.
The output of FIG. In FIG. 3, a white circle 2 is a pixel in an ON state, and a hatched circle 1 is a pixel in an OFF state. In this figure, the first gray scale out of 8 gray scales is displayed on the entire screen by using the 4-line simultaneous selection method. The on / off pattern is the same for every four lines for simultaneous selection of four lines, and the pattern is shifted for each set of four lines having different input times, which is a feature of the first embodiment of the present invention.

By adjusting the shift amount for each four lines (line shift) and the shift amount for each frame (frame shift) by this method, the frame shift is set to 3 or 5 and the line shift is set to 3 or 5 in the 8-gradation display. If set to any one, flicker can be eliminated at a frame frequency of 120 Hz.

It is said that when ± V2 occurs among the five segment output values, the image quality deteriorates. For example, when an image is displayed only at ± V2 and Vc, flicker due to interference with a 50 Hz fluorescent lamp is likely to occur. In the gradation display method according to the present invention, by taking the orthogonal function as shown in FIG. 15, when the entire screen has the same gradation, the on-off data is on for all four rows or off for all four rows. , The operation result of the orthogonal function is 2 or -2. Generally, the result of the operation is 4, 2, 0, -2,
-4, and 4 is a voltage value V2 (= 2 × V1),
2 is applied to the segment signal line as V1, 0 is Vc, -2 is -V1, and -4 is -V2. Therefore, in Embodiment 1 of the present invention, ± V2 does not occur, and a display with little deterioration in image quality can be performed. Further, there is no need to add a circuit that does not generate ± V2, and the circuit scale can be reduced accordingly.

(Embodiment 2) FIG. 4 shows an FRC image pattern according to a second embodiment of the present invention. 3 is different from FIG. 3 in that at least two types of line shifts are used, and different values can be taken as a line shift A3 and a line shift B4. The point is that it can be set individually.

In the above-described configuration, the on-pixels 2 are arranged obliquely and regularly in FIG. 3 by making the values of 3 and 4 different from each other. Even in this case, since the four lines have the same on / off data, there is no occurrence of V2. Line shift is A, B2
Since there are two types, a register for holding two types of line shift values and a circuit for discriminating which of A and B to execute are added, which leads to a slight increase in circuit scale. It was found that flicker was reduced at about 100 Hz.

(Embodiment 3) FIG. 20 is a block diagram of gradation processing according to a third embodiment of the present invention. The difference from FIG. 1 is that a RAM that holds the shift amount of at least one of the even-numbered row and the odd-numbered row in the set of N rows, and an R that holds the shift amounts of the line shift and the frame shift
It has a shift amount holding RAM 201 made of AM and a microcomputer 202 for rewriting the RAM. As a result, the gradation control unit 191 sends the input synchronization signal 19
3 and 194, the shift amount holding RAM 201
, And shifts the register in the gradation register circuit 192 based on this data. Thereby, different register outputs can be obtained for the even-numbered rows and the odd-numbered rows in the set of N rows. FIG. 5 shows a third embodiment of the present invention. In this example, N =
In this case, the four-row simultaneous selection method of No. 4 is used, and the first gradation of eight gradations is displayed. In the first and second embodiments, the shift is performed every four rows. In this embodiment, in addition to the shift performed every four rows, different on / off data is obtained in even and odd rows among the four rows. . In FIG. 5, even lines are shifted with respect to odd lines, and this is
And

In the 8-gradation display, if the even line shift 51 is set to any one of 1 to 4, the frame shift is set to 3 or 5, and the line shift is set to 1, 2, 5, or 6, the frame frequency becomes 80 Hz. Also, the effect that flicker did not occur was obtained. When four gradations are displayed, the even line shift may be set to 2 or 3, the frame shift may be set to 1, and the line shift may be set to any of 1 to 3. The four-gradation display takes four of the eight-gradation displays, and there are commonly used gradations.
It was found that the optimum shift amount changes depending on the number of gradations. Therefore, as shown in FIG. 22, the value of the shift amount holding RAM 201 can be changed by the display gradation number 221.
The optimum shift is performed according to the number of display gradations.

Further, it has been found that the optimum line shift and the shift amount in the set for every N rows are different depending on the frame frequency. When comparing the case of 80 Hz and the case of 120 Hz, it was found that each was different by two or three. Therefore, a configuration was considered in which the value of the shift amount holding RAM can be changed by the microcomputer 202 depending on the case where the frame frequency 222 is 70 to 110 Hz and the case where the frame frequency 222 is 120 to 160 Hz, as in the case of the gradation display number.

When performing gradation expression by FRC, gradation expression is performed based on the difference in average luminance of pixels in several frames, and when used as a liquid crystal display device, the degree of occurrence of flicker depends on the response speed of the liquid crystal. Change. In particular, when the response speed is in the range of 50 ms to 120 ms, ON frames and OFF frames are clear, and vertical streaks due to interference with other gradations are likely to appear. In particular, interference with other gradations affects all pixels on the segment line where the interference has occurred, and the image quality is more significantly reduced than flicker. Therefore,
Switch 2 outside the gradation control block of FIG.
24, and the response speed is 50 to 120 by the switch.
The microcomputer 202 rewrites the value of the shift amount holding RAM 201 so that the shift amount is different between the case of ms and the case of 130 to 300 ms. For example, in the case of line shift, the response speed is 130 to 300 ms.
Is preferably 1 or 2, and 50 to 120
This is because 3 or 4 is preferable for the liquid crystal of ms. This makes it possible to display an image with an optimum shift amount with little interference and flicker according to the response speed of the panel to be displayed.

As another method for shifting on / off in four rows, the methods shown in FIGS. 6, 7 and 16 can be considered. FIG.
In contrast to the example of FIG. 5, the shift amount holding R
Rewrite the value of AM201 to shift odd columns,
FIG. 7 shows a method for inserting an odd-numbered line shift 61, and FIG. 7 shows a 2-3 line shift 71 for shifting two or three rows.
In 6, a 3-4 line shift 1 for shifting three or four rows
61 shows an example. In FIG. 7, instead of a few rows, one,
Four columns may be shifted (1-4 line shift), and in FIG. 16, even if the first and second columns are shifted (1-2 line shift), the same effect can be obtained. A shift method effective for flicker differs depending on the values of the line shift 3 and the frame shift 4. It is necessary to combine adjacent pixels so that they have different on / off data.

In any of these methods, when the same gradation is displayed on the entire surface of the data of four rows, the shift ratio is such that the on / off ratio is 4: 0, 2/2 or 0/4. This is the method. In the case of this combination, when the orthogonal function of FIG. 15 is used, scanning is performed only with a voltage of ± V1 as a result of the MLS operation. Accordingly, FRC capable of displaying without generating a potential of ± V2 and displaying a low frame frequency is possible.
This is a gradation display method.

(Embodiment 4) Further, in order to randomly arrange in a frame, a circuit 311 for detecting the number of sets for every N rows is provided as shown in FIG. There is a method of changing the shift amount of a row to be shifted in a set for every N rows by rewriting the value of the amount holding RAM 201. For example, as shown in FIG. 8, there is a method of changing the amount of the even-numbered line shift every four rows. In the example of FIG. 8, the shift amount is 3 for odd blocks and the shift amount is 5 for even blocks, and the ON patterns shifted within N rows as compared with FIG. Although it is possible to take a completely different shift amount in each block, the number of registers for storing the shift amount increases, and the circuit scale increases. In practice, from 2 to 4 shift amount patterns are desirable from the viewpoint of the effect of reducing flicker and the circuit scale. Pattern 1 of the shift amount is excluded because it is the third embodiment of the invention shown in FIG. In FIG. 8, the even line shift has been described. However, the odd line shift, 1-2, 3-4, 1-
A similar effect can be obtained with a 4, 2-3 line shift.

(Embodiment 5) FIG. 9 shows a fifth embodiment of the present invention. Shift amount holding RAM 201 in FIG.
Is changed for each block, so that a different shift method is used for each block, and the ON / OFF pattern is randomized. In the example of FIG. 9, in the case of the four-line simultaneous selection method, an even-numbered line shift is used in an odd-numbered block, and a 2-3-line shift is used in an even-numbered block. This enables a random arrangement as compared with the patterns of FIGS. In addition, as an example, even line shift and 2-3
Although the method of combining line shifts has been described, similar effects can be obtained by combining any of the other odd numbers, 1-2, 3-4, and 1-4 line shifts. However, since the circuit scale is increased by increasing the number of combinations in the same manner as in the fourth embodiment, it is preferable to use two or three types of combinations. In this example, the case of simultaneous selection of 4 lines has been described. In general, in the case of simultaneous selection of N lines, a set of a first N rows and a set of a second N rows which is the next set after the first set. In, the same effect can be obtained by changing at least one column to be shifted.

(Embodiment 6) In the above invention, a method for reducing the flicker by randomly arranging ON and OFF in a certain frame is described. As a sixth embodiment of the present invention, a method of randomly arranging on / off patterns in the time axis direction, that is, for each frame rate control, is shown in FIG.
0 and FIG. When gradation is expressed using seven frames, changing the shift method during this period may change the effective value applied to the liquid crystal depending on the shift amount. Therefore, the shift method is changed every seven frames in which the FRC is completed. In general, when gradation is expressed in M frames, as shown in FIG. 32, a frame count circuit 321 instructs to change the column to be shifted in the form of FIG.
27 can be realized by changing the value of the shift amount storing RAM. In FIG. 10, the odd-numbered FRC shows the even-numbered rows,
In the even FRC, two and three columns are shifted. Thus, at least two rows of on / off patterns change between FRCs. In FIG. 27, the on / off patterns of all the data of the four rows change in order to change the line shift amount.
Further, a random pattern can be further generated by using the configurations of FIGS. 10 and 27 together. In the first to fifth aspects of the present invention, the on / off pattern is random when only a certain frame is viewed. However, the randomness of the on / off is limited because the pattern only shifts the entire screen in a certain direction due to the frame shift between the frames. If it is insufficient, the flow of the on / off pattern will look like a wave and the screen will appear to flow. By changing the shift amount each time the FRC is completed, the speed of the wave can be changed for each FRC. By suppressing the flow of the screen, even if the on-off patterns are not arranged randomly in the frame, the flicker can be reduced. The occurrence can be suppressed.

(Embodiment 7) As a method of suppressing the occurrence of flicker by changing the speed of a wave, the value of the frame shift may be changed for each FRC. The method of combining the frame shift values is arbitrary, but a preferable combination is that the frame shift value is set to 1 in a certain FRC (period A) as shown in FIG.
(Period B) is set to 6. In this way, the period A becomes 1 clockwise, and the period B becomes 1 counterclockwise. By alternately combining A and B, the flow direction is reversed, and the flow stops using the optical illusion. show. Generally, when the frame shift is set to M in the period A and the frame shift is set to (N−1−M) in the period B, it can be realized in the N gray scale. In this example, A and B are used alternately each time the FRC is completed.
It may be repeated for each RC. In addition, FR for each gradation
If the frame required for C is different, alternating A and B for each common multiple value is also effective for preventing interference between gray scales. For example, 8FRC and 12FRC
In the case of performing the gradation expression by combining the above, A and B are desirably a multiple of 24, and the effect is most exhibited when the number of frames in the period A matches the number of frames in the period B.

When the line shift is L in the period A, the line shift is (the number of gradations-1-L) in the period B.

In the combination with the even-numbered and odd-numbered line shifts, if the even-numbered line shift is performed in the period A, the odd-numbered line shift having the same shift amount as the period A is performed in the period B. When the combination of the frame shift M and the even line shift L in the period A has the least flicker, the combination of the frame shift (N−1−M) in the period B and the odd line shift L in the period A and the period B Was found to be at the same level. When the shift amount is changed (N is the number of gradations), the degree of flicker changes between periods A and B, so that flicker cannot be reduced, and a bad combination of the two is noticeable. Conversely, when the optimization is performed by the odd line shift in the period A, the even line shift is used in the period B. The shift amount is always set to L, and the lines to be shifted are switched between the periods A and B. 1-4 line shift and 2-3 line shift, 1-2 line shift and 3-4
The same applies to the relationship of the line shift. By using the above-described relationship of the frame shift, the line shift, the even line shift, the odd line shift, the 1-4 line shift, the 2-3 line shift, the 1-2 line shift, and the 3-4 line shift, The illusion can eliminate flicker. FIG. 12 shows 8 gradations (7 FRC), even line shift,
The relationship between the shift amounts when the odd line shift is used is shown. The FRC is completed when the pattern is shifted to the right by F from the first frame of the period A, and is shifted six times. Then, turn back, this time to the right (7-F), i.e.
Rotate to complete FRC. Since both periods A and B require seven frames, the frame shift is 0 at the time of the return from period A to B and from B to A.

(Embodiment 8) In Embodiment 7 of the present invention, when shifting from period A to B and from B to A (7 and 14 in FIG. 12), the frame shift becomes 0, that is, the wave stops, and flickering occurs. Was a factor that was difficult to disappear. Therefore, as shown in FIG. 13, the initial state is changed depending on whether the pattern is shifted rightward or leftward. After the FRC is completed from A1 to A7, in the embodiment 7, B4, B3, B2,
B1, B7 and B6. As a result, 7 and 1 in FIG.
As shown in FIG. 4, when shifting from A to B and from B to A, the frame is also shifted, so that an effect is obtained in which the waves do not stop and flicker becomes difficult to see. Period B starts at B5
Not limited to this, any of B1 to B6 may be used. (In the case of B7, it is excluded because it is the seventh embodiment of the invention.) Since only the start position is shifted, no shift in the effective value occurs.

(Embodiment 9) In Embodiment 3 of the present invention, the shift amount holding RAM 201 shown in FIG.
Since only at least one of the shift amounts of the odd-numbered rows was held, the on-off data coincided with the pixels of the two adjacent rows. For further randomization, it is sufficient that each row can have a different shift amount in a set of N rows. For this purpose, the shift amount holding RAM 201 is provided with a RAM for individually holding the shift amount for all N rows. As a result, for example, in the four-line simultaneous selection method, the shift from the first row to the fourth row can be individually set, so that an on / off pattern as shown in FIG. 23 can be realized, and flicker can be reduced.

(Embodiment 10) FIG. 29 shows a tenth embodiment of the present invention. Conventionally, the least significant bit to the most significant bit of the gradation register output 291 (M bits) are sequentially connected to the gradation selection units 292 of the segments 1 to M,
This is repeated up to the last column of the segment. In the present invention, as shown at 295, blocks of M columns connected in order from the most significant bit are inserted, and blocks of M columns connected in order from the least significant bit are arranged alternately. FIG. 33 shows an on / off pattern in the case where the first gradation among the seven gradations is displayed as line shift 1, frame shift 1, and even line shift 3. As the frame progresses, the ON pattern moves to the right in columns 1 to 7 of the same connection as in the related art, and the ON pattern advances to the left in columns 8 to 14 connected in the opposite manner. As a result, the waves flowing to the right in the conventional wiring flow to the left in the replaced part. As a result, the area of the waves flowing in the same direction is reduced, so that flicker becomes less noticeable. This allows the frame frequency to be reduced by 3 to 5 Hz.

(Embodiment 11) The shift amount F of the frame shift is expressed as follows. When the gradation expression is performed in X frames (X is a natural number), when the frame is shifted X times, all of the 1 to X columns are shifted. If this condition is not satisfied, the display will be uneven in effective value for each pixel when the same gradation is displayed on the entire screen. Therefore, F is limited to non-divisors of X. Therefore, when X is a prime number, the number of combinations of F increases, but when there are many divisors, the possible values decrease. For example, when gradation is expressed in 12 frames, F can take four ways of 1, 5, 7, and 11. However, when gradation is expressed in six frames, F can take only one of 1 or 5. Therefore, it is difficult to reduce flicker by the frame shift value.
In the case of 5 frames or less, since the number of frames is small, even if there are two possible values of F, flicker disappeared at a frame frequency of 80 Hz by performing the first to ninth aspects of the invention. In the case of seven frames or more, there are at least four possible values. Also, F = 1 or X-1
By taking an F other than the above, the lens moves to the next pixel by at least two pixels. Therefore, there is an effect that the movement of the wave is slowed down due to the illusion of the eyes and the wave becomes less noticeable. When the first to ninth embodiments of the invention are combined, flicker is similarly eliminated at a frame frequency of 80 Hz. However, in the case of 6 frames, F was only 1 or 5, and the speed of the wave could not be changed. Therefore, it was found that flicker was conspicuous despite the small number of frames. To stop flicker, about 120 Hz is required. In order to make this the same level as the others, it is necessary to disperse as if the frame shift amount F is a value other than 1 or 5. Therefore, the connection between the output of the register and the connection of the gradation selector is changed so that a frame shift amount that cannot be actually taken can be artificially created. FIG. 30 shows a method of connecting the output of the gradation register 291 and the gradation selection unit 292 according to the embodiment of the present invention. Gradation register 29 in order from the first column of the segment
The even-numbered bits from the least significant bit 294 of one output are sequentially connected. When the connection to the most significant bit is completed, the odd-numbered bits from the lower bit are successively connected. FIG. 34 shows an on / off pattern when the frame shift is set to 1 when the connection is made in this manner. In the conventional example, the entire screen is always shifted by 1 between frames, but in the embodiment of the present invention, the shift amount changes for each frame, and the shift amount is 3, 4,.
When the even line shift is used for each set of N rows in addition to 3, 4, 3, and 1, the start position of the repetition of the previous shift amount is different between the even line and the odd line in the set of N rows. Therefore, the speed of the wave differs depending on the position of the pixel for each frame, and the flicker becomes difficult to see. As a result, a flicker-free display can be performed even at a frame frequency of 80 Hz. In addition to the tenth and eleventh aspects of the present invention, generally, if the X-bit gradation register output 291 and the gradation selection unit 292 are connected on a one-to-one basis, the FRC wave speed becomes random and flicker is reduced. Further, it was found that when this method was applied to other gradations, a similar effect was obtained, and the frame frequency was reduced from 80 Hz to 75 Hz.

(Embodiment 12) Conventionally, since the frame shift has the same value in each frame, the image appears to flow at a constant speed. Therefore, the present inventors have considered making the flow difficult to see by giving different values between frames and changing the speed at which the image flows. To give different frame shift values between frames, FIG.
As shown in the figure, the gradation comparison table 281 is used. In the gradation comparison table 281, a random variable is generated, the value of which is written into the shift amount holding RAM 201 by the microcomputer 202, and the RAM 201 performs a shift process of the register of the gradation register circuit 192. The variables generated in the gradation comparison table 281 need to be a combination such that, when gradation is expressed in a Y frame (Y is a natural number of 2 or more), the shift always passes from the 1 frame to the Y frame once. There is. As a result, the on / off pattern is as shown in FIG. 35, and it is possible to prevent an image from flowing at a constant speed in a constant direction. As a result, flicker-free display can be performed at a frame frequency of 80 Hz.

(Embodiment 13) It has been found that the degree of flicker and interference between gradations differ depending on the number of colors and whether the screen is stationary or moving. As the FRC is used, the number of necessary frames increases as the number of colors increases, and in a moving image, there is a problem that the gradation changes before the FRC is completed. FIG. 37 shows a difference in frame frequency at which interference between gradations is eliminated due to a difference in flicker and an input signal data type. As the number of colors increases, the required frame frequency increases. For the same number of colors, the moving image needs to have a higher frame frequency. To prevent flicker and inter-gray level interference in all data, 160
Hz frame frequency is required. Still image 25
For six colors, the frame frequency may be only 80 Hz. Conventionally 16
Although it was driven at 0 Hz, in order to reduce power consumption,
The lowest frame frequency that always eliminates flicker and inter-gray-level interference depending on the data format may be used. Therefore, FIG.
As shown in FIG. 7, a data format detecting means 365 for determining the type of an input signal is introduced, and the oscillators 1 and 2, the switching circuit 363, and the frequency dividing circuit 364 are controlled to control the gradation control unit 367, the controller 368, and the memory 366. The clock and the frame frequency for operating the can be changed. The method of distinguishing between a moving image and a still image can be determined, for example, by referring to the moving image / still image identification information inserted at the beginning of the packet. The difference in the number of colors can be determined by detecting the bit length. This function can be implemented by providing the data format detection means 365 with this function. Under the conditions of FIG. 37, in order to eliminate flicker and interference between gradations, the frequency of the oscillator 1 is set to 160 Hz, and the frequency of the
Hz, the switching circuit 363 selects the oscillator 1 for 4096 colors of the moving image, and no frequency division for the frequency dividing circuit 364. The switching circuit 363 selects the oscillator 2 for the 4096 colors of the still image, If the frequency division is not performed, the switching circuit 363 is set to the oscillator 1 for 256 still images.
Is selected, and the frequency is divided by 2 by the frequency dividing circuit 364. Other data can be similarly implemented. Compared to the conventional method using the same frequency, for example, when only about 10% of a moving image is displayed, power consumption can be reduced by 30 to 40%.

(Embodiment 14) Embodiment 13
, The frame frequency was changed according to the data. In the third embodiment, it has been clarified that changing the frame frequency changes the optimum shift amount. Therefore, FIG.
The data format detection unit 365 is also input to the gradation control unit 367 and the shift amount holding RAM 360, and the data amount detection unit 365 rewrites the shift amount holding RAM, and the gradation control unit 367 changes the shift method. As a result, the image quality can be improved and the frame frequency can be further reduced.

(Embodiment 15) The initial data stored in the A-bit gray scale register in the gray scale register circuit 369 in FIG. The number is B and the rest are off. There are a plurality of ways of giving such register values. For example, in the case of the third gradation out of nine gradations, for example, 38
1 to 383. When the frame frequency at which flicker stops is checked by performing frame shift, line shift, even column shift, etc., respectively, 381
Is about 75 Hz in the pattern of FIG.
At 10 Hz and 383, it was about 95 Hz. Similarly 1
In the case of the fifth gradation out of the three gradations, a study was also made from 384 to 386. As a result, the frequency was about 80 Hz in the case of 384, 140 Hz in 385, and 120 Hz in 386. 381
383, the frame frequency decreases as the ON bits are successively arranged. About this, FIG.
5 shows a change of an on / off pattern of a pixel in each frame. When the frame shift is 5, in the pattern of 381, the segment signal line to which the signal of the most significant bit is input is turned on / off / off / on / off / off / on / off in order from the first frame, and 382, 383 On is evenly lined up compared to. On the other hand, if the frame shift is set to 1, the case of 382 is arranged most randomly. In order to randomize on / off in the B gradation display, it is considered that the initial value of the gradation register and the value of the frame shift have a correlation. FIG. 40 shows a change in the arrangement of ON and OFF between the current frame and the next frame when the frame shift amount is equal to or more than B and equal to or less than AB.
In addition, B indicates A / 2 or less and shows a case where the number of ONs is small, and a method in which a small number of ONs are not adjacent is considered. On is B bit continuous arrangement 404 and the rest are off 40
In case 3, since the frame shift amount F is equal to or larger than B and equal to or smaller than AB, the segment signal line 404 that is on in the current frame is always turned off in the next frame, and does not continuously occur for two or more frames. On the other hand, when ONs are dispersed and arranged, for example, if the B bits are dispersed from 409a to 409d, ONs may continuously occur as in 400. Next, when F is smaller than B or larger than AB, when ON is continuously arranged by B bits, 41
As shown in FIG. 5, there is a case where ON is always present continuously for at least two frames or more. On the other hand, in the case of the distributed arrangement, when the ON is arranged as 419a to 419d, the ON becomes 2
It can be made to overlap over the frame. Therefore, if F is greater than or equal to B and less than or equal to AB, it is only necessary to continuously arrange B bits. If F is less than B or greater than AB, if ON is distributed, ON is dispersed between frames and flicker is reduced. A small display is possible.

When B is larger than A / 2, it is only necessary to switch on and off. When F is equal to or more than (AB) and equal to or less than B, the information of the voltage expressing ON is represented by (A-
B) The initial value of the gradation register is substituted so that the information of the voltage that expresses OFF continues for B bits, and if F is larger than B or smaller than (AB), the OFF state is set. By substituting the initial value of the gradation register so that the information of the voltage to be expressed is not arranged in the adjacent bit, it is possible to disperse a small number of off-states.

(Embodiment 16) In the case where a plurality of gray scales are displayed by FRC, the image quality is degraded when the on / off state is not distributed within a frame or between frames. In 1 to 15, the value of the shift amount of the gradation register is inappropriate, and a certain pattern may flow and look like a wave. The flicker and pattern flow at each gradation can be improved by displaying the gradation on the entire screen and adjusting the shift amount. On the other hand, in this method, if a natural image or a portrait image is displayed even if the flicker of each gradation and the pattern flow are stopped, there is a problem that streaks (hereinafter referred to as vertical streaks) and flickers along the segment signal lines are generated. I understand. In a natural image, since many gradations occur every several dots, interference is caused by flicker processing among a plurality of gradations. Changing the shift processing of at least one of the tones constituting the portion where the vertical streak or flicker occurs changes the degree of the vertical streak or flicker. Even if you adjust with natural images,
Adjustment of the shift amount is difficult because it is necessary to check in which part each gray level is displayed, and it is difficult to determine whether or not the wave has disappeared due to the narrow display area of each gray level. Therefore, the pattern shown in FIG. 42 was considered for evaluation, in which the degree of occurrence of flicker and pattern flow was also known, and interference between gradations was found.
The pattern in FIG. 42 is a uniform display area 4 of a certain gradation A421.
24, and a checkered display area. The checkered display area is obtained by dividing the display area other than the uniform display area 424 into four in the common direction and four in the segment direction. The divided checkered display area is a uniform display area 424. Same tone A421 and 16
Forming a checkerboard of two rows and one column with one grayscale B of the grayscales,
The gradation B is divided into four in the row direction and four in the column direction.
Are given different gradations in all the regions. The flicker and pattern flow of a certain gradation A can be confirmed in the uniform display area 424, and all gradations can be confirmed by changing A to all 16 gradations. In the inter-gray level interference, for example, if the gray level A and the gray level 9 interfere, the gray level A
It can be confirmed that interference has occurred due to the presence of vertical streaks in the area 424b on the same segment line where the gradation 9 is displayed in the uniform display area. Generally, the area 42
When a vertical streak is present in 4a, there is interference between the gray level A and the gray levels 0, 7, 8 or 15, and when a vertical streak is present in the region 424b, the gray level A and the gray levels 1, 6, 9 or In the case where there is an interference with the image 14 and a vertical streak enters the region 424c, there is an interference between the gradation A and the gradation 2, 5, 10, or 13, and the region 424c
When a vertical streak appears in d, it can be seen that there is interference between the gradation A and the gradations 3, 4, 11, or 12. This allows
The adjustment can be performed while observing the flicker, the pattern flow, and the inter-gray-level interference in one pattern. The uniform display area is at least ４ and 以下 of the total number of common signal lines of the display device, and each of the divided checkered display areas is at least N rows or more, preferably 3 × N rows or more. The difference between the columns of each block divided into four equal to or less than four in the column direction is preferably less than or equal to 10 in the column direction.

In the case of the four simultaneous selection method (MLS4), the segment signal lines have five types of voltage values.
In the case of the display pattern of 2, only two out of the five values are output, and in the case where the remaining three values of the voltage are output, it is not confirmed particularly the interference between gradations. In order to apply the remaining three values to the segment signal lines, the on / off ratio of simultaneously selected four rows of data needs to be 1: 3 or 3: 1. In order to satisfy this, as shown in FIG. 43, one row and gradation A are inserted in the checkered display area. Grade A
May be any one of the checkered areas.

A method of adjusting the display to a display free from flicker, pattern flow, and interference between gradations will be described with reference to the images shown in FIGS.

In the uniform display area of the gradation A, the frame shift, the line shift, and the even-numbered row shift of the gradation A and the shift amount described in the first to fourteenth aspects are switched to provide the uniform display area of the gradation A. Eliminating the generated flicker and pattern flow, and eliminating the pattern flow occurring in the checkered area. This is performed for all gradations. In the case of 16-gradation display, A is changed from 0 to 15 to eliminate flicker and pattern flow at each gradation. In this way, if the flicker is eliminated, the uniform display areas 424a to 424d of the gradation A may be used in some cases.
In one or a plurality of regions, vertical streaks occur due to inter-grayscale interference along the segment signal lines. In this case, the shift amount of the gradation A is changed, or if the vertical streak still does not disappear, the shift amounts of the three gradations forming the checkered display area having the same segment signal line where the vertical streak is generated are changed. Let it. Thereby, the vertical streaks due to the interference are reduced. If the vertical streak is conspicuous even in this manner, the shift amount of the gradation A is further changed, and a value is set so that the vertical streak becomes invisible. In this case, the pattern flow can be seen, but when a natural image is taken, it is less noticeable than the vertical stripes. Therefore, it is better to prioritize elimination of the vertical stripes. With this method, in a 4096-color portrait, display without flicker, pattern flow, and interference between gradations is performed at a frame frequency of 7
It is now possible to run at 5 Hz.

The present invention can also be implemented by a combination of the first to sixteenth embodiments.

The case of simultaneous selection of four lines has been described. However, in general, when display is performed by simultaneous selection of N lines, image data of N rows is simultaneously transferred. Therefore, the pattern is changed every N rows. The same effect can be obtained. FIG. 18 shows an on / off pattern when eight rows are simultaneously selected. In the third to eighth embodiments, even line shift, odd line shift, 1-2, 3-4, 1-
In the case of N-line simultaneous selection, the line shift of 4, 2-3 is performed by selecting N / N among data of N lines transferred at the same time.
This is a shift that shifts two lines. There are a plurality of combinations of N / 2 lines. For example, if all the even lines are moved, an even line shift is performed. In the case of simultaneous selection of four lines, there are six ways of shifting, and names are all given. However, in the case of simultaneous selection of N lines, since there are many combinations, these are collectively referred to as N / 2 line shift. Since there is no change in the method, a flicker reduction effect can be generally obtained in the case of simultaneously selecting N lines.

In the above description, the display method of the first gradation in the case of the eight gradation display has been described. However, even in the case of the second to seventh gradations, the gradation number is not limited to the eight gradations. The same effect can be obtained by changing the shift amount from about 3 to 18 gradations, preferably from 3 to 16 gradations. FIG.
FIG. 9 shows a shifted on-off pattern for the case of the fifth gradation in the 13-gradation display as an example other than the 8-gradation display. FIG. 14 shows the optimum shift amounts for some gradations in the case of simultaneous selection of four lines.

FIG. 25 shows the case where the frame frequency at which the occurrence of flicker is reduced to 8 or 16 gradations according to the embodiment of the present invention.

FIG. 24 shows a case where a demodulator, an antenna 243, and a button 242 are attached to a display device 244 using at least one of the first to twelfth embodiments.
41 is a portable information terminal.

FIG. 19 shows a liquid crystal television comprising the display device 11 of the present invention and the video signal processing circuit 14 and the switching means 12 for changing the gradation shift data according to the power supply frequency. Two tone shift data for 50 Hz and 60 Hz are prepared and changed by the switching means 12 to prevent flicker due to interference with external light.

[0043]

As described above, according to the present invention, in the case where gradation is expressed by FRC in the N-row simultaneous selection method, the gradation is expressed for each set of N rows, for each frame, and for a plurality of rows of the set of N rows. By shifting the register, preparing at least two patterns of the shift amount, randomly changing the shift amount for each frame, and randomly changing the shift amount for each frame, gradation display with less flicker is possible. A display device can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a gradation display unit of a display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an on / off pattern of pixels of the entire panel when displaying the first gray scale during eight gray scale display according to the first embodiment of the present invention;

FIG. 3 is a diagram showing an on / off pattern of a pixel when displaying the first gray scale during eight gray scale display according to the first embodiment of the present invention;

FIG. 4 is a diagram showing an on / off pattern of a pixel according to a second embodiment of the present invention;

FIG. 5 is a diagram showing an on / off pattern of a pixel when an even-numbered line is shifted according to the third embodiment of the present invention;

FIG. 6 is a diagram showing an on / off pattern of a pixel when an odd-numbered line is shifted in the third embodiment of the present invention.

FIG. 7 is a diagram showing an on / off pattern of a pixel when a second and fourth lines are shifted in the third embodiment of the present invention.

FIG. 8 is a diagram showing an on / off pattern according to a fourth embodiment of the present invention;

FIG. 9 is a fifth embodiment of the present invention, and is a diagram showing an on / off pattern when a row to be shifted is changed for each block in each of N rows of blocks.

FIG. 10 is a sixth embodiment of the present invention, and is a diagram showing an on / off pattern when a row to be shifted every time FRC is completed is changed for each block;

FIG. 11 is a seventh embodiment of the present invention, in which the frame shift and the line shift are changed in the reverse direction each time the FRC is completed;
The figure which showed the on / off pattern when the column to be shifted was exchanged in the block of N rows

FIG. 12 is a seventh embodiment of the present invention, in which the frame shift and the line shift are changed in the opposite direction every time the FRC is completed;
The figure which showed the shift amount between each frame when the column to be shifted is exchanged in the block of N rows.

FIG. 13 is a diagram showing how to give a shift amount between frames according to the eighth embodiment of the present invention.

FIG. 14 is a diagram showing an optimal shift amount for reducing flicker in the embodiment of the present invention.

FIG. 15 is a diagram showing an orthogonal function when four lines are simultaneously selected in the present invention.

FIG. 16 is a diagram showing an on / off pattern of a pixel when the third and fourth lines are shifted in the third embodiment of the present invention.

FIG. 17 is a diagram showing an on / off pattern in FRC gray scale display according to a conventional embodiment.

FIG. 18 is a diagram showing an on-off pattern in the case of an 8-line selection driving method.

FIG. 19 is a diagram of a liquid crystal television incorporating the display device of the present invention.

FIG. 20 is a diagram showing a gradation display unit of a display device according to the second to ninth embodiments of the present invention.

FIG. 21 is a diagram showing an input signal operation circuit for obtaining a segment signal output in the multiple line selection method.

FIG. 22 is a diagram in which the value of the RAM is changed according to the difference in the number of display gradations, the frame frequency, and the response speed of the panel from the block diagram of FIG. 20 in the third embodiment of the present invention.

FIG. 23 is a diagram showing an on / off pattern when each row has a different shift amount in a set of four rows in the ninth embodiment of the present invention;

FIG. 24 is a diagram of a portable information terminal incorporating the display device of the present invention.

FIG. 25 is a diagram showing a frame frequency at which flicker subsides in the embodiment of the present invention.

FIG. 26 shows 5 out of 13 gray levels in the first embodiment of the present invention.
The figure which showed embodiment at the gradation level

FIG. 27 is a diagram showing an embodiment in the first gradation out of eight gradations in the sixth embodiment of the present invention.

FIG. 28 is a diagram showing that a frame shift value can be randomly set in the twelfth embodiment of the present invention;

FIG. 29 is a diagram showing an embodiment at the fifth gradation out of 13 gradations in the tenth embodiment of the present invention.

FIG. 30 is a diagram showing a wiring method with a gradation selection unit in the case of a 6-bit gradation register in the eleventh embodiment of the present invention.

FIG. 31 is a diagram illustrating a configuration in which the number of sets of N rows is counted and the shift amount can be changed for each set of N rows in the fourth embodiment of the present invention.

FIG. 32 shows a frame number,
Circuit configuration diagram in which the number of sets in N rows is counted and the shift amount is changed according to the counter value

FIG. 33 is a diagram showing an on / off pattern when the circuit configuration of FIG. 29 is used in the tenth embodiment of the present invention;

FIG. 34 is a diagram showing an on / off pattern together with a conventional example when the circuit configuration shown in FIG. 30 is used in the eleventh embodiment of the present invention.

FIG. 35 is a diagram showing an on / off pattern when the circuit configuration shown in FIG. 28 is used in the twelfth embodiment of the present invention;

FIG. 36 is a view showing a configuration in which a frame frequency and a value of a shift amount holding RAM are changed according to a format of input data in a thirteenth embodiment of the present invention.

FIG. 37 is a diagram showing a minimum flickerless frequency depending on a difference in input data type;

FIG. 38 is a diagram showing an example of an initial value of a gradation register in the case of the third gradation out of nine gradations and the fifth gradation out of thirteen gradations.

FIG. 39 is a diagram showing a frame shift, a gray scale register initial value, and on / off variations in a third gray scale out of nine gray scales;

FIG. 40 is a view for explaining an optimal arrangement of gradation register initial values when the frame shift value is equal to or more than the number of ON and equal to or less than the number of OFF;

FIG. 41 is a view for explaining an optimal arrangement of gradation register initial values when the frame shift value is smaller than the number of ON and larger than the number of OFF;

FIG. 42 is a diagram showing a pattern for evaluating flicker, pattern flow, and occurrence of inter-gray level interference;

FIG. 43 is a diagram showing a pattern for outputting and evaluating all voltage values in a four-row simultaneous selection method for flicker, pattern flow, and occurrence of inter-grayscale interference.

[Explanation of symbols]

 360 RAM for holding shift amount 361 Oscillator 1 362 Oscillator 2 363 Switching circuit 364 Dividing circuit 365 Data format detecting means 366 Memory 367 Gradation control unit 368 Controller 369 Gradation register circuit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 631 G09G 3/20 631H 641 641E (72) Inventor Atsuhiro Yamano 1006 Odakazuma, Kadoma, Osaka Prefecture Matsushita Electric Industrial F term (for reference) 2H093 NA51 NC22 ND06 ND10 5C006 AA14 AA22 AF13 AF44 AF51 AF53 AF61 BB11 BC03 BC12 BC16 BF02 BF14 BF23 BF24 BF49 FA23 FA47 FA56 5C080 AA10 BB05 CC03 DD06 DD22 EE29 JJ02 JJ05 KK05

Claims (7)

[Claims] 1. A matrix type display device which simultaneously selects N rows of common signal lines and performs gradation display by frame rate control, comprising: a gradation register circuit; a plurality of oscillators; and outputs of the plurality of oscillators. A switching circuit for selecting one of the following; a frequency dividing circuit for lowering the frequency of the oscillator; a data format detecting unit for detecting information of input display data; and a storage unit for storing the input display data. A gradation control unit that shifts a gradation register of the gradation register circuit; a storage unit; a controller that controls the gradation control unit; and an even row and an odd row in a set of N rows. A RAM for holding at least one shift amount, a RAM for shifting every N rows, and a gradation selection circuit provided for each segment; The register output is sequentially connected to the gradation selection circuit, the data format detection unit detects the number of colors of the input data and the moving image / still image, controls the switching circuit and the frequency dividing circuit based on the detection result, and A matrix display device characterized by switching rates. 2. A matrix display device for simultaneously selecting N rows of common signal lines and performing gradation display by frame rate control, comprising: a gradation register circuit; a plurality of oscillators; and outputs of the plurality of oscillators. A switching circuit for selecting one of the following; a frequency dividing circuit for lowering the frequency of the oscillator; a data format detecting unit for detecting information of input display data; and a storage unit for storing the input display data. A gradation control unit that shifts a gradation register of the gradation register circuit; a storage unit; a controller that controls the gradation control unit; and an even row and an odd row in a set of N rows. A RAM for holding at least one shift amount, a RAM for shifting every N rows, and a gradation selection circuit provided for each segment; The register output is sequentially connected to the gradation selection circuit, and the data format detection means detects the number of colors of the input data and the moving image / still image, and according to the detection result, the switching circuit, the frequency dividing circuit, and the gradation control. Control the circuit,
A matrix display device, wherein the RAM is rewritten and a frame rate and a shift amount of the gradation register are switched. 3. A matrix type display device which simultaneously selects N rows of common signal lines and performs gradation display by frame rate control, comprising: a gradation register circuit having an A-bit gradation register; A gray-scale control unit that shifts a gray-scale register of the register circuit by a horizontal synchronization signal or a vertical synchronization signal; a RAM that holds at least one of an even-numbered row and an odd-numbered row in a set of N rows; A RAM that shifts for each set of rows, and a gradation selection circuit provided for each segment, wherein the gradation register output is sequentially connected to the gradation selection circuit; Using the output of the gradation register, perform gradation processing of N rows, the gradation register shifts F bits for each frame, and the data of the gradation register expresses gradation B When B is a natural number and less than A / 2, when F is equal to or more than B and equal to or less than (A−B), information of a voltage for expressing ON is continuous for B bits, and information of a voltage for expressing OFF is continuous. (AB) The initial value of the gradation register is substituted so that bits are generated continuously. When F is smaller than B or larger than (AB), information of voltage expressing ON is arranged in an adjacent bit. When B is equal to or more than A / 2 and equal to or less than A, when F is equal to or more than (AB) and equal to or less than B, the information of the voltage expressing ON is represented by (A- B) The initial value of the gradation register is substituted so that the information of the voltage expressing OFF is generated continuously for B bits, and when F is larger than B or smaller than (AB),
A matrix display device, wherein an initial value of the gradation register is substituted so that information of a voltage expressing OFF is not arranged in an adjacent bit. 4. A uniform display area of a certain gradation A and a checkered display area, wherein the checkered display area divides a display area other than the uniform display area into four in a common direction and four in a segment direction, The divided checkerboard display area forms the same grayscale A as the uniform display area and one grayscale B out of 16 grayscales and a checkerboard of two rows and one column, and the grayscale B is arranged in the row direction. A method for adjusting a matrix-type display device, characterized in that different gray scales are provided in 16 regions divided into four and four in the column direction. 5. The uniform display area is at least ４ and at most １ of the total number of common signal lines of the display device, and the divided checkered display area is at least N rows or more, preferably 3 ×. 5. The method according to claim 4, wherein the number is not less than N rows and not more than 3/16. 6. An arbitrary one of the divided checkered display areas.
5. The adjustment method for a matrix type display device according to claim 4, wherein the same gray level as that of the uniform display area is displayed in a row. 7. A matrix type display device, comprising: a uniform display area of a certain gradation A; and a checkered display area, wherein the checkered display area has four display areas other than the uniform display area in a common direction, and a segment. The divided checkerboard display area is divided into four in the direction, and the divided checkerboard display area forms the same grayscale A as the uniform display area and one grayscale B out of 16 grayscales and a two-row, one-column checkerboard, By switching the shift amount of the gray scale A and the shift amount of the gray scale displayed in the checkered display area, the flicker generated in the uniform display area of the gray scale A and the gray scale difference generated along the columns are provided. And a flicker in the checkered display area is eliminated.