JP2002268471A - Asic with built-in programmable sequencer and picture forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to control a power source without interjacent software. SOLUTION: An ASIC 1 receives a plurality of external input signals, a plurality of trigger signals generated internally, and an input from a register controllable by software, having a plurality of basic structure blocks 2a, 2b, 2c operating according to the contents set to the register by the software, and controlling a sequence for shifting/returning a copying machine to/from a power- saving mode by performing the specified operation without being controlled by the software.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ASIC with a built-in programmable sequencer for controlling power in a power saving mode in a copying machine, a printer, a multifunction peripheral thereof, and the like, and an image forming apparatus.

[0002]

2. Description of the Related Art In recent years, copiers, printers, and their multifunction peripherals have been increasingly demanded to reduce power consumption as environmental issues have become more noticeable. Is performing a wide variety of power management. When performing this power supply management, the type of power supply and the management method change according to the configuration of the device. Therefore, it is common to perform on / off control of the power supply by software. That is, it is easy to change / correct the software according to the specifications of the device. When control by software is not possible in this way, for example, power control at a level at which power to the CPU itself is turned off can be performed by software, but power must be restored by hardware. In addition, the programmable sequencer generally executes software, and is limited to a specific operation without a CPU.

[0003]

In the advanced power saving mode, the CPU is also required to turn off the power, so that the power must be restored by hardware. However, since the number of power supplies to be controlled and the control method differ depending on the configuration of the device, it is necessary to design each time in accordance with the device. In addition, in this method, when there is a defect in the design or the control method is corrected, it is necessary to start over from the hardware design.

The present invention is directed to an ASIC with a built-in programmable sequencer and an image forming apparatus using the same, in which a power supply can be controlled without intervention of software by improving a disadvantage of the invention and configuring a programmable control circuit inside. The purpose is to provide.

[0005]

An ASIC with a programmable sequencer according to the present invention has a plurality of external input signals, a plurality of internally generated trigger signals, and an input from a register which can be controlled by software. , A circuit that operates according to the contents set in the register, and has a function of executing and outputting a predetermined operation without requiring control by software.

It is preferable to have a function of setting a specific operation by input setting other than the register setting.

It is also desirable that a specific packet in communication such as LAN can be detected as a trigger signal.

[0008] An image forming apparatus according to the present invention is characterized by using the ASIC with a built-in programmable sequencer.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A copying machine according to the present invention has an ASIC for controlling a power supply. The ASIC has a plurality of basic structure blocks having a plurality of external input signals, a plurality of internally generated trigger signals, and an input from a register which can be controlled by software, and operating according to the contents set in the register by software. And executes a predetermined operation without the need for software control to control the transition of the copier to the power saving mode and the return sequence from the power saving mode.

[0010]

FIG. 1 is a block diagram showing a configuration of an ASIC with a built-in programmable sequencer according to an embodiment of the present invention. The ASIC 1 controls a power supply of an image forming apparatus such as a copying machine, and controls a transition to a power saving mode and a return sequence from the power saving mode, and has three basic structural blocks 2a, 2b, and 2c.

Each basic structure block 2 has a block A, a block B, a block C and a block D as shown in the block diagram of FIG. Block A of the basic structure block 2 is an input selection block, which selects an external signal or an internal signal of the ASIC and a set value by a register, and selects inversion / non-inversion of logic. This input selection block A is 4
Place one. The number of input selection blocks A may be four or more or less depending on the number of external signals and internal signals. The signal that can be selected in the input selection block A may be arbitrarily changed by the designer according to the situation. In FIG. 1, three external signal inputs EXT-IN are assumed, and the internal signal is assumed to be the output OUT of the sequencer block and the register output reg. The input signal of the input selection block A is selected by register setting. At the same time, it sets whether or not the selected signal is logically inverted. As a result, a signal is input from the input selection block A to the block B. Block B is an operation block, and selects the logical product or logical sum of the signals from the input selection blocks A1 to A4. That is, four input selection blocks A1 to A4
Select the logical OR or logical AND of the signals from. Block C is a timer block, which has a function of detecting the rise or fall of a signal from the operation block B, adding a delay by a delay timer, and generating / latching an output signal. When the rise / fall of the signal from the operation block B is detected, the delay timer starts operating. When the counting is completed, a signal is output to the block D. Rising / falling is selected by register setting. Also reset (initialize) the delay timer
Can select one of an ASIC external signal, an ASIC internal signal, and a register output. The output is positive logic only. Block D is an output selection block for selecting the positive logic / negative logic of the output signal, and inverts / inverts the output from block C according to the contents set in the register and outputs the inverted signal from the output terminal to the outside of the block. .

The setting / selection of each of the blocks A to D is performed by register setting from software. Therefore, A
As long as the power of the SIC1 is not turned off or the ASIC1 itself is not reset, the function as the sequencer is not lost. The number of the basic structure blocks 2 in the ASIC 1 may be increased when performing complicated control.

FIG. 3 shows an example of the register configuration of the basic structure block 2. Registers 3 to 3 of input selection block A
6 is an external pin EXT- predetermined by the ASIC1.
Input from IN1 to EXT-IN3 and output signal OUT of ASIC1
One of 1 to OUT3 and a fixed value by software can be selected, and inversion / non-inversion of the value can be set. These registers 3 to 6 are formed of 8 bits for each input selection block A, and four registers exist in the basic structure block 1. ASI
To use other signals inside C1, use registers 3-6
The corresponding signal is added to As the register 7 of the operation block B, a 1-bit register is used for selecting whether to take a logical sum or a logical product of the signals from the input selection block A. The register 8 of the timer block C uses a register for setting a timer count value and a register for setting whether to select a trigger signal for resetting the counter and start counting at the rising edge or falling edge of the input signal. The counter is set to 16 to 32 bits depending on the base clock of the count and the required maximum count time. The selection of the trigger signal and the selection of the trigger are controlled by an 8-bit register. As the register 9 of the output selection block D, a 1-bit register is used for logical selection of an output signal. In the ASIC 1, these registers are prepared according to the number of the basic structure blocks 2 to be mounted. The initial value to be loaded into the register can be changed by setting the input to the external pin of the ASIC 1. This means that the ASIC 1 checks the input settings during reset and changes the register initial value.

In FIG. 1, Vdd1 is a primary power supply linked to a power switch, and Vdd2 and Vdd3 are secondary power supplies controlled by software / ASIC1. A
Power is supplied to the SIC1 from the primary power supply Vdd1 by turning on the power switch. At this time, the secondary power supply Vdd2 is turned on after a lapse of a predetermined time since the primary power supply Vdd1 is turned on, and the secondary power supply Vdd3 is turned on.
It turns on after a lapse of a certain time since dd2 turns on. By connecting the CPU / memory and the like to the secondary power supply Vdd2, the power supply can be turned off while leaving the ASIC 1 and a very small number of peripheral circuits, and the energy saving effect can be enhanced.

In the basic configuration block 2a, a logical sum of an external input and a register of the input selection block A may be used as a trigger, and the trigger may be activated by the initial value of the register. Then, after the delay timer finishes counting, OU
The power supply to the secondary power supply Vdd2 is started at the output of T1. As for the secondary power supply Vdd3, the output of OUT1 may be input, or the level of the secondary power supply Vdd2 may be directly input. If one delay counter is not enough,
As shown in FIG. 1, two basic structural blocks 2b and 2c may be used in series. When the primary power supply Vdd1 is supplied and the secondary power supplies Vdd2 and Vdd3 are off, the secondary power supplies Vdd2 and Vdd3 are triggered by a specific operation, for example, pressing a switch of an operation panel or opening a cover of a device. Can be turned on.

Further, since the delay counter also has the function of a latch by detecting an edge, if it is desired to turn off a specific power supply, for example, to turn off only the two-time power supply Vdd3, the software uses the basic configuration blocks 2b and 2c.
What is necessary is just to reset the delay timer. When it is desired to turn on again, the register setting of the input selection block A of the basic constituent blocks 2a and 2c is set as a trigger.

Furthermore, if the basic configuration block 2 is arranged in the ASIC 1 in anticipation of an increase or decrease in the number of power supplies to be controlled,
There is no need to change the design of the ASIC 1 every time the configuration of the device changes. Further, by making it possible to select the initial value of the basic configuration block 2 by an external signal, it is possible to cope with a change in a parameter or a device configuration when the primary power supply Vdd1 is turned on.

FIG. 4 shows a case where a signal from another module in the ASIC 1 is used as a trigger. By outputting the reception of a signal or a packet as a trigger signal at the communication interface 10 such as a network, the power can be turned on. In addition, by arranging something like an extended external input block, the input to the basic configuration block 2 can be apparently increased.

By arranging the basic configuration block 2 inside the ASIC 1, a programmable control circuit can be easily configured, and power saving of the device can be facilitated. Further, since the ASIC 1 is hardly affected even if there is a change in the design of the device because it is programmable, the ASIC 1 can be diverted to many types, and the development cost and period can be reduced.

[0020]

As described above, the present invention can cope with different power supply sequences by setting initial input to software or ASIC without redesigning hardware such as ASIC according to the system. Thus, it is possible to reduce the development cost and period and promote the power saving.

Further, all the power supplies except the ASIC can be cut off, and the power saving effect can be further improved. Furthermore, since it is programmable, even if there is a change in the device configuration or control method, the control circuit can be changed by changing the software, and the frequency of recreating hardware can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a basic structure block of the embodiment.

FIG. 3 is a configuration diagram of a register.

FIG. 4 is a block diagram showing a configuration of another embodiment.

[Explanation of symbols]

1; ASIC, 2; basic structural block, 3 to 9;

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Claims (4)

[Claims] 1. A circuit having a plurality of external input signals, a plurality of internally generated trigger signals, and an input from a register controllable by software, and operating according to the contents set in the register by software. ,
An ASIC with a built-in programmable sequencer having a function capable of executing and outputting a predetermined operation without requiring control by software. 2. The ASIC with a built-in programmable sequencer according to claim 1, which has a function of setting a specific operation by input setting other than the register setting. 3. The ASIC with a built-in programmable sequencer according to claim 1, wherein a specific packet in communication can be detected as the trigger signal. 4. An image forming apparatus which controls a transition to a power saving mode and a return sequence from the power saving mode by an ASIC with a built-in programmable sequencer according to claim 1, 2, or 3.