JP2002267723A - Scan flipflop circuit device, and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To exactly evade a hold-error in a scan path route. SOLUTION: This device is provided with the first scan flipflop circuit 21 and the second scan flipflop circuit 22, and the first and second scan flipflop circuit 21, 22 are operated alternately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system LSI.
The present invention relates to a scan flip-flop circuit device mounted on a computer.

[0002]

2. Description of the Related Art With the phenomenal development of semiconductor technology, the amount of logic circuits that can be mounted on a single semiconductor integrated circuit device is steadily increasing. Nowadays, a semiconductor integrated circuit device in which one million or more logic circuits are mounted is common. Therefore, it is impossible to design a logic circuit by one person. Such a semiconductor integrated circuit device is called a system LSI or the like. Therefore, the design of the system LSI is based on EDA (Engineering Design).
It is premised that the design is automatically performed on a computer using an Automation tool. If the function / architecture of the system is designed using a high-level function description language or the like, a logic synthesis tool automatically generates a logic circuit, and the logic circuit converts the logic circuit into physical layout data. By utilizing this physical data, a system LSI can be completed in a mass production flow at a factory or the like.

[0003] The scale of the logic circuit becomes large, and the system L
Problems that have emerged from automatically designing SI include the following (1) to (3). (1) Test circuit design (2) Clock design (3) Power consumption The test circuit is a circuit that determines whether or not a completed system LSI has been accurately manufactured.
Since the logic circuit inside is automatically designed, it becomes more difficult for a human to manually design a circuit for testing the logic circuit. For this reason, it has become natural to automatically design test circuits.

FIG. 12 illustrates a test method called a scan test technique. In FIG. 12, 1A, 1B,
1C, 1D, and 1E are scan flip-flop circuits (hereinafter, referred to as SFFs), and 2A and 2B are logic circuit blocks. FIG. 13 shows a configuration example of the SFF. The SFF includes a normal flip-flop circuit (hereinafter, referred to as FF) and a logic circuit. The FF is a circuit that stores data at the D terminal when the clock signal at the CLK terminal changes from “0” to “1” and outputs the data to the Q terminal. There is also an FF that stores data at the D terminal when the clock signal at the CLK terminal changes from “1” to “0” and outputs the data to the Q terminal. For simplicity, the former FF will be described here. . When the SM signal is “0”, the SFF outputs the normal F
Similar to F, this circuit stores data at the D terminal in the FF and outputs it to the Q terminal, and when the SM signal is "1", stores data at the SI terminal and outputs the data to the Q terminal.

FIG. 17 is a diagram showing a circuit configuration of the FF.
FIG. 8 is a timing chart showing the operation of the FF. An FF can be configured by connecting two latch circuits (hereinafter, referred to as latches). FIG. 17 shows a block diagram using a latch and a circuit diagram of the FF. The latch outputs the input I when the clock input T is "1".
, And operates to hold the signal of the output O when the clock input T is “0”. The FF propagates data only at the transition point of the clock signal, whereas the latch propagates data during an arbitrary phase of the clock signal (a period of “1” or “0”). Some latches propagate the input I to the output O when the clock input T is "0". However, here, for simplicity, description will be made using only a circuit that propagates the input I to the output O when the clock input T is "1".

The operation of the FF will be described with reference to FIGS. 17 and 18. The latch circuit [1] propagates the value of the D terminal to the M terminal while the CLK signal is "0", and holds the value of the M terminal while the CLK signal is "1". The latch circuit [2]
While the LK signal is "1", the value of the M terminal is propagated to the Q terminal, and while the CLK signal is "0", the value of the Q terminal is held. Therefore, regardless of whether the CLK signal is “1” or “0”, even if the signal at the D terminal operates, it does not directly propagate to the Q terminal. The output Q of the FF is the signal of the D terminal (input I of the latch circuit [1]) that has propagated to M (the output O of the latch circuit [1]) during the period when the CLK signal is "0", and the CLK signal is " When it changes to 1 ", it changes only when outputting to the Q terminal. This is because the value of the M terminal does not change when the CLK signal is "1", and the output of the latch [2] holds the signal when the CLK signal is "0". Therefore, the FF can perform an operation of storing data of the D terminal when the signal of the CLK terminal changes from “0” to “1” and outputting the data to the Q terminal. That is, the change of the output data can be defined only by the change point of the clock.

Referring to FIG. 12, an operation when a test of the logic circuit block 2B is desired will be described. External terminal SM
The signal is set to "1" and data is transmitted from the SI terminal to SFF-1.
B, set to SFF-1B. "1" at the CLK terminal,
By inputting a periodic waveform of "0", data at the SI terminal can be transferred and set in the order of 1A, 1B, and 1C. FIG. 14A shows the process. FIG. 14A shows the SFF
An example in which {1, 0} is set to -1B and 1C is shown. SF
After setting data in F, set the SM terminal to “0”,
When the CLK signal is changed to “1”, SFF-1B, 1
The output result of the logic circuit block 2B corresponding to the data of C is stored in the SFF-1D, 1E. And again S
By setting the M terminal to “1” and inputting a periodic signal to the CLK terminal, the data of the SFF-1D and 1E is read to the SO terminal. An example of the operation is shown in FIG. An example is shown in which the output result of the logic circuit block 2B is {0, 1}. In FIG. 12, a circuit in which the SFF portion is replaced with an FF is a circuit that satisfies a normal function as a system LSI, and is a circuit in which a function-designed circuit is generated by a logic synthesis tool. Therefore, replacing the FFs with the SFFs and connecting the SFFs sequentially (called scan path connection or the like) is referred to as automatic generation of a test circuit.

[0008] As can be seen from FIG.
In, logic circuits capable of realizing functions are arranged between storable logic circuits such as FFs, and the number of such blocks is huge. Therefore, one system L
Since a large number of FFs exist in the SI, it is very important to supply the same clock signal to each FF, that is, the same signal that changes to "1" or "0" at the same time. The difference in time when the clock signal changes between any two FFs is particularly called clock skew. Reducing the clock skew is an important issue in designing a system LSI.

When clock skew exists, FIG.
A malfunction as shown in FIG. Assume a circuit that adds the data of the FF groups A and B by combinational logic and stores the result in the FF group C. FIG. 15 is a timing chart in this case. FIG. 15 shows an example in which a signal without clock skew is supplied to the FF groups A, B, and C.
(A). The value obtained by adding the data of A and B is stored in C at the next changing point of the clock signal (in this example, the point changing from “0” to “1”). However, FIG. 15B illustrates a case where the clock signal supplied to the FF group B has a clock skew with another clock signal. In this case, before the addition result is stored in the FF group C, the FF group B
Data changes, the wrong output of the logic circuit is FF
It is stored in group C. In such a case, it is said that a hold error of the FF group B exists. When a hold error occurs in the system LSI, the system LSI does not operate properly no matter how slow the cycle of the clock signal is shifted.

FIG. 15B shows an example in which the worst case is assumed.
Considering the actual operation, there is a delay in the logic circuit.
It may be stored in group C. That is, if there are many logic circuits between the FFs, the influence of the clock skew is reduced by the delay, and the hold error is eliminated. But,
There are cases where there is no logic in the logic circuit and only data transfer to the FF, in which case there is no delay in the logic circuit, so if clock skew occurs, a hold error may occur. large. Considering this in FIG. 12, the effects of clock skew on the D terminals of SFF: 1B, 1C to 1D, 1E are small due to the presence of a logic circuit, but 1B to 1C where data transfer occurs at the time of test.
When data is transferred to the SI terminal, there is no logic circuit, so the influence of clock skew increases.

In a case where a clock signal is supplied to many FFs in the case of automatic design, a clock tree method is often used. FIG. 16 illustrates a clock signal supply method of the clock tree method. However, since a single logic circuit cannot supply signals to many FFs, a plurality of logic circuits (hereinafter referred to as driver circuits) are required. A clock signal is supplied, and the driver circuit 3 is configured on a tree,
This is a method in which the load on each driver circuit 3 is reduced, and eventually a clock signal is transmitted simultaneously from the signal source to each FF. In this case, it is important that the load (capacitance value and resistance value connected to the output of the circuit) of each driver circuit 3 be the same in each stage, and it is further automatically generated / placed and wired in a large-scale circuit. It becomes impossible for the same circuit to be adjusted by human ability.

In a recent system LSI design, the above-described clock tree circuit is executed by an automatic layout generation tool, that is, a tool for automatically arranging and wiring a logic circuit. The placement and routing tool roughly knows where each SFF is located,
This is because since the driver knows roughly what kind of load exists in the driver circuit in the middle of the process, the value can be adjusted to reduce the value of the clock skew. However, it is impossible to completely reduce the clock skew to “0”, and there is an error because the adjustment is based on an approximate value.

The automatic placement and routing tool executes the placement and routing so that the clock skew value is equal to or less than the set value. However, if the value to be set is small, there is no solution that satisfies the clock skew value, and the placement and routing is not completed, so a strict value cannot be set. Set value is SF
Although a smaller value is set above the value expected to be necessary for data transfer from F to SFF, when the placement and routing is completed,
For example, the transfer between the SFFs may be smaller than expected due to the arrangement of the SFFs being too close. Further, if the clock skew values of the two SFFs are slightly increased due to the arrangement, a hold error occurs between the two SFFs.

In the current system LSI, more than 100,000 SFFs are used.
It is impossible to eliminate the hold error between F. Therefore, if a hold error exists after the final layout is generated, it is necessary to correct the error location. To correct the error location, a new buffer circuit is inserted or the wiring route is changed. For this reason, since the error portion is corrected, a hold error may occur between the other SFFs that did not have the hold error, and the correction is usually not easily performed. As described above, since a logic circuit does not exist in the scan path connection path between the SFFs, the hold error often occurs frequently. As described above, the conventional SFF circuit has a problem that when a test circuit is synthesized by automatic design and a clock tree is automatically generated, a hold error due to clock skew frequently occurs. SUMMARY OF THE INVENTION It is an object of the present invention to avoid an SFF hold error that cannot be avoided by automatic design as described above.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan flip-flop circuit device capable of properly avoiding a scan path path hold error.

[0016]

According to a first aspect of the present invention, there is provided a scan flip-flop circuit device including a plurality of scan flip-flop circuits, wherein the scan flip-flop circuits are selectively operated in a predetermined operation mode. Things.

A scan flip-flop circuit device according to a second aspect of the present invention includes a first scan flip-flop circuit and a second scan flip-flop circuit, and operates the first and second scan flip-flop circuits alternately. It is like that.

In a scan flip-flop circuit device according to a third invention, a first scan flip-flop circuit having a logic circuit element and a latch element to which an output of the logic circuit element is input, the logic circuit element and the logic circuit A second scan flip-flop circuit having a latch element to which an output of the element is input, wherein the first and second scan flip-flop circuits are operated alternately.

In the scan flip-flop circuit device according to a fourth aspect of the present invention, the logic circuit element of the second scan flip-flop circuit has a logic circuit configuration different from that of the first scan flip-flop circuit. It has a circuit element.

According to a fifth aspect of the present invention, in the scan flip-flop circuit device, the clocks of the plurality of scan flip-flop circuits are alternately stopped.

In a scan flip-flop circuit device according to a sixth invention, input data to the plurality of scan flip-flop circuits is selectively rewritten.

A scan flip-flop circuit device according to a seventh aspect of the present invention includes a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, wherein the scan flip-flop circuit is provided. , A clock signal of an adjacent scan flip-flop circuit is input to prevent occurrence of a hold error.

In a scan flip-flop circuit device according to an eighth aspect of the present invention, the scan flip-flop circuit device includes a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side. A clock signal generated by a clock signal to be originally input to the circuit and a clock signal of a scan flip-flop circuit adjacent to the scan flip-flop circuit is input as a clock signal of the first latch circuit; The original clock signal is input to the latch circuit.

According to a ninth aspect of the present invention, in the scan flip-flop circuit device according to the seventh or eighth aspect, logic is formed so that a hold error of the scan flip-flop does not occur.

In the scan flip-flop circuit device according to the tenth aspect of the present invention, the first latch circuit on the input side receiving the clock signal and the D terminal input via the logic circuit and the Q terminal output of the first latch circuit are connected to the D terminal. A plurality of flip-flop circuits each having an output-side second latch circuit that receives as a terminal input, wherein the clock signal of the first latch circuit is such that the clock signal of the second latch circuit is “0”; And the second flip-flop circuit of the preceding stage
Is input as "1" when the latch circuit of "1" is "0".

In a scan flip-flop circuit device according to an eleventh aspect of the present invention, the scan flip-flop circuit includes a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side. In the first and second latch circuits, the delay amounts of clock signals input to the respective latch circuits are matched.

In a scan flip-flop circuit device according to a twelfth aspect, a first latch circuit on the input side receiving a clock signal and a D terminal input via a logic circuit, and a Q terminal output of the first latch circuit are connected to a D terminal. A plurality of flip-flop circuits each having an output-side second latch circuit that receives as a terminal input are provided, and a clock signal of the second latch circuit is input via a logic circuit similar to the logic circuit. Things.

In the scan flip-flop circuit device according to the thirteenth aspect, the operation control signal for selectively operating the scan flip-flop circuit is reset by a clock signal input to the scan flip-flop circuit and the scan flip-flop circuit. And a reset signal.

In the method for controlling a scan flip-flop circuit device according to a fourteenth aspect, when operating a scan flip-flop circuit device having a plurality of scan flip-flop circuits, the scan flip-flop circuit is selected in a predetermined operation mode. It is designed to operate in a typical manner.

In the method for controlling a scan flip-flop circuit device according to a fifteenth aspect, when operating the scan flip-flop circuit device including the first scan flip-flop circuit and the second scan flip-flop circuit, And the second scan flip-flop circuit is operated alternately.

In the control method of a scan flip-flop circuit device according to a sixteenth aspect, the clocks of the plurality of scan flip-flop circuits are selectively stopped.

In a control method of a scan flip-flop circuit device according to a seventeenth aspect, input data to the plurality of scan flip-flop circuits is selectively rewritten.

[0033] In a control method of a scan flip-flop circuit device according to an eighteenth aspect, a flip-flop including a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side. In operating the circuit device, a clock signal of a scan flip-flop circuit adjacent to the scan flip-flop circuit is inputted to prevent occurrence of a hold error.

In the method for controlling a scan flip-flop circuit device according to the nineteenth aspect, the flip-flop includes a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side. In operating the circuit device, the delay amounts of the clock signals input to the first and second latch circuits in the scan flip-flop circuit are adjusted to match.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment according to the present invention will be described with reference to FIGS. 1 and 2 are a block diagram showing an internal configuration of a scan flip-flop circuit SFF for implementing the first embodiment, and a connection configuration of the SFF as an example of its use. FIG. 3 shows the first embodiment.
FIG. 6 is a waveform chart showing timings in FIG. In the first embodiment, the configuration other than the specific configuration described here has the same configuration as that of the related art described above, and performs the same operation.

In FIG. 1, reference numeral 11 denotes a logical NOT circuit;
Is an AND circuit, 13 is an OR circuit, and 14 is the first input-side circuit.
And a T-side latch circuit as an output-side second latch circuit. The logic circuits 11, 12, 13
And an FF comprising first and second latch circuits:
4 constitutes an SFF, and a plurality of SFFs are connected as shown in FIG. Here, an input terminal of a PH signal for alternately operating a plurality of SFFs is added as compared with the conventional SFF, and the PH signal is a clock signal from the CLK terminal to FF: 14, that is, an input of the CLK signal. Is restricted. In FIG. 2, reference numeral 21 denotes FIG.
SFF-2A and 2C, 22 having the configuration shown in FIG. 1 are SFF-2B having the configuration shown in FIG. As described above, in the first embodiment according to the present invention, FIG.
(B) The two types of SFFs are alternately connected to the scan path. Both the SFFs of FIGS. 1A and 1B operate as normal FFs when the SM signal for shifting to the scan mode operation state is “0”, and thus are the same as the conventional SFFs. The description of the operation is omitted.

The operation when the SM signal which is the scan mode operation signal is "1" will be described. In the SFF of FIG. 1A, when the signal of the PH terminal is “1”, the CL of FF: 14
The signal at the K terminal changes to “1”, but when the signal at the PH terminal is “0”, the signal at the CLK terminal of FF: 14 is “1”.
Does not change. Conversely, in the SFF of FIG. 1A, when the signal at the PH terminal is “0”, the signal at the CLK terminal of the FF: 14 changes to “1”, but when the signal at the PH terminal is “1”. The signal at the CLK terminal of the FF 14 does not change to "1".

The operation of the embodiment according to the present invention will be described with reference to FIG. In FIG. 2, SFF-2A, 2
It is assumed that a clock skew exists between B and 2C. For example, the input of the clock signal to SFF-2B is
Assume that it is faster than FF. In this case, the conventional SF
In F, as shown in FIG.
This is the same as that of passing through 2B and transferred to SFF-2C. Since the SFF-2B and 2C have the same data in the same cycle with the basic CLK signal, the SFF cannot transfer data correctly, and cannot set data in each SFF. In the case where the SFF of the present invention is used, as shown in FIG.
It will be changed every two cycles of the signal. And
As a PH signal for alternately operating the SFF-2A, 2B and the SFF-2B, a signal for toggling "1" and "0" every cycle of the basic CLK signal is input. In the case of the first embodiment, it is desirable that the PH signal be a signal that changes at the falling edge of the CLK signal. In the present invention,
The CLK signal input to the FFs in the SFF-2A and 2C changes from "0" to "1" only during the period when the PH signal is "1". Further, the CLK signal input to the FF in the SFF-2B changes from “0” to “1” only during the period when the PH signal is “0”. That is, the clock signal input to the FF in each SFF has a change from “0” to “1” only once in two cycles, as compared with the basic clock signal. In the present invention, SF
Even if the F-2B CLK signal has a skew, the SFF-
In the cycle in which the data of 2B changes, the input CLK signal of the FF in SFF-2A and 2C does not change, so that data does not pass through from SFF-2B to SFF-2C. According to the present invention, in the SFF having the adjacent data transfer, the CLK signal of the internal FF does not change in the same cycle at the same time, so that the hold error due to the skew of the clock signal does not occur.

According to the first embodiment of the present invention, each of the logic elements has a different logic circuit configuration, and includes a latch element including the first latch circuit on the input side and a latch element including the second latch circuit on the output side. , A plurality of scan flip-flop circuits SFF-2A, 2B, including a first scan flip-flop circuit SFF-2A, 2C and a second scan flip-flop circuit SFF-2B,
2C, the scan flip-flop circuit SFF
-2A, 2B and 2C are selectively operated in a predetermined operation mode, that is, the clock signals of the first scan flip-flop circuits SFF-2A and 2C and the second scan flip-flop circuit SFF-2B are alternately changed. Stopping the first scan flip-flop circuit S
Since the FF-2A, 2C and the second scan flip-flop circuit SFF-2B are alternately operated, the scan flip-flop circuit can be selectively operated, so that a hold error in the scan path can be properly avoided. A scan flip-flop circuit device can be obtained.

According to the first embodiment of the present invention, each of the latch circuits has a different logic circuit configuration, and each has a latch element composed of a first latch circuit on the input side and a latch element composed of a second latch circuit on the output side. And a plurality of scan flip-flop circuits SFF-2A, including first scan flip-flop circuits SFF-2A and 2C and second scan flip-flop circuits SFF-2B
In operating the scan flip-flop circuit device including the scan flip-flop circuits 2B and 2C, the scan flip-flop circuits SFF-2A, 2B and 2C are selectively operated in a predetermined operation mode, that is, the first scan flip-flop circuit The first scan flip-flop circuits SFF-2A and 2C and the second scan flip-flop circuit SFF-2B are stopped by alternately stopping the clock signals of the SFF-2A and 2C and the second scan flip-flop circuit SFF-2B. Since the operation is performed alternately, it is possible to obtain a control method of the scan flip-flop circuit device that can appropriately avoid the hold error in the scan path by selectively operating the scan flip-flop circuit.

Embodiment 2 Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing a circuit configuration inside the SFF according to the second embodiment. FIG. 5 is a waveform chart showing timing in the first embodiment. In the second embodiment, the configuration other than the specific configuration described here has the same configuration as the first embodiment described above, and has the same operation. In the figure, 11 is a logical NOT circuit, 12 is a logical product circuit, 13 is a logical sum circuit, 14 is an L side latch circuit as a first latch circuit (latch) on the input side and a second latch circuit on the output side. And a T-side latch circuit. An SFF is constituted by the logic circuits 11, 12, 13 and the FF: 14 comprising the first and second latch circuits, and a plurality of SFFs are connected.

In the second embodiment, scan flip-flop circuit SFF having the configuration shown in FIG.
The PH signal for operating the scan flip-flop circuits SFF-2B having the configuration shown in FIG. 4B alternately does not control the CLK signal, but controls the data input signal.

The operation of the second embodiment will be described. As in the case of the first embodiment, when the SM signal is “0”, a normal FF operation is performed, and thus the description is omitted. When the SM signal is “1”, in the SFF of FIG. 4A, the internal FF sets the PH at the time when the clock signal at the CLK terminal changes from “0” to “1”.
When the signal holds the data of the SI terminal during the “1” period,
While the H signal is "0", it retains its own data.
Conversely, in the SFF of FIG. 4B, the internal FF outputs and holds the SI data during the period when the PH signal is "0" at the time when the clock signal at the CLK terminal changes from "0" to "1". While the PH signal is "1", it retains its own data.

FIG. 5 shows a timing chart when the SFFs in the second embodiment are connected as shown in FIG.
In the case of the second embodiment, it is better that the PH signal changes at the rise of the basic clock signal. The second embodiment is suitable because it is better that the signals are changed by one phase of the clock in the system. Operation is in the first embodiment
The operation is the same as. In a cycle in which a hold error occurs, 2B of the SFF uses the PH signal to
Since data of itself is written without taking in data of A, data does not pass through.

According to the second embodiment of the present invention, each of the logic elements has a different logic circuit configuration, and includes a latch element including the first latch circuit on the input side and a latch element including the second latch circuit on the output side. , A plurality of scan flip-flop circuits SFF-2A, 2B, including a first scan flip-flop circuit SFF-2A, 2C and a second scan flip-flop circuit SFF-2B,
2C, the scan flip-flop circuit SFF
-2A, 2B, and 2C are selectively operated in a predetermined operation mode, that is, input data to the first scan flip-flop circuits SFF-2A and 2C and the second scan flip-flop circuit SFF-2B are selected. Since the first scan flip-flop circuits SFF-2A and 2C and the second scan flip-flop circuit SFF-2B are alternately operated by rewriting, the scan flip-flop circuits can be selectively operated. Accordingly, it is possible to obtain a scan flip-flop circuit device capable of appropriately avoiding a hold error in a scan path.

According to the second embodiment of the present invention, each of the latch elements has a different logic circuit configuration, and includes a latch element composed of a first latch circuit on the input side and a latch element composed of a second latch circuit on the output side. And a plurality of scan flip-flop circuits SFF-2A, including first scan flip-flop circuits SFF-2A and 2C and second scan flip-flop circuits SFF-2B
In operating the scan flip-flop circuit device including the scan flip-flop circuits 2B and 2C, the scan flip-flop circuits SFF-2A, 2B and 2C are selectively operated in a predetermined operation mode, that is, the first scan flip-flop circuit By selectively rewriting input data to the SFF-2A, 2C and the second scan flip-flop circuit SFF-2B, the first scan flip-flop circuits SFF-2A, 2C and the second scan flip-flop circuit SFF- Since the 2B is alternately operated, it is possible to obtain a control method of the scan flip-flop circuit device that can properly avoid the hold error of the scan path by selectively operating the scan flip-flop circuit.

Embodiment 3 Third Embodiment According to the third embodiment of the present invention, FIGS. 6, 8 and 9 and FIGS.
Will be described. FIG. 6 shows an SFF according to the third embodiment.
FIG. 3 is a block diagram showing an internal configuration. FIG. 8 is a block diagram showing a connection configuration of the SFF according to the third embodiment.
FIG. 9 is a waveform chart showing timing in the third embodiment. In the third embodiment, the configuration other than the specific configuration described here has the same configuration as the first embodiment described above, and has the same operation.

In the first and second embodiments, the scan test time is twice as long as the conventional method.
Consider ways to avoid it. FIG. 19 and FIG.
0 is used to describe the cause of data through when transferring data between SFFs. For simplicity, data transfer between FFs will be described. However, since the cause of data through is related to clock skew, the same applies to SFF. When the FF is connected as shown in FIG. 19, it is equivalent to the fact that the latch circuit is actually connected. In FIG.
The block surrounded by the dotted line is the SFF (FF), and the SF
It is assumed that an L-side latch and a T-side latch are connected in F. The L-side latch is a latch connected to the input side data of the data SFF, and the T-side latch is a latch connected to the output side of the SFF.

The CLK1 signal is input to SFF1,
The clock input of the L side latch in FF1 is L1, the clock input of the T side latch is T1, the output of the L side latch is LO1,
Assume that the output of the T-side latch is TO1. Clock input L1 is the inverted clock signal of clock input T1. Similarly,
The CLK2 signal is input to the SFF2, and the L
The clock input of the side latch is L2, the clock input of the T side latch is T2, the output of the L side latch is LO2, the output of the T side latch is TO2, the CLK3 signal is input to SFF3, and the L side latch in SFF3 is input. Clock input is L3, T
The clock input of the side latch is T3 and the output of the L side latch is L
The output of the O3 and T-side latch is assumed to be TO3. The clock input L2 is the inverted clock signal of T2 and the clock input L3 is the inverted clock signal of T3.

FIG. 20 is a timing chart showing the data transfer state of FIG. In each latch, the signal input to each clock terminal is “1”.
, The input data is propagated, and if “0”, the data is held. The part where the data transfer is not performed correctly is from the T2 latch during the period “a” sandwiched between the dotted lines to the T3
Transfer to the latch. That is, the CLK3 signal and CL
Due to the presence of clock skew between the K2 signals, T
Since both L2 and L3 are "1", the data in the T2 latch propagates to the T3 latch during this period, and T2 and T3
Becomes the same data.

FIG. 6 shows a circuit for solving such a problem. In the figure, 11 is a logical NOT circuit, 12 is a logical product circuit, 13 is a logical sum circuit, 14 is an L side latch circuit 61A as a first latch circuit (latch) on the input side and a second latch circuit on the output side And a T-side latch circuit 61B. D of L-side latch circuit 61A
An input signal is applied to the terminal via the logic circuits 11, 12, and 13, and the CLK terminal of the L-side latch circuit 61A is supplied from the preceding scan flip-flop circuit via a logic circuit including the logic circuits 11, 12, and 13 to the CLK terminal. And a clock signal generated by the CLKP signal of the clock signal and the CLK signal which is the original clock signal. CL of T side latch circuit 61B
A CLK signal which is an original clock signal is applied to the K terminal. An FF comprising the logic circuits 11, 12, 13 and first and second latch circuits 61A, 61B:
4 constitutes an SFF, and a plurality of SFFs are connected as shown in FIG. The components shown in FIG. 6 are circuits similar to those described several times. In the SFF of the third embodiment, in addition to the CLK signal which is the original clock signal so far, the CLKP signal which is the clock signal introduced from the CLKP terminal connected to the preceding stage is simultaneously inputted. Since the connection of the scan path of the SFF is automatically performed based on the layout information, the scan path is connected (the scan-out signal of the preceding SFF and the scan-in signal of the subsequent SFF are connected). If not, they are located very close. Therefore, it is not difficult to connect a clock signal of an arbitrary SFF.

In the SFF of the third embodiment, the L-side latch 6
One clock signal is generated from the CLK signal, which is the original clock signal of itself, and the CLKP signal, which is the preceding clock signal. Of course, the input is selected by the SM signal as the scan mode operation signal introduced to the SM terminal. Therefore, as in the previous embodiments, when the signal at the SM terminal is “0”, The operation is the same as that of a normal FF. In the conventional SFF, the clock signal of the L-side latch is an inversion of the clock signal of the T-side latch.
In the FF, the clock signal of the L-side latch 61A is T
The logic circuit 1 is adjusted so that the clock signal of the latch 61B on the side is “0” and the clock signal of the T-side latch of the preceding SFF is “0”, it becomes “1”.
The logic of the logic circuit including 1, 12, 13 is formed. By doing so, the data through shown in FIG. 20 does not occur.

FIGS. 6 and 9 show a configuration example and a timing chart of the third embodiment in comparison with the conventional example. In FIG. 6, the number of clock signal terminals input to the SFF is increased as compared with the conventional example. In FIG. 9, there is no case where the clocks of the T2 latch and the L3 latch are both “1” as in the conventional example of FIG. No slew occurs.

According to the third embodiment of the present invention, the first latch circuit 61A on the input side that receives the clock signal and the D terminal input via the logic circuit including the logic circuits 11, 12, and 13 and the first latch circuit 61A Output-side second latch circuit 6 receiving the Q terminal output of latch circuit 61A as the D terminal input
1B respectively having a plurality of flip-flop circuits S
FF1, SFF2 and SFF3, and the clock signal of the first latch circuit 61A is supplied to the second latch circuit 6A.
When the 1B clock signal is “0” and the second latch circuit of the adjacent preceding flip-flop circuit is “0”, the signal is input as “1”. By inputting a clock signal and forming a logic so that a hold error does not occur, it is possible to obtain a scan flip-flop circuit device capable of properly avoiding a hold error in a scan path.

According to the third embodiment of the present invention, a plurality of flip-flop circuits SFF1, SFF2, SFF3 each having a first latch circuit 61A on the input side and a second latch circuit 61B on the output side are provided. When the flip-flop circuit device provided is operated, a clock signal of the adjacent scan flip-flop circuit is input to the scan flip-flop circuit to prevent occurrence of a hold error. By inputting a signal, it is possible to obtain a control method of a scan flip-flop circuit device which can appropriately avoid a hold error in a scan path.

Embodiment 4 Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram showing an internal configuration of the SFF according to the fourth embodiment. FIG. 8 is a block diagram showing a connection configuration of the SFF according to the fourth embodiment. FIG. 9 is a waveform chart showing timing in the fourth embodiment. In the fourth embodiment, for configurations other than the specific configuration described here,
It has a configuration similar to that of the first embodiment described above, and has a similar effect. In the figure, 11 is a logical NOT circuit, 12 is a logical product circuit, 13 is a logical sum circuit, 61A is an L side latch circuit as a first latch circuit (latch) on the input side, and 61B is a FF together with the L side latch circuit 61A. And a T-side latch circuit as an output-side second latch circuit. An FF comprising the logic circuits 11, 12, 13 and first and second latch circuits 61A, 61B
Constitutes an SFF, and a plurality of SFFs are connected as shown in FIG. An input signal is applied to the D terminal of the L-side latch circuit 61A via the logic circuits 11, 12, and 13, and the CLK terminal of the L-side latch circuit 61A is applied via a logic circuit including the logic circuits 11, 12, and 13. A clock signal generated by the CLKP signal from the preceding scan flip-flop circuit and the CLK signal that is the original clock signal is applied. A CLK signal, which is an original clock signal, is applied to a CLK terminal of the T-side latch circuit 61B.

In the conventional SFF, the delay difference is only one stage of the inverting circuit. However, in the third embodiment, the delay difference of the clock signal between the T-side latch and the L-side latch becomes large in the SFF. Therefore, there is a possibility that skew exists in the change of the clock signal only in the T-side latch circuit 61A and the L-side latch circuit 61B. Therefore, the T-side latch circuit 6
A delay adjusting circuit such as a circuit including logic circuits 11, 12, and 13 similar to the latch clock input to the CLK terminal of the latch circuit 61B is also inserted into the latch clock input to the CLK terminal of 1B, and the delay amount of the clock signal is inserted. To match as much as possible. The circuit configuration to be inserted is not specified.

According to the fourth embodiment of the present invention, in the configuration shown in the third embodiment, logic circuits 11, 12,.
13, a first latch circuit 61A on the input side for receiving a clock signal and a D terminal input via a logic circuit including an output terminal 13, and a second latch on the output side for receiving the Q terminal output of the first latch circuit 61A as a D terminal input And a plurality of flip-flop circuits SFF1, SFF2,
An SFF 3 for inputting the clock signal of the second latch circuit 61B via a logic circuit similar to the logic circuit of the first latch circuit 61A, and providing the first latch circuit 61A and the second latch circuit Regarding the circuit 61B,
Since the delay amounts of the respective clock signals are matched, the hold error of the scan path can be accurately avoided by adjusting the delay amounts of the clock signals in the first and second latch circuits 61A and 61B. A scan flip-flop circuit device can be obtained.

According to the fourth embodiment of the present invention, in the method shown in the third embodiment, the logic circuit 11
A first latch circuit 61A on the input side receiving a clock signal and a D terminal input via a logic circuit including 12 and 13, and a second latch circuit on the output side receiving the Q terminal output of the first latch circuit 61A as a D terminal input. Flip-flop circuits SFF1, SF each having a latch circuit 61B
In operating the flip-flop circuit device including F2 and SFF3, the clock signal of the second latch circuit 61B is input via a logic circuit similar to the logic circuit of the first latch circuit 61A, The first latch circuit 61A and the second latch circuit 61B are configured to match the delay amounts of the respective clock signals, so that the first and second latch circuits 61A and 61B.
By adjusting the delay amount of the clock signal in the above, it is possible to obtain a control method of the scan flip-flop circuit device that can appropriately avoid the hold error of the scan path.

Embodiment 5 FIG. Embodiment 5 of the present invention will be described with reference to FIGS. FIG. 10 is a block diagram showing a configuration according to the fifth embodiment. Figure 1
1 is a block diagram showing a PH signal generation circuit. In the fifth embodiment, the configuration other than the specific configuration described here has the same configuration as the first embodiment described above, and has the same operation.

In the first and second embodiments, it is necessary to newly input a PH signal for alternately operating a plurality of scan flip-flop circuits. But,
Many systems cannot increase the number of chip terminals. Therefore, consider mounting a circuit that automatically generates a PH signal.

FIG. 10 is a diagram of a scan path test system equipped with a PH generation circuit. 90 is a PH signal generation circuit. The PH signal is input to the PH generation circuit, and the PH signal is output. The CLK signal is a clock signal of the LSI, the RST signal is a signal for initializing the PH signal, and the RST signal may be a reset signal which always exists to determine the initial state of the system. No additional signals are required.

FIG. 11 shows an example of a PH signal generation circuit. RS
When the T signal is "1", "0" is input to the FF, so that the output (output PH signal) of the FF is fixed at "0".
When the RST signal is “0”, an inverted signal of the FF is input to the FF. Therefore, each time the CLK signal changes from “0” to “1”, the FF outputs an inverted signal of the currently held signal. . That is, the PH signal is synchronized with the CLK signal,
A signal that repeats "1" and "0" can be output.

According to the fifth embodiment of the present invention, PH signals as operation control signals for selectively operating scan flip-flop circuits 1A, 1B, 1C and 1D are applied to scan flip-flop circuits 1A, 1B, 1C and 1D. , And an RST signal as a reset signal for performing a reset operation of the scan flip-flop circuits 1A, 1B, 1C, and 1D.
To obtain a scan flip-flop circuit device capable of accurately avoiding a scan path path hold error with a simple configuration without increasing the number of terminals by automatically generating operation control signals for selectively operating B, 1C, and 1D. Can be.

As described above, according to the present invention, when a large-scale system LSI is automatically designed using an EDA tool, a hold error between scan flip-flop circuits which occurs at the end of a design stage can be avoided. This has the effect of greatly increasing the design efficiency. In the present invention, circuits constituting parts such as a flip-flop, a selection circuit, and a latch circuit are not specified, and any configuration having the same function may be used.

[0066]

According to the first aspect of the present invention, a plurality of scan flip-flop circuits are provided, and the scan flip-flop circuits are selectively operated in a predetermined operation mode. A scan flip-flop circuit device that can be avoided accurately can be obtained.

According to the second aspect, the first and second scan flip-flop circuits are provided, and the first and second scan flip-flop circuits are operated alternately. A scan flip-flop circuit device capable of appropriately avoiding a hold error in a scan path can be obtained.

According to the third aspect, the first scan flip-flop circuit including the logic circuit element and the latch element to which the output of the logic circuit element is input, and the input of the logic circuit element and the output of the logic circuit element A second scan flip-flop circuit having a latch element to be operated, and the first and second scan flip-flop circuits are operated alternately, so that a logic circuit element and an output of the logic circuit element are input. A scan flip-flop circuit device that includes a scan flip-flop circuit having a latch element and a scan error can be properly avoided.

According to the fourth aspect, the logic circuit element of the second scan flip-flop circuit has a logic circuit element having a different logic circuit configuration from the logic circuit element of the first scan flip-flop circuit. In a device provided with first and second scan flip-flop circuits each having a logic circuit element having a different logic circuit configuration, it is possible to obtain a scan flip-flop circuit device which can properly avoid a hold error in a scan path path. it can.

According to the fifth aspect of the present invention, the clocks of the plurality of scan flip-flop circuits are alternately stopped, so that the first and second scan flip-flop circuits are alternately operated, and the scan path of the scan path is controlled. A scan flip-flop circuit device that can appropriately avoid a hold error can be obtained.

According to the sixth aspect, the input data to the plurality of scan flip-flop circuits is selectively rewritten, so that the plurality of scan flip-flop circuits are alternately operated by selectively rewriting the input data. Thus, it is possible to obtain a scan flip-flop circuit device that can appropriately avoid a hold error in a scan path.

According to the seventh aspect, a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side are provided, and the scan flip-flop circuit adjacent to the scan flip-flop circuit is provided. Since the occurrence of the hold error is prevented by inputting the clock signal of the flip-flop circuit, it is possible to obtain a scan flip-flop circuit device capable of properly avoiding the hold error in the scan path.

According to the eighth aspect of the present invention, there are provided a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side. A clock signal generated by a clock signal to be generated and a clock signal of a scan flip-flop circuit adjacent to the scan flip-flop circuit is input as a clock signal of the first latch circuit. , The clock signal of the adjacent scan flip-flop circuit is input to the scan flip-flop circuit to prevent the occurrence of a hold error, and to prevent the hold error in the scan path path. A flip-flop circuit device can be obtained.

According to the ninth aspect of the present invention, in the seventh or eighth aspect, the logic is configured so that a hold error of the scan flip-flop does not occur, so that the hold error of the scan path can be properly avoided. A scan flip-flop circuit device can be obtained.

According to the tenth aspect, the first latch circuit on the input side receiving the clock signal and the D terminal input via the logic circuit and the output receiving the Q terminal output of the first latch circuit as the D terminal input And a plurality of flip-flop circuits each having a second latch circuit on the side of the first flip-flop circuit, wherein the clock signal of the first latch circuit is such that the clock signal of the second latch circuit is “0” and When the second latch circuit of the latch circuit is “0”, “1”
, It is possible to obtain a scan flip-flop circuit device that can accurately avoid a hold error in the scan path.

According to the eleventh aspect, there are provided a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, and the first and second latch circuits in the scan flip-flop circuit are provided. Since the delay amount of the clock signal input to each of the second latch circuits is adjusted, a scan flip-flop circuit device capable of appropriately avoiding a hold error in a scan path can be obtained.

According to the twelfth aspect, the first latch circuit on the input side receiving the clock signal and the D terminal input via the logic circuit, and the output receiving the Q terminal output of the first latch circuit as the D terminal input And a plurality of flip-flop circuits each having a second latch circuit on the side of the scan path. The clock signal of the second latch circuit is input via the same logic circuit as the logic circuit. Can be obtained accurately.

According to the thirteenth aspect, the operation control signal for selectively operating the scan flip-flop circuit includes the clock signal input to the scan flip-flop circuit and the reset signal for performing the reset operation of the scan flip-flop circuit. By automatically generating an operation control signal for selectively operating the scan flip-flop circuit, a scan flip-flop circuit device capable of accurately avoiding a scan path path hold error with a simple configuration is obtained. be able to.

According to the fourteenth aspect, when operating a scan flip-flop circuit device having a plurality of scan flip-flop circuits, the scan flip-flop circuit is selectively operated in a predetermined operation mode. Thus, it is possible to obtain a control method of a scan flip-flop circuit device that can appropriately avoid a hold error in a scan path.

According to the fifteenth aspect, when operating the scan flip-flop circuit device including the first scan flip-flop circuit and the second scan flip-flop circuit, the first and second scan flip-flop circuits are operated. Are alternately operated, so that it is possible to obtain a control method of the scan flip-flop circuit device that can appropriately avoid a hold error in the scan path.

According to the sixteenth aspect, the fourteenth or the first
According to the fifth aspect of the present invention, since the clock signals of the plurality of scan flip-flop circuits are selectively stopped, the plurality of scan flip-flop circuits are selectively operated to accurately avoid a scan path path hold error. A control method of a scan flip-flop circuit device that can be obtained can be obtained.

According to the seventeenth aspect, the fourteenth or the first
According to the fifth aspect of the present invention, the input data to the plurality of scan flip-flop circuits is selectively rewritten, so that the plurality of scan flip-flop circuits are selectively operated to accurately reduce the hold error of the scan path. A method of controlling the scan flip-flop circuit device that can be avoided can be obtained.

According to the eighteenth aspect, when operating a flip-flop circuit device including a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, Since the occurrence of a hold error is prevented by inputting a clock signal of an adjacent scan flip-flop circuit to the scan flip-flop circuit, a method of controlling a scan flip-flop circuit device that can accurately avoid a hold error in a scan path path is provided. Obtainable.

According to the nineteenth aspect, when operating a flip-flop circuit device including a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, In the first and second latch circuits in the scan flip-flop circuit, the delay amounts of clock signals input to the first and second latch circuits are adjusted to each other. Therefore, a scan flip-flop circuit device capable of accurately avoiding a hold error in a scan path path. A control method can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a usage example of the first and second embodiments according to the present invention.

FIG. 3 is a waveform chart illustrating timing in the first embodiment according to the present invention.

FIG. 4 is a block diagram showing a configuration according to a second embodiment of the present invention.

FIG. 5 is a waveform chart illustrating timings according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram illustrating a usage example of the third and fourth embodiments according to the present invention.

FIG. 9 is a waveform diagram illustrating timings in the third and fourth embodiments according to the present invention.

FIG. 10 is a block diagram illustrating a usage example of the fifth embodiment according to the present invention.

FIG. 11 is a block diagram showing a configuration according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration for explaining a scan test method.

FIG. 13 is a block diagram showing a configuration of a conventional scan flip-flop circuit.

FIG. 14 is a waveform chart for explaining data movement in the scan test method.

FIG. 15 is a waveform chart for explaining a hold error.

FIG. 16 is a block diagram for explaining a clock tree method.

FIG. 17 is a block diagram illustrating a configuration of a flip-flop circuit.

FIG. 18 is a waveform chart for explaining the operation of the flip-flop circuit.

FIG. 19 is a block diagram for explaining a hold error using a latch.

FIG. 20 is a waveform chart for explaining a hold error operation of the latch circuit.

[Explanation of symbols]

11 to 13 logic circuit, 14 latch circuit, 21, 22
Scan flip-flop circuit (SFF).

Claims (19)

[Claims] 1. A scan flip-flop circuit device comprising a plurality of scan flip-flop circuits, wherein the scan flip-flop circuit is selectively operated in a predetermined operation mode. 2. A first scan flip-flop circuit,
A second scan flip-flop circuit;
And a second scan flip-flop circuit alternately operated. 3. A first scan flip-flop circuit having a logic circuit element and a latch element to which an output of the logic circuit element is inputted, a first scan flip-flop circuit comprising: a logic circuit element and a latch element to which an output of the logic circuit element is inputted. A scan flip-flop circuit device comprising a second scan flip-flop circuit having the first scan flip-flop circuit and the second scan flip-flop circuit. 4. The logic circuit element of the second scan flip-flop circuit has a logic circuit element having a different logic circuit configuration from the logic circuit element of the first scan flip-flop circuit. The scan flip-flop circuit device according to claim 1. 5. The scan flip-flop circuit device according to claim 1, wherein clock signals of said plurality of scan flip-flop circuits are selectively stopped. 6. The scan flip-flop circuit device according to claim 1, wherein input data to said plurality of scan flip-flop circuits is selectively rewritten. 7. A plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, and a clock signal of a scan flip-flop circuit adjacent to the scan flip-flop circuit is provided. A scan flip-flop circuit device, wherein a scan error is input to prevent occurrence of a hold error. 8. A plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, wherein a clock signal to be originally input to the first latch circuit and A clock signal generated by a clock signal of a scan flip-flop circuit adjacent to the scan flip-flop circuit is input as a clock signal of the first latch circuit, and an original clock signal is input to the second latch circuit. The scan flip-flop circuit device according to claim 7, wherein: 9. The scan flip-flop circuit device according to claim 7, wherein logic is formed so that a hold error of the scan flip-flop does not occur. 10. A first latch circuit on an input side receiving a clock signal and a D terminal input via a logic circuit, and a second latch on an output side receiving a Q terminal output of the first latch circuit as a D terminal input. And a plurality of flip-flop circuits each including a first flip-flop circuit, wherein the clock signal of the first latch circuit is “0” when the clock signal of the second latch circuit is “0”, and 10. The scan flip-flop circuit device according to claim 9, wherein when the latch circuit is "0", it is inputted as "1". 11. A plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, wherein the first and second latch circuits in the scan flip-flop circuit are provided. 11. The scan flip-flop circuit device according to claim 9, wherein delay amounts of clock signals input to the scan flip-flop circuits are adjusted to each other. 12. A first latch circuit on the input side receiving a clock signal and a D terminal input via a logic circuit, and a second latch on the output side receiving a Q terminal output of the first latch circuit as a D terminal input. 12. The flip-flop circuit according to claim 11, further comprising a plurality of flip-flop circuits each including a circuit, wherein the clock signal of the second latch circuit is input via a logic circuit similar to the logic circuit. Scan flip-flop circuit device. 13. An operation control signal for selectively operating a scan flip-flop circuit is generated by a clock signal input to the scan flip-flop circuit and a reset signal for performing a reset operation of the scan flip-flop circuit. 7. The scan flip-flop circuit device according to claim 1, wherein: 14. A scan flip-flop circuit for selectively operating a scan flip-flop circuit in a predetermined operation mode when operating a scan flip-flop circuit device having a plurality of scan flip-flop circuits. Control method of the loop circuit device. 15. When operating a scan flip-flop circuit device including a first scan flip-flop circuit and a second scan flip-flop circuit, the first and second scan flip-flop circuits are operated alternately. A method for controlling a scan flip-flop circuit device according to claim 1. 16. The control method of a scan flip-flop circuit device according to claim 14, wherein clock signals of the plurality of scan flip-flop circuits are selectively stopped. 17. The control method for a scan flip-flop circuit device according to claim 14, wherein input data to the plurality of scan flip-flop circuits is selectively rewritten. 18. When operating a flip-flop circuit device including a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, the flip-flop circuit device adjacent to the scan flip-flop circuit is operated. A method of controlling a scan flip-flop circuit device, wherein a clock signal of a matching scan flip-flop circuit is input to prevent occurrence of a hold error. 19. When operating a flip-flop circuit device including a plurality of flip-flop circuits each having a first latch circuit on the input side and a second latch circuit on the output side, the scan flip-flop circuit includes: 19. The control method for a scan flip-flop circuit device according to claim 18, wherein the first and second latch circuits adjust a delay amount of a clock signal input to each of the first and second latch circuits.