JP2002264406A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor which can carry out a parallel operation for a plurality of inputted image data by a single operation means and can easily change its processing contents and order. SOLUTION: The image processor is provided with an input means for inputting image data, an image processing means for carrying out image processing to the image data, and an output means for outputting the image processed image data as sensible images. In the image processor, there are provided a plurality of input control means (11 and 19) for carrying out an input process for image data, an operation part (13) for processing image data inputted by the input control means (11 and 19), and a global processor (15) for controlling at least the operation part (13) and the input control means (11 and 19). The global processor (15) monitors process requests from the plurality of input control means (11 and 19), and makes the operation part (13) execute the process requests from the plurality of input control means (11 and 19) in accordance with a priority order of the requests from the input control means (11 and 19) when the plurality of image data are inputted at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data, such as a digital copying machine, a facsimile machine, and a multifunction printer, and more particularly, to an image processing apparatus capable of simultaneously processing a plurality of input image data. It relates to a processing device.

[0002]

2. Description of the Related Art For example, in a multifunctional digital copying machine, an original is read by an input means, and an image processing section performs predetermined processing 1 on the obtained digital image data to generate image data. The image data is temporarily stored in a memory, and the data is transferred to, for example, a facsimile processing unit via the memory. At the same time, predetermined processing 2 is performed on the image data stored in the memory, and the laser element is light-modulated and transferred to an output unit for forming a latent image corresponding to a document image on a photoconductor. In addition,
In the processing 1 and the processing 2, the respective processing units are individually provided, so that the two processings are performed in parallel.

[0003]

As described above, in the conventional image processing apparatus, when a plurality of processes are performed in parallel, a plurality of processing units corresponding to a plurality of image data are provided in parallel to perform the parallel operation. Was realized. In addition, in the case of a parallel operation in which similar processing is performed on a plurality of image data, it is necessary to have a plurality of the same processing units. Processing may be limited.

[0004] It is an object of the present invention to provide an image processing apparatus in which the parallel operation on a plurality of input images is performed by a single arithmetic unit, so that the scale of the image processing unit does not need to be increased.

[0005]

In order to solve the above-mentioned problems, according to the present invention, an analog image signal is inputted and converted into digital image data, or digital image data is inputted. Means for inputting image data in an image processing apparatus comprising: an image processing means for performing image processing on the digital image data; and an output means for outputting the image-processed image data as a visualized image. Input control means, and an arithmetic means for processing image data input by the input control means,
A global processor that controls at least the arithmetic means and input control means, wherein the global processor monitors processing requests from a plurality of input control means,
When a plurality of image data are inputted at the same time when each processing is selected and executed by the arithmetic means according to the request, in response to a processing request from the plurality of input control means, The arithmetic means is executed in accordance with the priority order of requests.

Further, according to the invention described in claim 2, according to claim 1,
In the invention described above, the input control means includes an input memory for storing image data, and a storage amount determining means for determining that the image data in the input memory has reached a predetermined amount. According to a third aspect of the present invention, in the first aspect of the present invention, a priority switching storage unit for switching the priority order is provided, and a global processor is provided with a plurality of global processors by a signal stored in the priority switching storage unit. The configuration is such that the priority of processing for input image data is switched. According to a fourth aspect of the present invention, in the third aspect of the invention, the priority switching storage means has switching information for a number of processes for a plurality of input image data, and switches the priority for each process. It was configured.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram of a multi-function printer shown as an example of an image processing apparatus in which the present invention is implemented.

In such a multifunctional printer (hereinafter referred to as MFP), the reading unit 1 for optically reading an original uses a mirror and a lens to receive light reflected from a lamp by a mirror and a lens (for example, a CCD). )
Focus on An image signal converted into an electric signal by a light receiving element mounted on an SBU (sensor board unit) 2 serving as image input means is converted into digital image data and then output from the SBU 2. Further, the image data is input to a CDIC (compression / decompression and data interface control unit) 3 which is a data transfer unit. The CDIC 3 controls all image data transmission between the functional device and the data bus. The CDIC 3 controls the data transfer between the SBU 2, the parallel bus, and the IPP (image processing processor, image processing unit) 4, and the communication between the system controller 5 and the process controller that manages the overall control of the MFP. is there. S
The image data from BU2 is sent to IPP via CDIC3.
4 where the signal deterioration of the optical system and the signal deterioration due to the quantization into digital data are corrected, and the CD
Output to IC3.

The jobs in this embodiment include a job for storing the read image in a memory (image storage means) and reusing the read image, and a job for not storing the read image in the memory. Hereinafter, each case will be described. As an example of storing the data in the memory, there is a method of operating the reading unit 1 only once, storing the data in the memory, and reading out the stored data a plurality of times when a plurality of originals are copied. As an example in which no memory is used, when only one document is copied, it is only necessary to reproduce the read image as it is, so that there is no need to access the memory.

First, when the memory is not used, the data transferred from the IPP 4 to the CDIC 3 is returned from the CDIC 3 to the IPP 4 again. Then, image quality processing for converting the luminance data output from the light receiving element (CCD) into the area gradation in the IPP 4 is performed. The image data after the image quality processing is transferred from the IPP 4 via the CDIC 3 to the VDC (video data control unit) 6 serving as image output means. Post-processing relating to the dot arrangement and pulse control for reproducing the dots are performed on the image data changed to the area gradation, and the image forming unit 7 forms a reproduced image on transfer paper.

Next, an image processing section (corresponding to the IPP4 or the like) of this embodiment will be described with reference to FIG.
First, the input 1 data input by the input unit is input to the input 1 control unit 11 in the image processing unit. The input 1 control means 11 adds the input 1 data to the input 1 memory 12 in response to the write instruction of the write control signal from the preceding stage.
Stored under control of s and write control signal. As described above, once the input 1 data is temporarily stored in the memory, the conversion between the external input speed and the transfer speed in the image processing unit can be performed. The same applies to the input data 2 by the input 2 control means 19 and the input 2 memory 20.
Further, when processing two or more input data, while one input data is being processed by the arithmetic unit 13, the processing of the other input data can be made to wait.

When a predetermined amount of data is stored in the input 1 memory 12, the input 1 control means 11 reads a predetermined amount of input data from the input 1 memory 12, transfers the read data to the arithmetic unit 13, and completes the transfer. At this point, a processing request flag is set to the global processor 15. The access speed of reading and writing to the input 1 memory 12 is twice or more as fast as the input speed of input data. The write and the transfer from the memory to the input register in the operation unit 13 can be performed simultaneously. As shown in the figure, this embodiment has a configuration having two or more input control means, and can receive two or more input data in parallel and transfer them to the arithmetic unit 13.

The input 1 data from the input means is stored in the input 1 register in the operation unit 13 and is subjected to predetermined image processing by the operation unit 14 under the control of the global processor 15, and the result is output to the output 1 register. Stored in a register. Arithmetic unit
The contents of the data transfer and the operation processing in 13 are all based on the processing flow program held in the program memory 16. It performs arithmetic processing in the calculator 14 and the calculator 14, and controls the output register.

In this embodiment, two or more input registers and two or more output registers are provided so that two or more input data can be processed in the arithmetic unit 13 in parallel. The arithmetic unit 14 has a single configuration, but the arithmetic processing for two or more input data is time-divided,
This makes it possible for a single arithmetic unit 14 to perform arithmetic processing on a plurality of data. Also, global processor 15
Is a computing unit 13 of the input 1 control means and the input 2 control means.
Process request flag indicating the end of transfer to
The processing flow in the calculation unit 13 is executed in response to both processing requests, but the number of times of monitoring the request flag, frequency, time,
The priority and the like are based on the processing selection program in the program memory 16.

The data after the operation stored in the output 1 register is read out by the output 1 control means 17 under the control of the address and the read control in accordance with the instruction of the global processor 15 and transferred to the output 1 memory 18. When predetermined output data is stored in the output 1 memory 18, the output 1 control means 17
In this control, the data in the output 1 memory 18 is read out under the control of the address and the read control, and output as output data to the subsequent stage in synchronization with the write control signal. Output 2
The same applies to the case where the control means 21 and the output 2 memory 22 are used. As described above, in this embodiment, a configuration having two or more output control means is provided, and two or more calculation results from the calculation unit 13 can be output to the subsequent stage in parallel.

Next, referring to FIG. 3, the input control means 11, 19
Will be described. This input control means, when write-inputting the input data from the input means of the preceding stage into the input memories 12 and 20, indicates the written data amount indicating the written data amount.
The value of the ORD number register 23 is updated. The written WO
When the value of the RD number register 23 reaches the value of the read WORD number register 24 indicating the amount of data that can be transferred to the operation unit 13 at the next stage, the read transfer from the input memories 12 and 20 to the operation unit 13 is performed. Becomes possible.

The global processor 15 writes an arbitrary value to the read transfer GO register 25 in the input control means to read the read WOR from the input memories 12 and 20 to the arithmetic unit 13.
Input data is transferred by the value of the D number register 24, and a transfer completion flag is set after the end. The global processor 15 can monitor the transfer achievement flag, and starts processing in the arithmetic unit 13 according to the transfer achievement flag.

Read transfer GO register in input control means
Global processor 15 to 25 and transfer completion flag 26
The control of the number of accesses, the frequency, the priority, and the time, and the arithmetic processing flow after the transfer achievement flag processing are based on the processing flow in the program memory 16.
The image processing apparatus of the present invention can be configured to have two or more such input control means, receive a request for a plurality of input data in response to a processing request, and perform an arithmetic processing flow corresponding to the request. Becomes

Next, referring to FIG. 4, a global processor executed according to a program in the program memory 16 will be described.
The 15 processing flows will be described. The global processor 15 controls the monitoring of the transfer achievement flag processing by the input control means 11 and 19, the arithmetic processing, and the trigger of the transfer GO by this processing flow. In the following, the input control means is set to 2
The following describes an example of a configuration that can perform different arithmetic processing on two different input data.

First, the transfer completion flag of the input 1 data is confirmed (S1). If the transfer is achieved (“ON” in S1), the arithmetic unit 13 performs the arithmetic processing 1 on the input 1 data (S2). After the arithmetic operation is completed, the read transfer GO for the next input 1 data is performed. (S3). On the other hand, if the transfer completion flag is not set ([OFF] in S1), the read transfer GO for the next input data is immediately performed.
(S3).

Next, the transfer completion flag of the input 2 data is confirmed (S4). If the transfer is achieved ("ON" in S4), the operation unit 13 performs the operation process 2 on the input 2 data (S5), and after the operation is completed, the read transfer GO for the next input 2 data. (S6). On the other hand, if the transfer achievement flag is not set ("OFF" in S4), the read transfer GO for the next input data is immediately performed.
(S6). By repeating the above operation, different arithmetic processing can be performed on two different input data, and a processing request of the input data by the global processor 15 is accepted according to the input speed.

Next, referring to FIG. 5, the processing flow of the global processor 15 according to the priority will be described in the case of having two input control means and performing different arithmetic processing on two different input data. As shown in the figure, first, the transfer completion flag of the input 1 data is confirmed (S11). If the transfer is achieved (“ON” in S11), the operation unit 13
Performs the arithmetic processing 1 on the input 1 data (S1
2). Then, after the operation is completed, a trigger of the read transfer GO is set for the next input 1 data (S13), and the process returns to step S11.

On the other hand, if the transfer achievement flag is not set ("OFF" in S11), the transfer achievement flag of the input 2 data is confirmed (S14). If the transfer is achieved ("ON" in S14), the arithmetic unit 13 performs arithmetic processing 2 on the input 2 data (S15). Then, after the operation is completed, a trigger of the read transfer GO is set for the next input 2 data (S16), and the process returns to step S11. Step S14
If the transfer flag has not been set ("OFF" in S14), the process immediately returns to step S11.

By repeating the above operation, different arithmetic processing can be performed on two different input data, and the global processor 15 can accept processing requests for input 1 data and input 2 data. It is possible to receive input 1 data preferentially, that is, to receive a request according to the priority of input data.

Next, referring to FIG. 6, a processing flow in which the priority order can be selected will be described. In this embodiment, the global processor 15 monitors the transfer achievement flags of the input control means 11 and 19, performs arithmetic processing, triggers a transfer GO, and controls a priority switching signal in a priority switching storage unit. It should be noted that a RAM or a register external to the global processor 15 is used as the priority switching storage unit, so that data can be read / written from the global processor 15. Also, the priority switching means can simultaneously read / write from the outside, and can set switching of the priority from the outside. In the example shown in FIG. 6, the priority order switching storage unit 27 has switching information for the number of processes for a plurality of input image data, and switches the priority for each process.

First, the transfer completion flag of the input 1 data is confirmed (S21). If the transfer is achieved (“ON” in S21), the arithmetic unit 13 performs arithmetic processing 1 on the input 1 data (S22). Further, after the operation is completed, a read transfer GO is triggered for the next input 1 data (S2).
3). Next, a priority switching signal for the arithmetic processing 1 is confirmed with reference to the priority switching memory 27 (see FIG. 6) (S24). If the priority is on, the process returns to the input 1 transfer achievement flag check in step S21. If the priority is "off", the process proceeds to the input 2 transfer achievement flag check (S25), and if the transfer achievement flag is not set (step S25). ("OFF" in S25), the process returns to step S21, and the transfer completion flag of the input 1 data is confirmed. If the transfer is achieved (S
The arithmetic unit 13 performs an arithmetic operation 2 on the input 2 data (S26). Then, after the operation is completed, a trigger of the read transfer GO is set up for the next input 2 data (S
27).

Subsequently, a priority switching signal for the arithmetic processing 2 is confirmed (S28). If the priority is on, the flow proceeds to the input 2 transfer achievement flag confirmation in step S25.
If the priority is off, the process proceeds to the input 1 transfer achievement flag confirmation in step S21. By repeating the above operation, two different
It is possible to perform different arithmetic processing on two input data, and furthermore, the global processor 15 accepts the processing request of the input 1 data and the input 2 data preferentially according to the priority. It is also possible to selectively switch the priority order.

[0028]

As described above, according to the present invention,
According to the first aspect of the present invention, the global processor monitors processing requests from a plurality of input control units, and when a plurality of image data are input at the same time, calculates in accordance with the priority order of the requests from each of the input control units. Since the image data is processed by the means, the processing for a plurality of input image data can be executed by a single arithmetic means according to the priority. According to the second aspect of the invention,
In the invention described in the above, the image data is accumulated in the input control means, and when the accumulated image data reaches a predetermined amount, it is known that the predetermined amount has been reached. Therefore, processing by a single arithmetic unit is facilitated.

According to the third aspect of the present invention, the first aspect of the present invention is provided.
In the invention described above, the priority of the processing on a plurality of input image data is switched by the signal stored in the priority switching storage means, so that it is possible to flexibly deal with the situation. In the invention according to claim 4,
According to the third aspect of the present invention, the priority order is switched for each process by the switching information corresponding to the number of processes for a plurality of input image data, so that a flexible response according to a situation is more effectively realized. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a multifunction printer shown as an example of an image processing apparatus in which the present invention is implemented.

FIG. 2 is a block diagram illustrating a configuration of a main part of an image processing apparatus according to an exemplary embodiment of the present invention.

FIG. 3 is a configuration diagram of a main part of an image processing apparatus showing an embodiment of the present invention.

FIG. 4 is a processing flowchart of a main part of an image processing apparatus according to an embodiment of the present invention.

FIG. 5 is a processing flowchart of a main part of an image processing apparatus showing another embodiment of the present invention.

FIG. 6 is a processing flowchart of a main part of an image processing apparatus showing another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 reading unit 11 input 1 control means 12 input 1 memory 13 arithmetic unit 14 arithmetic unit 15 global processor 16 program memory 23 written WORD register 24 read WORD register 27 priority switching storage unit

Claims (4)

[Claims] 1. An input means for inputting an analog image signal to convert it into digital image data or inputting digital image data; an image processing means for performing image processing on the digital image data; A plurality of input control means for performing input processing of image data, and an arithmetic means for processing image data input by the input control means in an image processing apparatus having output means for outputting the obtained image data as a visualized image And a global processor that controls at least the arithmetic means and input control means. The global processor monitors processing requests from a plurality of input control means, selects each processing in response to the request, and When a plurality of image data are input at the same time, the processing request from the plurality of input control means is An image processing apparatus configured to cause the calculation means to execute the requests in accordance with the priority order of the requests from the input control means. 2. The image processing apparatus according to claim 1, wherein
An image processing apparatus comprising: an input memory for storing image data in an input control unit; and a storage amount determining unit for determining that the amount of image data in the input memory has reached a predetermined amount. . 3. The image processing apparatus according to claim 1, wherein
A priority switching storage unit for switching the priority order, wherein the global processor switches the processing priority order for a plurality of input image data by a signal stored in the priority switching storage unit. Characteristic image processing device. 4. The image processing apparatus according to claim 3, wherein
An image processing apparatus characterized in that the priority switching storage means has switching information for the number of processes for a plurality of input image data, and switches the priority for each process.